CN110646756A - Quiescent current eliminating circuit and method of nuclear magnetic resonance gradient power amplifier - Google Patents
Quiescent current eliminating circuit and method of nuclear magnetic resonance gradient power amplifier Download PDFInfo
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Abstract
The invention provides a static current eliminating circuit of a nuclear magnetic resonance gradient power amplifier, which comprises an FPGA controller, a first digital-to-analog converter DAC, a proportional resistor, a gradient power amplifier, a measuring resistor and a gradient coil which are sequentially connected in series, wherein the output end of the gradient coil is grounded through a Blank switch, the FPGA controller is also connected with a second digital-to-analog converter DAC, and the output end of the second digital-to-analog converter DAC is connected to the input end of the gradient power amplifier through an offset proportional resistor. The invention leads the quiescent current to be zero by a method of iteratively detecting the quiescent current and calculating the feedback voltage, and simultaneously uses a Blank switch to isolate the gradient power amplifier and the gradient coil loop, blocks the output of the quiescent current and becomes an ideal quiescent current-free gradient power amplifier which is not influenced by external signals.
Description
Technical Field
The invention relates to a static current eliminating circuit and a method of a nuclear magnetic resonance gradient power amplifier.
Background
The nuclear magnetic resonance spectrometer is developed and produced by applying the nuclear magnetic resonance principle, and is characterized in that a nuclear magnetic resonance phenomenon of a nuclear of a measured object is excited by transmitting high-power radio-frequency pulses to the measured object placed in a uniform strong magnetic field, and nuclear magnetic resonance signals of a target sample area or a frequency spectrum area are obtained by methods such as accumulation, phase coding, gradient selection and the like. The phase encoding and gradient selection method usually outputs pulse current with specified power through a gradient power amplifier, the current forms a gradient magnetic field with linear change in a gradient coil, so that the resonance characteristic of the magnetic field of each region of the tested sample in the direction Z, X, Y is accurately encoded, and the nuclear magnetic resonance signal of the target sample region or the frequency spectrum region is accurately selected. In order to realize the accuracy of selection, the pulse current output by a gradient power amplifier of the nuclear magnetic resonance spectrometer is objectively required to have good linearity, high precision, accurate shape and good positive and negative pulse symmetry.
In the nuclear magnetic resonance spectrometer, a gradient power amplifier is used as an analog power amplification part, the output of the gradient power amplifier is directly connected with a gradient coil arranged in the center of a magnet, a radio frequency coil is arranged in the gradient coil in a short distance, and the nuclear magnetic resonance spectrometer has the following requirements on a gradient system in actual work:
1) the output of the gradient power amplifier is in the form of pulses, and when no pulse is output, the ideal output current of the gradient power amplifier should be 0. The gradient power amplifier is used as an analog power component, the interior of the gradient power amplifier is composed of a large number of operational amplifiers, power tubes and the like, analog devices such as the operational amplifiers, the power tubes and the like have inherent characteristics of output bias, when the input voltage of the gradient power amplifier is 0, the gradient power amplifier still can output static current which is not 0, and according to different characteristics of the analog devices, the static current is changed from microampere to milliampere. When the quiescent current of the gradient power amplifier flows through the gradient coil, the gradient coil generates Z, X or Y-direction magnetic field, so that the magnetic field uniformity of the superconducting magnet is destroyed.
2) When weak quiescent current exists in the gradient power amplifier, compensation can be performed through room-temperature shimming, but the compensation is constant and can not be changed in the nuclear magnetic test process, and the change of the gradient quiescent current can cause the compensation failure. The gradient power amplifier is used as an analog circuit, when the state of the power supply voltage changes, such as drift, the quiescent current of the gradient power amplifier changes, so that the compensation fails, and particularly when a nuclear magnetic resonance spectrometer is tested for a long time, the accumulated quiescent current drift can cause the test result to be seriously deteriorated.
3) The output of the gradient power amplifier should not be affected by other components in the nmr spectrometer. In a nuclear magnetic resonance spectrometer, a gradient coil is not only a transmitting coil of a gradient field, but also an audio receiving coil, the gradient coil can receive radio frequency pulses of a radio frequency coil arranged in the middle of the gradient coil and interference signals of an external space, the signals are input into a gradient power amplifier through a cable to enable output current of the gradient power amplifier to fluctuate, and simultaneously interference pulses are generated and output to the gradient coil, so that the magnetic field is seriously deteriorated, the quality of a test signal is reduced, and even a test result is wrong.
4) The gradient power amplifier has good linearity and the output shape must be accurate. Nuclear magnetic resonance (nmr) often uses a plurality of gradient pulses whose output magnitudes are in a precise proportional relationship to perform gradient encoding on a sample under test. In fact, the gradient power amplifier has a quiescent current, so that the gradient pulse which theoretically needs a strict proportional relation deviates from the proportional relation of the theory, the shape pulse deviates from an ideal function shape, and the quiescent current of the gradient power amplifier is objectively required to reach microampere level.
In order to meet the requirements, the method in the prior art comprises the following steps:
1) since the quiescent current is always present and variable, it can only be reduced and cannot be eliminated by optimizing the device, and two methods are generally adopted for eliminating:
a. measuring the magnitude of the quiescent current once every interval of time, and setting the bias current in a digital control value of the gradient current by a software method to eliminate the bias current;
b. additional currents are generated between each nuclear magnetic examination through the X, Y, Z direction of the room temperature shim to cancel the magnetic field generated by the gradient quiescent current in the corresponding direction.
2) In order to avoid the gradient coil receiving the external interference signal, a low-pass filter is often connected in series between the cables connecting the gradient power amplifier and the gradient coil to filter the interference of the high-frequency signal emitted by the radio frequency coil.
The prior art has the following disadvantages:
1) the method for measuring the quiescent current at intervals is usually carried out manually, and measured values are recorded in control software, because the implemented time has uncertainty, the time point is difficult to fix, professional maintenance personnel are required for measurement, the method is difficult to operate by ordinary users, and the quiescent current measurement cannot be carried out in the process of carrying out long-time nuclear magnetic testing.
2) The magnetic field generated by the static current in the direction X, Y, Z is counteracted by the room temperature shimming method, so that the influence of the static current can be eliminated in a short time, but when the static current changes, the shimming cannot be carried out in time, and the influence of the static current cannot be completely eliminated. Since shimming cannot be performed during nuclear magnetic detection, nuclear magnetic detection with longer time will suffer from more serious influence of quiescent current, resulting in poor quality of nuclear magnetic detection and even data invalidity.
3) Because the gradient power amplifier works in an audio frequency range, the size of the filter is large by a method of eliminating external interference through the filter connected in series, the whole structure of the system becomes complicated, the filter cannot eliminate external interference signals in the audio frequency range, the filter only has a certain inhibiting effect on out-of-band signals, and a part of interference signals still enter the gradient power amplifier, so that the quiescent current of the gradient power amplifier is changed.
Disclosure of Invention
The invention provides a static current-free nuclear magnetic resonance gradient power amplifier and a static current elimination circuit and method, wherein a Blank switch is used for isolating a gradient power amplifier and a gradient coil loop, the output of static current is blocked, the influence of external signals on the gradient power amplifier is avoided, and meanwhile, the static current tends to zero by a method of iteratively detecting the static current and calculating feedback voltage, so that the gradient power amplifier becomes an ideal static current-free gradient power amplifier which is not influenced by the external signals.
The technical scheme of the invention is realized as follows:
the static current eliminating circuit of the nuclear magnetic resonance gradient power amplifier comprises an FPGA controller 1, a first digital-to-analog converter DAC2, a proportional resistor 4, a gradient power amplifier 7, a measuring resistor 8 and a gradient coil 15 which are sequentially connected in series, wherein the input end and the output end of the gradient power amplifier 7 are connected with a feedback proportional resistor 6 in parallel, and the gradient coil 15 is connected with the ground through a Blank switch 16.
Preferably, a measuring resistor 8 is further connected between the output end of the gradient power amplifier 7 and the gradient coil 15, and two input ends of the differential amplifier 9 are respectively connected to two ends of the measuring resistor 8.
Preferably, the output end of the differential amplifier 9 is connected to the immobile end of the first single-pole double-throw switch 10, the first mobile end of the first single-pole double-throw switch 10 is connected to the input end of the first feedback amplifier 11, the output end of the first feedback amplifier 11 is connected to the first mobile end of the second single-pole double-throw switch 13, the immobile end of the second single-pole double-throw switch 13 is connected to the input end of the analog-to-digital converter ADC14, and the output end of the analog-to-digital converter ADC14 is connected to the FPGA controller 1.
Preferably, the second moving terminal of the first single-pole double-throw switch 10 is connected to the input terminal of a second feedback amplifier 12, and the output terminal of the second feedback amplifier 12 is connected to the second moving terminal of a second single-pole double-throw switch 13.
Preferably, the amplification factor of the first feedback amplifier 11 is larger than that of the second feedback amplifier 12, the first feedback amplifier 11 is used for detecting quiescent current smaller than 1mA, and the second feedback amplifier 12 is used for detecting gradient current larger than 1A.
A static current eliminating method of a nuclear magnetic resonance gradient power amplifier is characterized in that an FPGA controller (1) receives external gradient control data and drives a first digital-to-analog converter DAC2 to generate a voltage waveform, the voltage is amplified by a proportional power amplifier composed of a proportional resistor (4), a feedback proportional resistor (6) and a gradient power amplifier (7) to output a gradient current I, the gradient current I is output to a gradient coil (15), and a gradient magnetic field is formed in the gradient coil (15), the FPGA controller (1) also drives a second digital-to-analog converter DAC3 to generate a reverse feedback voltage delta D according to an error current delta D, and the feedback voltage delta D is input to the gradient power amplifier (7) after passing through an offset proportional resistor (5) to eliminate the static current of the gradient power amplifier (7).
Preferably, the method specifically comprises the following steps:
s1, in a t0 period, the gradient power amplifier 7 works in a gradient output mode to output a gradient current I, the Blank switch 16 is controlled by an external signal, the FPGA controller 1 receives external gradient control data and drives the first digital-to-analog converter DAC2 to generate a voltage waveform, the gradient power amplifier 7 is powered on or triggered by the external signal, the FPGA controller 1 is switched to a static current regulation mode, and the period of t1 is entered;
in the time period of S2 and t1, the FPGA controller 1 turns off the gradient control signal and Blank switch 16 signal input from the outside, sets the Blank switch 16 to 0 and turns off, so that the current output of the gradient power amplifier is 0, and clears the outputs of the first digital-to-analog converter DAC2 and the second digital-to-analog converter DAC 3;
in the time period of S3 and t2, the FPGA controller 1 switches the first single-pole double-throw switch 10 and the second single-pole double-throw switch 13 to the first feedback amplifier 11, so that the voltage on the measuring resistor 8 is input to the analog-to-digital converter ADC 14; the FPGA controller (1) continuously acquires the voltage value when the current output is 0 through the analog-to-digital converter ADC14, and records the value as a static current adjustment target value DZero；
t2 for a specified time to ensure the target value DZeroStabilize, and then proceed to time t 3.
In the period S4 and t3, the Blank switch 16 is set to be turned on 1, so that the quiescent current of the gradient power amplifier flows out, and the output quiescent current magnitude D is continuously detected through the first feedback amplifier 11 and the analog-to-digital converter ADC14Current；
The FPGA controller (1) calculates an error current delta D: error current Δ D ═ quiescent current DCurrentQuiescent current adjustment target value DZero；
The FPGA controller (1) controls the second digital-to-analog converter DAC (3) to generate an inverted error feedback voltage delta D according to the error current delta D, and the error feedback voltage delta D passes through the offset proportional resistor (5) and then is input to the gradient power amplifier (7) to counteract the quiescent current DCurrentTo eliminate quiescent current;
at the time interval S5 and t4, the output of the DAC3 of the second digital-to-analog converter is maintained, the Blank switch 16 is set to 0 and is turned off, the ADC14 stops collecting, the first single-pole double-throw switch 10 and the second single-pole double-throw switch 13 are switched to the second feedback amplifier 12, the quiescent current adjustment mode exits after the specified time is continued, and the period t5 is entered;
in the time periods of S6 and t5, the gradient power amplifier 7 works in the gradient output mode, the error feedback voltage- Δ D calculated in the time period of t3 is maintained, the FPGA controller 1 accesses the gradient control signal and Blank switch signal input from the outside, the gradient power amplifier is controlled by the external controller to work, and the analog-to-digital converter ADC14 continuously collects and monitors the output gradient waveform.
Preferably, in step S3, the FPGA controller (1) continuously adjusts the target value D for the collected quiescent currentZeroPerforming average calculation, and setting the average value as an adjustment target value DZeroAdjustment of the target value D of the quiescent currentZeroThe bias voltage of the detection circuit is detected when the corresponding output current is 0.
Preferably, in step S4, if the error current Δ D is greater than the set threshold, the error feedback value is iteratively calculated to reduce the quiescent current, and the feedback process is as follows:
a. sending the error current delta D to a PID calculation module of the FPGA controller (1) and calculating a control value of a DAC (3);
b. writing the calculated control value to the second digital-to-analog converter DAC (3);
c. the voltage generated by the second digital-to-analog converter DAC (3) forms a current in the gradient power amplifier (7) in the direction opposite to the actual quiescent current, so that the quiescent current is cancelled;
d. repeatedly collecting the quiescent current, calculating the error current delta D and writing a new feedback value until the magnitude D of the quiescent currentCurrentLess than the threshold.
Preferably, in step S4, if the error current Δ D is smaller than the threshold, the calculation of the new feedback value is stopped, and the quiescent current is continuously monitored for t seconds, if the magnitude of the quiescent current D is smaller than the thresholdCurrentContinuing to remain less than the threshold, t4 is entered,otherwise, step S4 is repeated until the error current Δ D meets the threshold requirement within t seconds.
The invention has the following beneficial effects: a Blank switch is adopted to isolate the gradient power amplifier, the output and the gradient coil, so that the static current cannot be output, the influence of the static current on a magnetic field is avoided, and the abnormal gradient output or the change of the static current caused by external factors such as a radio frequency coil and the like is also prevented. Meanwhile, a static current acquisition and feedback loop is formed by adopting a differential measurement resistor, a high-gain amplifier, a high-precision analog-to-digital converter ADC and a digital-to-analog converter DAC, and the static current is automatically eliminated by iteration through a PID algorithm, so that the output static current of the gradient power amplifier is reduced to microampere level, and the output of the gradient power amplifier is ensured to keep accurate shape and symmetry; the quiescent current monitoring and eliminating system is operated automatically, is convenient to use, and realizes an ideal gradient power amplifier with high linearity, high symmetry and no quiescent current.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic block diagram of the circuit of the present invention.
FIG. 2 is a timing diagram of a static current adjustment.
Fig. 3 is a flow chart of the adjustment of the quiescent current.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the following embodiments of the present invention, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the quiescent current cancellation circuit of a nuclear magnetic resonance gradient power amplifier includes an FPGA controller 1, a first digital-to-analog converter DAC2, a proportional resistor 4, a gradient power amplifier 7, a measuring resistor 8, and a gradient coil 15, which are connected in series in sequence, wherein an input end and an output end of the gradient power amplifier 7 are connected in parallel with a feedback proportional resistor 6, and the gradient coil 15 is connected to ground through a Blank switch 16.
The FPGA controller 1 is further connected to an input of a second digital-to-analog converter DAC3, an output of said second digital-to-analog converter DAC3 being connected to an offset scaling resistor 5, said offset scaling resistor 5 also being connected to an input of the gradient power amplifier 7. A measuring resistor 8 is connected between the output end of the gradient power amplifier 7 and the gradient coil 15, and two input ends of the differential amplifier 9 are respectively connected to two ends of the measuring resistor 8.
The output end of the differential amplifier 9 is connected to the motionless end of a first single-pole double-throw switch 10, the first motional end of the first single-pole double-throw switch 10 is connected to the input end of a first feedback amplifier 11, the output end of the first feedback amplifier 11 is connected to the first motional end of a second single-pole double-throw switch 13, the motionless end of the second single-pole double-throw switch 13 is connected to the input end of an analog-to-digital converter ADC14, and the output end of the analog-to-digital converter ADC14 is connected to the FPGA controller 1; the second moving terminal of the first single-pole double-throw switch 10 is connected to the input terminal of a second feedback amplifier 12, and the output terminal of the second feedback amplifier 12 is connected to the second moving terminal of a second single-pole double-throw switch 13.
The amplification factor of the first feedback amplifier 11 is greater than that of the second feedback amplifier 12, the first feedback amplifier 11 is used for detecting a quiescent current below 1mA, the second feedback amplifier 12 is used for detecting a gradient current above 1A, and the maximum output of the first feedback amplifier 11 and the maximum output of the second feedback amplifier 12 are close to the maximum allowable input of the analog-to-digital converter ADC14, so as to ensure the maximum detection current resolution.
The FPGA controller 1 receives external gradient control data and drives the first DAC2 to generate a voltage waveform, the voltage is amplified by a proportional power amplifier composed of the proportional resistor 4, the feedback proportional resistor 6 and the gradient power amplifier 7 to output a gradient current I, the gradient current I is output to the gradient coil 15 through the measuring resistor 8, and a gradient magnetic field is formed in the gradient coil 15.
The FPGA controller 1 also drives the second digital-to-analog converter DAC3 to generate an inverted constant feedback voltage according to the error current Δ D, and the constant feedback voltage is input to the gradient power amplifier 7 through the offset proportional resistor 5 to eliminate the quiescent current of the gradient power amplifier 7.
In this embodiment, the switching timing of the Blank switch 16 is synchronized with the output of the gradient current I, that is, when the gradient current I is output, the Blank switch 16 is turned on to normally output the gradient current I, and when the gradient current I is not output, the Blank switch 16 is turned off; when the Blank switch 16 is turned off, the quiescent current of the gradient power amplifier is blocked, preventing the quiescent current from flowing to the gradient coil 15; when the Blank switch 16 is opened, the output of the gradient power amplifier is superimposed with the quiescent current and output to the gradient coil to generate a magnetic field.
In the embodiment, the gradient power amplifier 7 is composed of a multi-stage operational amplifier and a power amplifier tube, the operational amplifier and the power amplifier tube have inherent static bias, and when the input of the gradient power amplifier 7 is 0, the output of the gradient power amplifier also has a certain static current, and the current is between a few microamperes and a few tens of milliamperes. The quiescent current causes the following problems: 1) the static current finally forms a gradient magnetic field in Z, X or Y direction with certain intensity in the gradient coil 15, so that the uniformity of the magnetic field is destroyed; 2) the static current is superposed in the normally output gradient current I, so that the finally output gradient current I generates offset, and the shape and the proportional relation of the gradient waveform deviate from a theoretical value.
When a gradient current I flows through the measuring resistor 8, a voltage V ═ I × R is formed across the measuring resistor 8sThe voltage V is detected and amplified by the differential amplifier 9 and selectively output to the first feedback amplifier 11 or the second feedback amplifier 12 via the first single-pole double-throw switch 10. The first feedback amplifier 11 has a large amplification factor and is used for detecting a weak quiescent current smaller than 1 mA; the first feedback amplifier 11 has a small amplification factor and is used for detecting the gradient current of 1A or more in normal output. First feedback amplifier 11 or secondThe outputs of the two feedback amplifiers 12 are fed to an analog-to-digital converter ADC14, which converts the output voltage into a digital signal by an analog-to-digital converter ADC14 under the control of the FPGA controller 1.
The gradient power amplifier 7 operates in two modes: a quiescent current adjustment mode and a gradient output mode.
When the gradient power amplifier works in a quiescent current regulation mode, the first single-pole double-throw switch 10 and the second single-pole double-throw switch 13 are tangential to the first feedback amplifier 11, a weak voltage formed by quiescent current on the measuring resistor 8 is amplified by the differential amplifier 9 and the first feedback amplifier 11, and the voltage of an output signal of the first feedback amplifier 11 is close to the maximum allowable input of the analog-to-digital converter ADC14 within an allowable quiescent current range;
when the gradient power amplifier 7 works in the gradient output mode, the strong voltage formed on the measuring resistor 8 by the gradient currents above the first single-pole double-throw switch 10 and the second single-pole double-throw switch 13 and the tangential second feedback amplifier 12, 1A is amplified by the differential amplifier 9 and the second feedback amplifier 12, and the maximum output voltage is close to the maximum allowable input voltage of the analog-to-digital converter ADC 14.
A static current eliminating method of a nuclear magnetic resonance gradient power amplifier specifically comprises the following steps:
and in the period of S1 and t0, the gradient power amplifier 7 works in the gradient output mode, the Blank switch 16 is controlled by an external signal, the FPGA controller 1 receives external gradient control data and drives the first digital-to-analog converter DAC2 to generate a voltage waveform, the gradient power amplifier 7 is powered on or triggered by receiving the external signal, and the FPGA controller 1 switches to the quiescent current adjustment mode and enters the period of t 1.
In the time period of S2 and t1, the FPGA controller 1 closes the gradient control signal and the Blank switch 16 signal which are input from the outside, sets the Blank switch (16) to 0 and disconnects the current output of the gradient power amplifier to 0, and clears the outputs of the first digital-to-analog converter DAC (2) and the second digital-to-analog converter DAC (3);
in the time period of S3 and t2, the FPGA controller 1 switches the first spdt switch 10 and the second spdt switch 13 to the first feedback amplifier 11, so as to measure the electricity on the resistor 8The voltage is input to an analog-to-digital converter ADC 14; the ADC14 continuously acquires the voltage value when the current output is 0, and records the value as the quiescent current adjustment target value DZero；
The FPGA controller (1) continuously adjusts the target value D of the acquired quiescent currentZeroPerforming average calculation, and setting the average value as an adjustment target value DZeroAdjustment of the target value D of the quiescent currentZeroThe method enables the finally adjusted quiescent current to eliminate errors introduced by the sampling circuit corresponding to the bias voltage of the detection circuit when the output current is 0.
t2 is continued for a specified time to ensure the collected values are stable, and then the t3 period is entered.
In the period S4 and t3, the Blank switch 16 is set to be turned on 1, so that the quiescent current of the gradient power amplifier flows out, and the output quiescent current magnitude D is continuously detected through the first feedback amplifier 11 and the analog-to-digital converter ADC14CurrentAnd the FPGA controller (1) calculates an error current delta D:
error current Δ D ═ quiescent current DCurrentQuiescent current adjustment target value DZero
Wherein DCurrentThe sum of the voltage formed by the quiescent current of the gradient power amplifier at the sense resistor 8 and the bias voltage of the feedback sense circuit part is sensed, DZeroThe difference value of the bias voltage of the feedback detection circuit and the error current delta D is the error current delta D, namely the static current exists in the actual gradient power amplifier circuit, the FPGA controller 1 calculates a feedback value by using a PID algorithm according to the error current delta D, drives the second digital-to-analog converter DAC3 to generate a reverse error current delta D shape, passes through the bias proportional resistor 5, then is input to the gradient power amplifier 7, and repeats iteration to finally reduce the static current to the uA level.
In the processes of detecting the quiescent current and calculating the feedback voltage, if the error current delta D is larger than a set threshold value, iteratively calculating an error feedback value to reduce the quiescent current, wherein the calculation process is as follows:
a. sending the error current delta D to a PID calculation module of the FPGA controller (1) and calculating a control value of a DAC (3);
b. writing the calculated control value to the second digital-to-analog converter DAC (3);
c. the voltage generated by the second digital-to-analog converter DAC (3) forms a current in the gradient power amplifier (7) in the direction opposite to the actual quiescent current, so that the quiescent current is cancelled;
d. repeatedly collecting the quiescent current, calculating the error current delta D and writing a new feedback value until the magnitude D of the quiescent currentCurrentLess than the threshold.
In the process of detecting the quiescent current and calculating the feedback voltage, if the error current delta D is less than the threshold value, stopping calculating a new feedback value, continuously monitoring the quiescent current for t seconds, and if the magnitude D of the quiescent currentCurrentAnd continuously keeping the error current delta D smaller than the threshold value, entering t4, otherwise, repeating the iterative calculation step until the error current delta D meets the threshold value requirement within t seconds.
At the time interval S5 and t4, the output of the DAC3 of the second digital-to-analog converter is maintained, the Blank switch 16 is set to 0 and is turned off, the ADC14 stops collecting, the first single-pole double-throw switch 10 and the second single-pole double-throw switch 13 are switched to the second feedback amplifier 12, the quiescent current adjustment mode exits after the specified time is continued, and the period t5 is entered;
in the time periods of S6 and t5, the gradient power amplifier 7 works in a gradient output mode, the error current Δ D calculated in the time period of t3 is maintained, the FPGA controller 1 is connected to an externally input gradient control signal and a Blank switch signal, the gradient power amplifier is controlled by an external controller to work, the analog-to-digital converter ADC14 continuously collects the signals, and monitors the output gradient waveform to judge the correctness of the output waveform, and the received gradient waveform is transmitted through the communication interface and is used for monitoring the working state of the gradient system.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. The static current eliminating circuit of the nuclear magnetic resonance gradient power amplifier comprises an FPGA controller (1), a first digital-to-analog converter DAC (2), a proportional resistor (4), a gradient power amplifier (7), a measuring resistor (8) and a gradient coil (15) which are sequentially connected in series, wherein the input end and the output end of the gradient power amplifier (7) are connected with a feedback proportional resistor (6) in parallel, and the gradient coil (15) is connected with the ground through a Blank switch (16).
2. The quiescent current cancellation circuit of a nuclear magnetic resonance gradient power amplifier according to claim 1, characterized in that a measuring resistor (8) is further connected between the output terminal of the gradient power amplifier (7) and the gradient coil (15), and two input terminals of the differential amplifier (9) are respectively connected to two ends of the measuring resistor (8).
3. The quiescent current cancellation circuit of a nuclear magnetic resonance gradient power amplifier according to claim 2, characterized in that the output terminal of said differential amplifier (9) is connected to the stationary terminal of a first single-pole double-throw switch (10), the first moving terminal of the first single-pole double-throw switch (10) is connected to the input terminal of a first feedback amplifier (11), the output terminal of said first feedback amplifier (11) is connected to the first moving terminal of a second single-pole double-throw switch (13), the stationary terminal of said second single-pole double-throw switch (13) is connected to the input terminal of an analog-to-digital converter (ADC) (14), and the output terminal of said analog-to-digital converter (ADC) (14) is connected to the FPGA controller (1).
4. A quiescent current cancellation circuit for a nuclear magnetic resonance gradient power amplifier according to claim 3, wherein the second moving terminal of said first single-pole double-throw switch (10) is connected to the input terminal of a second feedback amplifier (12), and the output terminal of said second feedback amplifier (12) is connected to the second moving terminal of a second single-pole double-throw switch (13).
5. The quiescent current cancellation circuit of a nuclear magnetic resonance gradient power amplifier according to claim 4, wherein the amplification of said first feedback amplifier (11) is larger than that of said second feedback amplifier (12), said first feedback amplifier (11) being adapted to detect quiescent currents below 1mA and said second feedback amplifier (12) being adapted to detect gradient currents above 1A.
6. A static current eliminating method of nuclear magnetic resonance gradient power amplifier, an FPGA controller (1) receives external gradient control data and drives a first digital-to-analog converter DAC (2) to generate a voltage waveform, the voltage is amplified by a proportional power amplifier composed of a proportional resistor (4), a feedback proportional resistor (6) and a gradient power amplifier (7) to output a gradient current I, the gradient current I is output to a gradient coil (15), and a gradient magnetic field is formed in the gradient coil (15), the method is characterized in that the FPGA controller (1) also calculates a feedback value by a PID algorithm according to an error current delta D and drives a second digital-to-analog converter DAC (3) to generate a reverse feedback voltage delta D, the feedback voltage delta D is input to the gradient power amplifier (7) after passing through an offset proportional resistor (5) and iterates repeatedly, eventually reducing the quiescent current to the uA level.
7. The method of claim 6, further comprising the steps of:
s1, in a t0 period, a gradient power amplifier (7) works in a gradient output mode to output a gradient current I, a Blank switch (16) is controlled by an external signal, an FPGA controller (1) receives external gradient control data and drives a first digital-to-analog converter DAC (2) to generate a voltage waveform, the gradient power amplifier (7) is electrified or triggered by the external signal, the FPGA controller (1) is switched to a static current regulation mode, and the period enters a t1 period;
in the S2 period, t1 period, the FPGA controller (1) closes the gradient control signal and Blank switch (16) signal input from the outside, sets the Blank switch (16) to 0 and disconnects, so that the current output of the gradient power amplifier is 0, and clears the outputs of the first digital-to-analog converter DAC (2) and the second digital-to-analog converter DAC (3);
in the S3 and t2 period, the FPGA controller (1) switches a first single-pole double-throw switch (10) and a second single-pole double-throw switch (13) to a first feedback amplifier (11), so that the voltage on the measuring resistor (8) is input to an analog-to-digital converter (ADC) (14); the FPGA controller (1) continuously acquires a voltage value when the current output is 0 through an analog-to-digital converter (ADC) (14), and records the voltage value as a static current adjustment target value DZero；
t2 for a specified time to ensure the target value DZeroStabilize accurately and then enter the period t 3.
In the S4 and t3 period, the FPGA controller (1) turns on the Blank switch (16) to 1, so that the quiescent current of the gradient power amplifier flows out, and the output quiescent current D is continuously detected through the first feedback amplifier (11) and the analog-to-digital converter ADC (14)Current；
The FPGA controller (1) calculates an error current delta D:
error current Δ D ═ quiescent current DCurrentQuiescent current adjustment target value DZero
The FPGA controller (1) calculates a feedback value by using a PID algorithm according to the error current delta D, controls the second digital-to-analog converter DAC (3) to generate an inverted error feedback voltage delta D, inputs the error feedback voltage delta D to the gradient power amplifier (7) after passing through the offset proportional resistor (5), iterates repeatedly, and converts the quiescent current DCurrentDecrease to a threshold;
in the S5 and t4 periods, the output of a DAC (3) of the second digital-to-analog converter is kept, a Blank switch (16) is set to be 0 and is disconnected, an ADC (14) of the analog-to-digital converter stops collecting, a first single-pole double-throw switch (10) and a second single-pole double-throw switch (13) are switched to a second feedback amplifier (12), the static current regulation mode is exited after the specified time is continued, and the period is t 5;
in the S6 and t5 periods, the gradient power amplifier (7) works in a gradient output mode, the error feedback voltage-delta D calculated in the t3 period is kept, the FPGA controller (1) is connected with an externally input gradient control signal and a Blank switch signal, the gradient power amplifier is controlled to work by the external controller, and meanwhile, the analog-to-digital converter ADC (14) continuously collects and monitors an output gradient waveform.
8. The quiescent current cancellation method of nuclear magnetic resonance gradient power amplifier according to claim 7, characterized in that in step S3, the FPGA controller (1) continuously adjusts the target value D for the acquired quiescent currentZeroPerforming average calculation, and setting the average value as an adjustment target value DZeroAdjustment of the target value D of the quiescent currentZeroThe bias voltage of the detection circuit is detected when the corresponding output current is 0.
9. The method of claim 7, wherein in step S4, if the error current Δ D is greater than the predetermined threshold, the error feedback value is iteratively calculated to reduce the quiescent current, and the calculation procedure is as follows:
a. sending the error current delta D to a PID calculation module of the FPGA controller (1) and calculating a control value of a DAC (3);
b. writing the calculated control value to the second digital-to-analog converter DAC (3);
c. the voltage generated by the second digital-to-analog converter DAC (3) forms a current in the gradient power amplifier (7) in the direction opposite to the actual quiescent current, so that the quiescent current is cancelled;
d. repeatedly collecting the quiescent current, calculating the error current delta D and writing a new feedback value until the magnitude D of the quiescent currentCurrentLess than the threshold.
10. The method of claim 7, wherein in step S4, if the error current Δ D is smaller than the threshold, the calculation of the new feedback value is stopped, the quiescent current is monitored for t seconds, and if the magnitude of the quiescent current D is smaller than the threshold, the quiescent current is monitored for t secondsCurrentAnd continuously keeping the current value less than the threshold value, entering t4, otherwise, repeating the step S4 until the error current Delta D meets the threshold value requirement within t seconds.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111857218A (en) * | 2020-07-09 | 2020-10-30 | 吉林大学 | Two-stage low-noise large-current high-resolution numerical control current source |
| CN116578160A (en) * | 2023-07-13 | 2023-08-11 | 国仪量子(合肥)技术有限公司 | Magnetic field intensity control device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111857218A (en) * | 2020-07-09 | 2020-10-30 | 吉林大学 | Two-stage low-noise large-current high-resolution numerical control current source |
| CN116578160A (en) * | 2023-07-13 | 2023-08-11 | 国仪量子(合肥)技术有限公司 | Magnetic field intensity control device |
| CN116578160B (en) * | 2023-07-13 | 2023-09-12 | 国仪量子(合肥)技术有限公司 | Magnetic field intensity control device |
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