A kind of measurement apparatus with bicyclic alc circuit
Technical field
The present invention relates to signal testing, field of measuring technique, more particularly to a kind of measurement with bicyclic alc circuit
Device.
Background technology
Radio-frequency signal source is a kind of common equipment in measurement, testing field.Radio-frequency signal source Main Function is generation one
The radiofrequency signal of frequency range and amplitude range is determined, as the excitation or reference of device under test.Also various modulation can be exported
Signal, such as FM (Frequency Modulation, frequency modulation), AM (Aplitude Modulation, amplitude modulation), PM
(Phase Modulation, phase modulation), IQ, Pulse (pulse) etc., for the debugging of communication apparatus provides basis.Penetrate
The amplitude accuracy of frequency source signal output signal, locking time and stability are one of important indicators of radio-frequency signal source,
And these indexs are usually to come real by alc circuit (Automatic Level Control, automatic level control circuit)
It is existing.Additionally, phase of output signal noise and it is spuious be also radio-frequency signal source important indicator, making an uproar in ALC loops
Sound (or shake) is likely to influence whether this performance.Apparatus output signal amplitude is also required to suitably to adjust, signal
Source internal signal amplitude can also change within the specific limits.The scope and minimum resolution that ALC can be locked be also
The important component of ALC performances.
Most of ALC are made up of a complete loop, mainly there is " detection ", " comparing " and " regulation " 3
Module.During normal work (ALC on), its real-time detection amplitude output signal, the result that will be detected with setting
Range value is compared, the attenuation (or gain) according to comparative result dynamic regulation loop, until output signal width
Degree is equal with setting value.Noise (or shake) in ALC loops can make " regulation " module output attenuatoin amount one
Determine shake in scope, this shake can be added in input signal with noise or spuious form, make final output signal
Phase noise spuious changes a lot.
ALC loops have analog- and digital- two kinds of implementations, and simulation ALC loop speeds are fast, noise is low but control not
Enough intelligence;Digital ALC loops operability and Function Extension ability are stronger, but its noise its speed of service higher is inclined
Low (locking time is partially long).
Patent CN201020696938.9 describes a kind of analog- and digital- bicyclic ALC systems being combined, in mould
Intend increased digital conditioning circuit between ALC ring " detection " and " comparing " module, to expect simultaneously using simulation
The advantage of ALC rings and numeral ALC rings.It is designed primarily to while ALC ring normal works are simulated, will " inspection
Ripple " module (level sensitive circuit) output is changed into digital quantity, and " compares " ginseng of module according to this parameter regulation
Examine voltage.This scheme increased the ability that reference voltage is adjusted according to detecting circuit to simulate ALC.
For most of simulation ALC rings, the sufficiently low analog device of noise can be selected, make the near of ALC introducings
Other noise is spuious sufficiently small, has substantially no effect on output signal performance.For digital ALC, by digital-to-analogue conversion DAC
The limitation of resolution ratio, the shake of " regulation " module can be than larger, and this chattering frequency is related to the bandwidth of ALC loops,
And be difficult with the mode of wave filter and eliminate, it is to improve DAC resolution ratio to solve this problem most straightforward approach, will be trembled
Dynamic amplitude reduction is in acceptable scope.For most of ALC, the locking time of loop is that another is heavy
The renewal speed of the index wanted, ADC and DAC can directly influence the locking time of loop.Shorter locking time
Renewal speed faster is needed, but fast and high resolution the DAC of renewal speed is relatively costly, and disclosure satisfy that signal
The high-speed DAC of source ALC adjustable extents and accuracy requirement is difficult to find;The mode cascaded using multiple high-speed DACs
Resolution ratio can be increased, but extra cost can be increased, thereby increases and it is possible to there is the asynchronous switching point for causing of control signal and tremble
Dynamic problem.
The content of the invention
A kind of measurement apparatus with bicyclic alc circuit are the embodiment of the invention provides, signal source ALC can be met
The demand of big adjustable extent, high-resolution and low jitter.
Bicyclic alc circuit includes the first alc circuit and the second alc circuit;Wherein, the first alc circuit includes
First adjustable radio frequency attenuator, power divider 102, wave detector 103, analog-to-digital conversion module 104, digit chip
105 and first D/A converter module 106;Second alc circuit includes power divider 102, wave detector 103, mould
Number modular converter 104, digit chip 105, the second adjustable radio frequency attenuator and the second D/A converter module 108;
The input of second adjustable radio frequency attenuator as bicyclic alc circuit input, the second tunable radio frequency
The output end of attenuator is connected with the input of the first adjustable radio frequency attenuator, for the width to input radio frequency signal 1A
Degree is decayed;
The output end of first adjustable radio frequency attenuator is connected with the input of power divider 102, for input
The amplitude of radiofrequency signal 1A is further decayed;
The power divider 102 will be divided into the first output and penetrates by the input radio frequency signal 1A after the decay of amplitude twice
The output radiofrequency signals of frequency signal 1B and second;First output end of power divider 102 is used as bicyclic alc circuit
Output end, export radiofrequency signal 1B for exporting first;Second output end and wave detector of power divider 102
103 input connection, for the second output radiofrequency signal to be exported to wave detector 103;
The output end of the wave detector 103 is connected with the input of analog-to-digital conversion module 104, for being penetrated to the second output
Frequency signal carries out detection, obtains detecting circuit;
The output end of the analog-to-digital conversion module 104 is connected with the input of digit chip 105, for by detecting circuit
Analog-to-digital conversion is carried out, digitized detecting circuit is obtained;
First output end of the digit chip 105 is connected with the input of the first D/A converter module 106, and second is defeated
Go out end to be connected with the input of the second D/A converter module 108;
The digit chip 105 is used to determine according to digitized detecting circuit the control voltage of adjustable radio frequency attenuator,
When the control voltage of the first adjustable radio frequency attenuator is defined as, the work of the first alc circuit;Can when being defined as second
When adjusting the control voltage of radio frequency attenuator, the work of the second alc circuit;
The output end of first D/A converter module 106 is connected with the adjustable side of first adjustable radio frequency attenuator,
For the control voltage of the first adjustable radio frequency attenuator to be carried out into digital-to-analogue conversion;
The output end of second D/A converter module 108 is connected with the adjustable side of second adjustable radio frequency attenuator,
For the control voltage of the second adjustable radio frequency attenuator to be carried out into digital-to-analogue conversion.
In one embodiment, the digit chip 105 includes comparison module 201, error judgment module 202, the
One compares integrator 203 and second compares integrator 205;
The input of the comparison module 201 as digit chip 105 input, the output end of comparison module 201
Input with error judgment module 202 is connected, for digitized detecting circuit and reference voltage to be compared,
Obtain error current voltage;
The input that first output end of the error judgment module 202 compares integrator 203 with first is connected, error
The input that second output end of judge module 202 compares integrator 205 with second is connected, for error current electricity
The size of pressure judged, if error current voltage is more than default error amount, by error current voltage output to the
One compares integrator 203;If error current voltage is less than default error amount, by error current voltage output to the
Two compare integrator 205;
Described first compares the output end of integrator 203 as the first output end of the digit chip 105, for right
Error current voltage is integrated;
Described second compares the output end of integrator 205 as the second output end of the digit chip 105, for right
Error current voltage is integrated.
In one embodiment, the digit chip 105 also includes the logafier 302 of zero point module 301 and first;
The input of the zero point module 301 as digit chip 105 input, the zero point module 301 it is defeated
Go out end to be connected with the input of the first logafier 302, school is carried out for the zero point to digitized detecting circuit
It is accurate;
The output end of first logafier 302 is connected with the input of comparison module 201, for zero point school
Digitized detecting circuit after standard carries out logarithmic amplification.
In one embodiment, the digit chip 105 also include zero point module 301, linearity compensation module 402,
Sampling filter module 403 and extraction of square root module 404;
The input of the zero point module 301 as digit chip 105 input, the zero point module 301 it is defeated
Go out end to be connected with the input of linearity compensation module 402, school is carried out for the zero point to digitized detecting circuit
It is accurate;
The output end of the linearity compensation module 402 is connected with the input of sampling filter module 403, for zero
The non-linear of digitized detecting circuit after point calibration is compensated;
The output end of the sampling filter module 403 is connected with the input of extraction of square root module 404, for non-to carrying out
Digitized detecting circuit after linear compensation carries out over-sampling;
The output end of the extraction of square root module 404 is connected with the input of comparison module 201, for by after over-sampling
Detecting circuit is reduced to voltage amplitude by power magnitude.
In one embodiment, described first compare integrator 203 and second compare integrator 205 include amplifier
And accumulator;
The input of the amplifier is connected with the output end of error judgment module 202, for error current voltage to be entered
Row amplifies;
The input of the accumulator is connected with the output end of amplifier, and the output end of the accumulator is used as the numeral
The output end of chip 105, for being added up to the error current voltage after amplification, obtains final error voltage.
In one embodiment, the digit chip 105 also includes first processing module 204 and Second processing module
206;
The output end that the input of the first processing module 204 compares integrator 203 with first is connected, and described first
The output end of processing module 204 as the digit chip the first output end, for comparing integrator by first
Final error voltage after 203 integrations is processed accordingly;
The output end that the input of the Second processing module 206 compares integrator 205 with second is connected, and described second
The output end of processing module 206 as the digit chip the second output end, for comparing integrator by second
Final error voltage after 205 integrations is processed accordingly.
In one embodiment, the first processing module 204 include first switch 308, error voltage module 309,
Preset voltage module 310, first adder and voltage transformation module 311;
When alc circuit normal work, the first switch 308 is closed;When alc circuit open loop works, institute
First switch 308 is stated to open;
The error voltage module 309 is used to store preset error voltage or compare integrator 203 by first to integrate
Final error voltage afterwards;
The preset voltage module 310 is used to store preset voltage;
The first adder is used to be added final error voltage with preset voltage, obtains the first adjustable radio frequency attenuator
Control voltage;
The input of the voltage transformation module 311 is connected with the output end of adder, for correcting the first tunable radio frequency
It is non-linear between the attenuation and control voltage of attenuator.
In one embodiment, the first processing module 204 also includes the second logafier 413;
The input of second logafier 413 is connected with the output end of first adder, and second logarithm is put
The output end of big device 413 is connected with the input of the voltage transformation module 311, for decaying to the first tunable radio frequency
The control voltage of device carries out logarithmic amplification.
In one embodiment, the Second processing module 206 includes second switch 314, second adder and optional
Switch 317;
Compare the error voltage after integrator 203 is integrated by second switch 314 and test voltage 315 by first
As the input of optional switch 317 after addition;When bicyclic ALC normally runs, the ALC of optional switch 317 and the 2nd
Circuit is connected, and exports the control voltage of the second adjustable radio frequency attenuator;When AM is opened, the decay of the second tunable radio frequency
Device is used to realize that AM is modulated.
In one embodiment, the comparison module 201 uses subtracter.
In embodiments of the present invention, two sets of integration modules in digit chip internal build, form two ALC electricity
Road:First alc circuit and the second digital alc circuit, the first alc circuit use the first adjustable radio frequency attenuator
Amplitude output signal is tentatively adjusted, amplitude output signal error is maintained in less scope;Second numeral
ALC loops are further corrected using the second adjustable radio frequency attenuator to the remaining amplitude of output signal, are realized
Relatively low error jitter, meets the demand of the big adjustable extents of signal source ALC, high-resolution and low jitter.
Brief description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, not
Constitute limitation of the invention.In the accompanying drawings:
Fig. 1 is a kind of measurement apparatus structural representation with bicyclic alc circuit provided in an embodiment of the present invention;
Fig. 2 is a kind of digit chip internal structure schematic diagram provided in an embodiment of the present invention;
Fig. 3 is a kind of bicyclic ALC digit chips internal hardware connection figure of logarithmic mode provided in an embodiment of the present invention;
Fig. 4 is a kind of bicyclic ALC digit chips internal hardware connection figure of linear model provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention become more apparent, with reference to implementation method and accompanying drawing,
The present invention is described in further details.Here, exemplary embodiment of the invention and its illustrating for explaining this hair
It is bright but not as a limitation of the invention.
In radio-frequency signal source, need to realize AM functions mostly.AM can use other decay independently of ALC
Device and control unit are realized, to increase control flexibility and lifting AM and ALC performances.General, AM is closed
When AM attenuators be in idle condition.At this point it is possible to change slow characteristic using AM attenuators attenuation,
Build bicyclic digital ALC, lifting means attenuation resolution ratio, the DAC resolution ratio of equivalent lifting ALC.
For the digital ALC problems high to DAC turnover rates and resolution requirement, with reference to the characteristics of radio-frequency signal source,
The present invention proposes a kind of measurement apparatus of bicyclic alc circuit.This scheme has used two independent attenuators to build
Two ALC rings, the adjustable extent of one of attenuator is larger, is used to meet the demand of ALC adjustable extents;
The adjustable damping amount resolution ratio of another attenuator is higher, the demand for meeting ALC high-resolution and low jitter.
Fig. 1 is a kind of measurement apparatus structural representation with bicyclic alc circuit provided in an embodiment of the present invention, such as
Shown in Fig. 1, bicyclic alc circuit includes the first alc circuit and the second alc circuit;Wherein, ALC electricity
Road include the first adjustable radio frequency attenuator 101, power divider 102, wave detector 103, analog-to-digital conversion module 104,
The D/A converter module 106 of digit chip 105 and first;Second alc circuit includes power divider 102, wave detector
103rd, analog-to-digital conversion module 104, digit chip 105, the second adjustable radio frequency attenuator 107 and the second digital-to-analogue conversion mould
Block 108.
Wherein, the input of second adjustable radio frequency attenuator 107 as bicyclic alc circuit input,
The output end of two adjustable radio frequency attenuators 107 is connected with the input of the first adjustable radio frequency attenuator 101, for defeated
The amplitude for entering radiofrequency signal 1A is decayed;
The output end of first adjustable radio frequency attenuator 101 is connected with the input of power divider 102, for right
The amplitude of input radio frequency signal 1A is further decayed;
The power divider 102 will be divided into the first output and penetrates by the input radio frequency signal 1A after the decay of amplitude twice
The output radiofrequency signals of frequency signal 1B and second;First output end of power divider 102 is used as bicyclic alc circuit
Output end, export radiofrequency signal 1B for exporting first;Second output end and wave detector of power divider 102
103 input connection, for the second output radiofrequency signal to be exported to wave detector 103;
The output end of the wave detector 103 is connected with the input of analog-to-digital conversion module 104, for being penetrated to the second output
Frequency signal carries out detection, obtains detecting circuit;
The output end of the analog-to-digital conversion module 104 is connected with the input of digit chip 105, for by detecting circuit
Analog-to-digital conversion is carried out, digitized detecting circuit is obtained;
First output end of the digit chip 105 is connected with the input of the first D/A converter module 106, and second is defeated
Go out end to be connected with the input of the second D/A converter module 108;
The digit chip 105 is used to determine according to digitized detecting circuit the control voltage of adjustable radio frequency attenuator,
When the control voltage of the first adjustable radio frequency attenuator 101 is defined as, the work of the first alc circuit;When being defined as
During the control voltage of two adjustable radio frequency attenuators 107, the work of the second alc circuit;
The output end of first D/A converter module 106 connects with the adjustable side of first adjustable radio frequency attenuator 101
Connect, for the control voltage of the first adjustable radio frequency attenuator 101 to be carried out into digital-to-analogue conversion;
The output end of second D/A converter module 108 connects with the adjustable side of second adjustable radio frequency attenuator 107
Connect, for the control voltage of the second adjustable radio frequency attenuator 107 to be carried out into digital-to-analogue conversion.
Specific, or the first adjustable radio frequency attenuator 107 and the second adjustable radio frequency attenuator 101, that is
The position of the first adjustable radio frequency attenuator and the second adjustable radio frequency attenuator can be exchange, not influence bicyclic so
Alc circuit works.
During specific implementation, the operation principle of bicyclic alc circuit is as follows:
After input radio frequency signal 1A sequentially passes through two adjustable radio frequency attenuators 107 and 101 and power divider 102
Output radiofrequency signal 1B.Wherein power divider 102 distributes to wave detector 103 sub-fraction radiofrequency signal, uses
To extract the amplitude information of output radiofrequency signal 1B.The output signal of wave detector 103 digitizes laggard by ADC104
Enter digit chip 105, digit chip calculates two the control voltage 1D and 1E of attenuator, respectively through DAC106
Corresponding adjustable radio frequency attenuator 101 and 107 is controlled with after 108 outputs.Wherein adjustable radio frequency attenuator 101 can
Adjust attenuation scope larger, but minimum step is also bigger than normal;The adjustable extent of adjustable radio frequency attenuator 107 is smaller, but most
Small stepping is also smaller.Two adjustable radio frequency attenuators can be the attenuator, or knot of different structure or type
The attenuator that structure is identical but operating point is different.
Fig. 2 is a kind of digit chip internal structure schematic diagram provided in an embodiment of the present invention, as shown in Fig. 2 the number
Word chip 105 includes that comparison module 201, error judgment module 202, first are compared integrator 203, second compare
Integrator 205, first processing module 204 and Second processing module 206;
Wherein, the input of comparison module 201 as digit chip 105 input, the output of comparison module 201
End is connected with the input of error judgment module 202;First output end of error judgment module 202 compares product with first
Divide the input connection of device 203, the second output end of error judgment module 202 compares the defeated of integrator 205 with second
Enter end connection;The output end that the input of first processing module 204 compares integrator 203 with first is connected, at first
Manage module 204 output end as the digit chip the first output end, the input of Second processing module 206 with
The second output end connection for comparing integrator 205, the output end of Second processing module 206 is used as the digit chip
Second output end.
The operation principle of digit chip is:
Digitized detecting circuit is compared by comparison module 201 with the reference DAC of setting, obtains error electricity
Pressure;Error judgment module 202 judges that error current voltage larger error current compares integration into first
Added up in device 203, integration output by first processing module 204 carry out nonlinear compensation etc. other treatment after it is defeated
Go out, control the first adjustable radio frequency attenuator 101;During less error current compares integrator 205 into other second
Added up, integration output by Second processing module 206 carry out nonlinear compensation etc. other treatment after export, control
Second adjustable radio frequency attenuator 107.
Error current can be divided into two-way output by error judgment module 202 in real time, it is also possible to according to the mistake for detecting
Whole errors in some time ranges are sent into special modality by difference rule.Larger error current and less current
Error determines according to actual conditions.
First processing module 204 and Second processing module 206 are relevant with specific circuit, can be without this in the middle of reality
Two modules.Now, first compares the output end of integrator 203 as the first output end of the digit chip 105;
Second compares the output end of integrator 205 as the second output end of the digit chip 105.
During specific implementation, this bicyclic ALC uses two adjustable attenuators, and two sets are accumulated in digit chip internal build
Sub-module, forms two ALC loops.One of ALC rings (coarse adjustment ALC rings) using adjustable extent it is big,
The first relatively low adjustable radio frequency attenuator 101 of adjustable accuracy, is tentatively adjusted to amplitude output signal, believes output
Number range error is maintained in less scope.Another ALC loop (fine tuning ALC rings) uses adjustable range
Small, high resolution the second adjustable radio frequency attenuator 107, is further corrected to remaining range error, is realized
Relatively low error jitter.Two ALC loops can run simultaneously, it is also possible to according to error voltage distribution situation timesharing
Between section operation.When ALC just brought into operation or losing lock after, amplitude output signal is larger with setting value deviation, now
Mainly coarse adjustment ALC inscription of loop.When range error is less than to a certain degree, it may appear that less than Rule of judgment
Small error, now fine tuning ALC rings bring into operation.When range error is smaller, the error for detecting is basic
Fine tuning ALC rings are entered, the output voltage of coarse adjustment ALC rings may keep constant the long period.Mistake can also be set
Difference judgment model, the output of another loop keeps constant when making a loop work in two ALC rings.It is bicyclic
When working simultaneously, it is configured without the alternation condition to loop, but need to design two locking models of ALC rings
Enclose and regulations speed, it is to avoid two loops run and cause vibration in the opposite direction simultaneously.During bicyclic alternation not
With the oscillation problem worried between two loops, but need to design loop switching condition and fit system, it is to avoid two rings
Oscillatory type switching between road.
Bicyclic ALC can be realized using the ALC of logarithmic mode, the bicyclic ALC digit chips inside of logarithmic mode is hard
Part is connected as shown in figure 3, can include the logafier of zero point module 301 and first in the digit chip 105
302;The input of zero point module 301 as digit chip 105 input, the output end of zero point module 301 with
The input connection of the first logafier 302;The output end of the first logafier 302 and comparison module 304
Input connection.
During specific implementation, zero point module 301 act as calibrating the zero point of digitized detecting circuit 1C, makes
During proper detected signal amplitude very little (less than minimum measurement signal certain limit), the result into subsequent module is
The a reference value (such as " 0 " or " 1 ") of setting.The reason for needing this module is analog detector and digitizer
On conceptual design a reference value digitlization after may not just when digital scheme benchmark, or due to analog device criticizing
The a reference value of the factor influence distinct device such as amount conformity error has certain deviation.
During specific implementation, in the digit chip 105 first compares integrator 203 and second compares integrator 205
Include amplifier and accumulator;The input of amplifier is connected with the output end of error judgment module 202, for inciting somebody to action
Error current voltage is amplified;The input of accumulator is connected with the output end of amplifier, the output of the accumulator
Hold as the output end of the digit chip 105, for being added up to the error current voltage after amplification, obtain most
Whole error voltage.Wherein, first compares integrator 203 including first order amplifier 306 (form is K2*x+b2)
With accumulator 307;Second compares integrator 205 includes second level amplifier 312 (form is k*x) and accumulator
313。
During specific implementation, the first processing module 204 in the digit chip 105 includes first switch 308, error
Voltage module 309, preset voltage module 310, first adder and voltage transformation module 311;
When alc circuit normal work, the first switch 308 is closed;When alc circuit open loop works, institute
First switch 308 is stated to open;
Error voltage module 309 is used to storing preset error voltage or compares after integrator 203 integrates by first
Final error voltage;
Preset voltage module 310 is used to store preset voltage;
First adder is used to be added final error voltage with preset voltage, obtains the first adjustable radio frequency attenuator 101
Control voltage;
The input of voltage transformation module 311 is connected with the output end of adder, for correcting the decay of the first tunable radio frequency
It is non-linear between the attenuation and control voltage of device 101.
During specific implementation, the Second processing module 206 in digit chip 105 includes second switch 314, the second addition
Device and optional switch 317;
Compare the final error voltage after integrator 203 is integrated by first and pass through second switch 314 and test voltage
As the input of optional switch 317 after 315 additions;When bicyclic ALC normally runs, optional switch 317 and
Two alc circuits are connected, and export the control voltage of the second adjustable radio frequency attenuator 107;When AM is opened, second
Adjustable radio frequency attenuator 107 is used to realize that AM is modulated.
The operation principle of the bicyclic ALC digit chips of logarithmic mode is:
After digitized detecting circuit 1C enters digit chip, subtract each other with zero point module 301 first, put by logarithm
It is compared (subtract each other) with reference voltage DAC304 after big device 302.If error current is larger, optional switch 305
Connected with coarse adjustment ALC loops, error current enters first order amplifier 306, enters by accumulator 307 after amplification
Row is cumulative.Output after cumulative enters error voltage module 309 by the configuration of first switch 308, with preset voltage mould
Block 310 together realizes ALC on, ALC off, ALC hold functions.Error voltage is with preset voltage by first
Adder adds and the control by exporting the first tunable radio frequency (coarse adjustment) attenuator 101 after voltage transformation module 311 is electric
Pressure 1D.If error current is smaller, optional switch 305 is connected with fine tuning ALC rings, and error current is put into the second level
Big device 312, is added up after amplification by accumulator 313.Cumulative input is by the second (changeable) switch 314
As the input of optional switch 317 after being added with test voltage DAC315.When bicyclic ALC normally runs, can
Choosing switch 317 is connected with fine tuning ALC rings, exports the control voltage of the second tunable radio frequency (fine tuning) attenuator 107
1E.When AM is opened, optional switch 317 is connected with AM control voltages module 316, and ALC uses monocyclic control
System, fine tuning ALC attenuators are used to realize that AM is modulated, you can select the input of switch 317 as the control electricity of AM
Pressure.
Optional (error switch) switch 305 can be operated in real-time mode, realize bicyclic while work;Can also divide
Bicyclic alternation is realized in time period switching.
Logafier 302 can be realized using analog circuit outside digit chip.
Bicyclic ALC can be also realized using the ALC of linear model, the bicyclic ALC digit chips inside of linear model is hard
Part connect as shown in figure 4, in digit chip 105 can also include zero point module 401, linearity compensation module 402,
Sampling filter module 403 and extraction of square root module 404;
The input of zero point module 401 as digit chip 105 input, output end and linearity compensation module
402 input connection;The output end of linearity compensation module 402 is connected with the input of sampling filter module 403;
The output end of sampling filter module 403 is connected with the input of extraction of square root module 404;The output of the module 404 that extracts square root
End is connected with the input of comparison module 201, for the detecting circuit after over-sampling to be reduced into voltage by power magnitude
Amplitude.
During specific implementation, zero point module 401 is same with the function phase of zero point module 301.
Linearity compensation module 402 act as non-linear the compensating to wave detector (diode detector etc.).It is former
The logafier (dual slope logarithmic amplifier) of particular design is used mostly in ALC at the same realize logarithmic amplification and
Linearity compensation function, needs separate design herein, it is possible to use quadratic function is realized.
The Main Function of sampling filter module 403 is that over-sampling is carried out to detecting circuit (is using being adopted much larger than Nyquist
The frequency of sample frequency is sampled to input signal), lift detecting circuit significance bit as cost to reduce efficiently sampling rate
Number, this module does not work when AM is opened.This sampling filter is changeable, when and speed higher to resolution requirement is needed
Ask (ALC work) when being not very high, enable over-sampling function;When higher to rate request and resolution requirement is not
(auxiliary AM) closes over-sampling function when very high.
Linear model ALC application conditions and integration be with volt (V) as base unit, attenuator control be still by
What dB forms were realized;It is easy to coordinate with AM, but higher to ADC requirements.The signal stream of linear model ALC
Journey is substantially suitable with the ALC of logarithmic mode, and difference section is described as follows.Digitized detecting circuit and reference electricity
Pressure DAC406 be compared before not by logarithmic amplification, and be the use of linearity compensation module 402, changeable
Sampling filter module 403 and extraction of square root module 404.Second logafier 413 be placed on error voltage with it is pre-
Put after voltage is added and finishes, to realize controlling the logarithmic mode of attenuator.
Error judgment module 407 can also use timesharing switch mode using the pattern of real-time working, realize bicyclic
Switch operating or bicyclic alternation.
Illustrate and use the bicyclic available beneficial effect of alc circuit of the invention:
Monocyclic pattern realizes that -20~10dBm ALC adjustable extents (contain using the DAC of 2MHz turnover rates, 14bit
9kHz~3GHz frequencies and 0~50 degree celsius temperature are compensated), when ALC output amplitudes are smaller, offset signal
There is larger noise signal or spurious signal in 100Hz~100kHz interval probabilities.Noise signal is reachable
- 110dBc/Hz, spurious signal is presented as the obvious spike on radiofrequency signal phase noise curve.Use bicyclic ALC
Afterwards, this noise is less than -120dBc/Hz, and this spurious signal is less than phase noise.
In sum, the present invention in digit chip internal build two sets of integration modules, form two alc circuits:
First alc circuit and the second digital alc circuit, the first alc circuit is using the first adjustable radio frequency attenuator to defeated
Go out signal amplitude tentatively to be adjusted, amplitude output signal error is maintained in less scope;Second numeral ALC
Loop is further corrected using the second adjustable radio frequency attenuator to the remaining amplitude of output signal, is realized relatively low
Error jitter, meets the demand of signal source ALC adjustable extents, high-resolution and low jitter.
Between the adjustable radio frequency attenuator 101 and 107 or the adjustable radio frequency attenuator 101 (or 107) and institute
State and can be provided with the amplitude adjusting device such as amplifier, fixed attenuator between power divider 102.
Obviously, those skilled in the art should be understood that each module or each step of the above-mentioned embodiment of the present invention can be with
Realized with general computing device, they can be concentrated on single computing device, or be distributed in multiple calculating
On the network that device is constituted, alternatively, they can be realized with the executable program code of computing device, so that,
Can be stored in being performed by computing device in storage device, and in some cases, can be being different from
Order herein performs shown or described step, or they are fabricated to each integrated circuit modules respectively, or
Multiple modules or step in them are fabricated to single integrated circuit module to realize by person.So, the embodiment of the present invention
Any specific hardware and software is not restricted to combine.
The preferred embodiments of the present invention are the foregoing is only, is not intended to limit the invention, for the skill of this area
For art personnel, the embodiment of the present invention can have various modifications and variations.It is all within the spirit and principles in the present invention,
Any modification, equivalent substitution and improvements made etc., should be included within the scope of the present invention.