CN106873696A - A kind of self adaptation fast source voltage regulating system - Google Patents
A kind of self adaptation fast source voltage regulating system Download PDFInfo
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- CN106873696A CN106873696A CN201710167757.3A CN201710167757A CN106873696A CN 106873696 A CN106873696 A CN 106873696A CN 201710167757 A CN201710167757 A CN 201710167757A CN 106873696 A CN106873696 A CN 106873696A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The invention discloses a kind of self adaptation fast source voltage regulating system, joint dynamic voltage frequency adjusts (DVFS) and two kinds of regulation strategies of adaptive voltage scaling (AVS), is realized by the relatively slow AVS fine tunings two parts of DVFS Fast Coarses mediation respectively.It is characterized in that：The system includes AVS control modules on DVFS control modules, piece on hardware performance monitoring modular, piece on main circuit system platform, frequency adjuster phase-locked loop pll, out-put supply path PMOS switch group, piece external power managing chip PMIC, performance decision-making module, piece.The method and system reduce the operating voltage and frequency of chip simultaneously, reduce the nargin of chip voltage, compensate for the influence of quick voltage change, reduce the power dissipation overhead of chip.
Description
Technical field
The present invention relates to a kind of voltage-regulation mode, it is related to digital integrated electronic circuit, more particularly to a kind of low power dissipation design skill
Art.
Background technology
Low-power Technology (Low power technology) is used for solving power consumption problem, and power problemses are to determine to rub
Can you continue applicable single factor by law.Low-power Technology can be divided into system-level, logic level from different levels, circuit-level,
Domain level, process level.Present invention design belongs to System-Level Low Power Consumption Design technology.In recent years, as integrated circuit (IC) works
Frequency, integrated level, the continuous improvement of complexity, the power consumption of IC quickly increases, and the raising of power consumption brings a series of reality
Problem：Causing IC running temperatures to rise can cause the operational factor of semiconductor circuit to be drifted about, and influence IC normal works；Power consumption increases
Causing IC running temperatures to rise can shorten the chip life-span；Requirement to system cooling, not only increases system cost, and limit
The further raising of systematic function.
In recent years, both at home and abroad to dynamic voltage frequency adjustment (DVFS) technology research application it is quite varied and into
Ripe, traditional DVFS modes are realized using opened loop control, after the completion of chip design, setting voltage and frequency in the form of a lookup table
The corresponding relation of rate, then the actual working state according to chip choose corresponding working frequency and voltage to search.
Research and application in the world for adaptive voltage scaling (AVS) technology is also very active.Based on on-line monitoring
Influence of the AVS technologies by PVT factors to circuit be all attributed to the change of path delay, then design sequential monitoring in slice single
Unit's monitoring key path time sequence, according to the key path time sequence for monitoring, whether anxiety carries out voltage-regulation.Therefore monitor single
Can unit really reflect that the time delay of true critical path is directly connected to the accuracy of voltage-regulation.
With being continuously increased for integrated level, the fluctuation of supply voltage is increasing, and the fluctuation of supply voltage is main to be pressed by IR
Drop (IR drop) and induced noise di/dt (IR droop) cause.IR pressure drops are the dead resistances that electric power network is flowed through by electric current
Cause, and di/dt noises are then because the stray inductance that parasitic capacitance, resistance are combined causes.The time of these power supply noises
Constant is generally between nanosecond and microsecond.This requires that monitoring unit has sample rate high, and requires there is voltage high
Adjustment feedback speed.Based on monitoring key path time sequence AVS methods voltage-regulation feedback network generally by I2C interfaces with
Outside power management chip connection, its voltage-regulation speed is subject to the electricity of I2C transmission speeds and external power source managing chip
The limitation of pressure regulation stabilized speed, it usually needs the time of some microseconds.
Based on subject matter recited above, the invention provides on a kind of joint DVFS and piece AVS it is quick self-adapted
Supply voltage regulating system, can successfully manage quick voltage fluctuation.
The content of the invention
Goal of the invention：It is an object of the present invention to provide a kind of quick voltage regulating system, carrys out quick compensation chips in work
The influence of PVT (Process, Voltage, the Temperature) deviation being subject in work, can mainly compensate the ripple of supply voltage
It is dynamic.This method overcomes the governing speed problem of AVS regulations, can be widely applied to dedicated IC chip and treatment
Device chip.
Technical scheme：Quick voltage frequency regulating system of the present invention, including hardware and software two parts, Hardware Subdivision
Divide by AVS on PLL, PMOS switch group, piece external power managing chip PMIC, hardware performance monitoring modular, DVFS control modules, piece
Control module is constituted.Software section is made up of performance layer decision-making module and supply frequency management module.
DVFS and AVS combine regulations strategy is realized by the relatively slow AVS fine tunings two parts of DVFS Fast Coarses mediation respectively.
Associated working pattern between the two is：Property needed for specified register write-in current processor from from upper layer software (applications) to hardware circuit
Energy state, configures the parameter of DVFS control modules, and realizes the switching to multiple power supplies rail by DVFS control modules, and the process is simultaneously
The output valve of the outer source of stable pressure of piece is not changed.On piece AVS control modules by monitor the pressure of key path time sequence to piece outside
The output of source of stable pressure is adjusted, so as to change the operating voltage of current chip.
Concrete technical scheme is as follows：
System includes main circuit system platform, frequency adjuster phase-locked loop pll, out-put supply path PMOS switch group, piece
AVS on DVFS control modules, piece on hardware performance monitoring modular, piece on external power managing chip PMIC, performance decision-making module, piece
Control module；
Wherein, on piece hardware performance monitoring modular output by performance decision-making module with piece DVFS control modules it is defeated
Enter end to be connected, the output end of DVFS control modules is connected to frequency adjuster phase-locked loop pll and out-put supply path respectively on piece
The input of PMOS switch group, on the piece of main circuit system platform ring oscillator output end with piece AVS control modules it is defeated
Enter end to be connected, and the output end of AVS control modules is connected with the input of piece external power managing chip PMIC on piece；
Described upper hardware performance monitoring modular is the hardware circuit module of chip internal, on main monitoring chip bus
Data transfer and director data information, and performance decision-making module is transmitted this information to, performance decision-making module is according to current different
Application scenarios, the performance requirement of current processor is assessed, while predicting following property development demand by algorithm to control
The switching of DVFS state machine states；
The out-put supply path PMOS switch group is made up of N number of PMOS switch, and N is greater than 1 integer, its open and
Closure state is controlled according to the look-up table of DVFS systems activation design；
Described upper DVFS control module mainly includes software switch group, comparator, D/A converting circuit and controller；It is soft
The digit of part switches set matches with PMOS numbers in the out-put supply path PMOS switch group, and by inverter drive
The grid of PMOS transistor；The effect of comparator is the school that supply voltage is realized by comparison reference voltage and supply voltage
It is accurate；D/A converting circuit provides voltage-regulation stepping for power supply regulation process, while for comparator provides reference voltage, digital-to-analogue turns
The data signal input for changing circuit comes from controller；Controller is the core of power selection circuit, for controlling power supply
The sequential of switching, has different orders under different switch modes；Simultaneously the controller control power selection circuit other
The effective time of each functional module, each several part is not only set to work in order, and it is complete when whole circuit need not switch
Close, reduce the power dissipation overhead of the circuit.
The main circuit system platform is comprising a SoC chip for embedded type CPU processor.Carrying out different applications
During calculation process, because different application calculation process is different to the demand of core performance, can be by configuring different voltage/frequencies
Rate point reduces unnecessary power dissipation overhead.
The frequency adjuster phase-locked loop pll frequency different for system is provided.In modern electronic technology, in order to obtain
High-precision frequency of oscillation, generally using quartz oscillator.But the frequency of quartz oscillator does not allow malleable, and sharp
Different system clock frequencys can be easily obtained with phaselocked loop.PLL is dynamically configured by DVFS control modules in the present invention
Parameter be met the system clock frequency of different application scene.
The out-put supply path PMOS switch group realizes the switching between different electrical power voltage rails.Led to by N group power supplys
Cross PMOS switch group to realize being connected with one of which power supply, because switching is very quick, can be used to voltage and be switched fast.In chip
The power remove of portion's difference voltage domain needs power gating unit (Power-Gating Cell, also referred to as MTCMOS) to realize.Can
Power-Gating is realized to select the connection on deenergization (VDD) or ground (VSS), both Power-Gating Cell
Header-Switch and Footer-Switch is referred to as by image.Intend being used in the form of Header-Switch in the present invention
The power track cut-out that PMOS is implemented without.
Described external power managing chip PMIC is chip power supply with I2C interfaces.On the one hand, PMIC adaptations chip currently should
Appropriate voltage is dynamically configured with demand, the power dissipation overhead of chip is reduced as far as possible；On the other hand, PMIC is by directly monitoring core
The power grid magnitude of voltage of piece, adaptively intense adjustment is carried out compared with reference voltage to current voltage, to compensate fast electric
The influence of buckling.Adaptive supply voltage regulation is to monitor electric power network by direct, and using inside power management chip
Comparator compare the value of voltage and reference voltage on power grid to control the voltage output of power management chip, make PMIC
The magnitude of voltage of calibration is exported, so as to compensate quick voltage change.
The performance decision-making module mainly realized by software, and the work of current system is obtained by hardware performance monitoring module
Make loading condition, the current desired voltage/frequency value of system is obtained by existing algorithm.PMOS switch group open and shut off by
Current desired voltage is worth to, and frequency values of the parameter configuration of PLL needed for current system are determined.
Described upper hardware performance monitoring module is that (hardware circuit needs timer and counting within certain sampling period
Device) by Monitoring Data bus and instruction bus respectively, finally give CPI (Clock cycle Per Instruction, table
Show the instruction average clock periodicity for performing certain program) value judge the workload of current system.
Mainly by the workload information for monitoring, selection is adapted to the electricity of present load to described upper DVFS control module
Source path and the simultaneously different parameters of configuration PLL, so as to set the voltage/frequency point of suitable current work load.In the present invention
System performance requirements are divided into three levels, are arranged to the form of look-up table, for the selection of DVFS control modules.
The method that described upper AVS control module employs static regulation plus dynamic regulation, greatly accelerates governing speed.
At the beginning of chip starts, using ring oscillator monitoring current chip process deviation on piece, by I2C protocol integrated test system external power sources
Managing chip dynamically adjusts the operating voltage of chip, suppresses the influence of process deviation.In chip operation then using the outer PMIC of piece
Voltage change on real-time monitoring power grid, so that dynamic debugging system operating voltage is reducing the influence of voltage deviation.Directly
The comparator inside using power management chip is connect to compare the value of voltage and reference voltage on power grid to control power management
The voltage output of chip, voltage can Automatic adjusument and the sampling period it is short, further reduce the time sequence allowances that bring of PVT so that
VDD is reduced to reduce power consumption.
Brief description of the drawings
Fig. 1 is as the system architecture diagram of first embodiment of the invention；
Fig. 2 is as the system platform figure of first embodiment of the invention system architecture diagram；
Fig. 3 is as DVFS and AVS associated working ideograph of the present invention；
Fig. 4 is realized as the hardware circuit of DVFS and AVS combine regulations strategy of the present invention；
Fig. 5 is to switch simulation waveform from low to high as DVFS of the present invention control power supplys
Fig. 6 be as AVS of the present invention under conventional voltage voltage-regulation simulation waveform
Fig. 7 is as AVS voltage-regulations control signal truth table of the present invention
Specific embodiment
Technical solution of the present invention is described in detail below in conjunction with the accompanying drawings, but protection scope of the present invention is not limited to
The embodiment.
Embodiment：
Fig. 1 is the system architecture diagram of the embodiment of the present invention, realizes quick voltage regulation, significantly reduces power consumption
Expense, and can quickly compensate quick voltage change.The system includes main circuit system platform 1；Frequency adjuster phaselocked loop
PLL2；Out-put supply path PMOS switch group 3；Piece external power managing chip PMIC4；Performance layer decision-making module 5；Hardware on piece
Can monitoring modular 6；DVFS control modules 7 on piece；AVS control modules 8 on piece.
Wherein, input of the bus signals output of main circuit system platform 1 to hardware performance monitoring modular 6 on piece.Piece
External power managing chip PMIC4 is by out-put supply path PMOS switch group 3 for main circuit system platform 1 is powered.Main circuit system
The power supply of system platform 1 is the input of comparator in piece external power managing chip PMIC 4.The input of DVFS control modules 7 is on piece
The end value that the output of hardware performance monitoring modular 6 is obtained by performance decision-making module on piece.DVFS control modules 7 is defeated on piece
It is the input control signal of frequency adjuster phase-locked loop pll 2 and out-put supply path PMOS switch group 3 to go out.AVS controls mould on piece
The input signal of block 8 is the monitoring path timing information of main circuit system platform 1, output signal connection sheet external power managing chip
The input of PMIC4.
The main circuit system platform 1 is that, comprising a SoC chip for embedded type CPU processor, the chip is public using ARM
Take charge of the Advanced Microcontroller Bus Architecture (Advanced Microcontroller Bus Architecture, AMBA) of research and development
Build, comprising Cortex-M3 kernels, embedded SRAM (Embedded Static Random Access
Memory, ESRAM), Advanced Encryption Standard (Advanced Encryption Standard, AES) module, universal asynchronous receiving-transmitting
Device (Universal Asynchronous Receiver/Transmitter, UART) and Advanced High-Performance Bus
(Advanced High Performance Bus, AHB), advanced peripheral bus (Advanced Peripheral Bus,
APB).The main circuit system platform when different application calculation process are carried out, because different application calculation process is to kernel
The demand of performance is different, can reduce unnecessary power dissipation overhead by configuring different voltage/frequency points.
DVFS and AVS combine regulations strategy is realized by the relatively slow AVS fine tunings two parts of DVFS Fast Coarses mediation respectively.
Associated working pattern between the two is：Property needed for specified register write-in current processor from from upper layer software (applications) to hardware circuit
Energy state, configures the parameter of DVFS control modules, and realizes the switching to multiple power supplies rail by DVFS control modules, and the process is simultaneously
The output valve of the outer source of stable pressure of piece is not changed.AVS control modules reduce system design using adaptive supply voltage regulative mode
In the voltage margin that leaves.The module directly monitors electric power network, by monitor the pressure of key path time sequence to piece outside
The output of source of stable pressure is adjusted, so as to change the operating voltage of current chip.The structure chart of DVFS and AVS combine regulation strategies
As shown in Figure 2：
Detailed operation flow of the invention is as follows.
The first step：Before System on Chip/SoC startup, AVS control modules 8 are being tested by ring oscillator on monitoring piece on piece
When the voltage of PMIC is set into write-in look-up table, it is inclined to compensate current chip technique to set voltage according to ring oscillator result
Difference.This process is referred to as AVS static calibrations.When ring oscillator concussion number of times is relatively fewer, illustrate that now process corner is poor, should
When according to look-up table setting voltage higher；When ring oscillator concussion number of times is relatively more, illustrate that now process corner is preferably,
Relatively low voltage should be set according to look-up table.
Second step, during chip operation, hardware performance monitoring modular obtains reflection currently within certain sampling period on piece
The parameter of system workload, and DVFS control modules are output control signals to by performance decision-making module.
3rd step, a certain layer on piece in DVFS control modules selection look-up table meets the electricity of current system requirement critical value
Pressure/Frequency point, while being respectively configured opening and shutting off for PLL and PMOS switch group.
4th step, triggering internal set signal flag while system platform performance requirement changes, this signal represents performance
Demand is improved or reduced.
5th step, is further to reduce voltage margin after PLL and power switch PMOS groups are in stable state, will be adopted
Voltage is compared with the value of reference voltage on the power grid for collecting, and for controlling the voltage output of power management chip, makes
The magnitude of voltage that PMIC outputs are calibrated is to compensate quick voltage change.This process is referred to as AVS dynamic calibrations.Two of which voltage
Compare using the comparator inside PMIC power management chips to realize.
Two key modules that fast source voltage regulating system of the invention is related to are introduced separately below.
First, DVFS control modules 7 on piece
As shown in Fig. 4 dotted portions, quick DVFS handover module Main Functions are selection power supplys on piece, wherein mainly including
Software switch group, comparator, digital analog converter and controller, complete power supply selection function together with PMOS switch group.Software is opened
The digit of pass group matches with PMOS numbers in the out-put supply path PMOS switch group 3, and by inverter drive
The grid of PMOS transistor；The effect of comparator is the school that supply voltage is realized by comparison reference voltage and supply voltage
It is accurate；D/A converting circuit provides voltage-regulation stepping for power supply regulation process, while for comparator provides reference voltage, digital-to-analogue turns
The data signal input for changing circuit comes from controller；Controller is the core of power selection circuit, for controlling power supply
The sequential of switching, has different orders under different switch modes；Simultaneously the controller control power selection circuit other
The effective time of each functional module, each several part is not only set to work in order, and it is complete when whole circuit need not switch
Close, reduce the power dissipation overhead of the circuit.
When DVFS is adjusted, upper layer software (applications) system (performance decision-making module) can be according to current different application scenarios, assessment
The performance requirement of current processor, while predicting following property development demand by existing algorithm.By controlling bottom circuit
In special register group (register in Fig. 4), write-in different performance demand under corresponding state value.The register group will match somebody with somebody
The parameter of DVFS control modules is put, and then realization carries out supply frequency regulation to chip circuit.The register control DVFS of chip
State machine state switches, and when obtaining h2I signals after coding and being effective, shows now to need to be switched to low-load from high load condition
State, current adjustment state is changed into VLOW.Controller enables each funtion part of power supply selecting module, and constantly to number
Weighted-voltage D/A converter supplied with digital signal, is allowed to the analog voltage of output as the reference voltage of comparator.The other end of comparator
It is the output voltage of power selection circuit, the output control of comparator software switch group is opened and broken, while software switch group
Opening and breaking for power gating switch element is controlled again, eventually through opening and the regulation power supply selection circuit that breaks for power gating unit
Voltage output, realize voltage switching from high to low.Wherein Clk for power selection circuit working frequency, h2I be voltage from
High to Low switching useful signal, I2h is that voltage switches useful signal to height, and Vcore is the final output result of the circuit.
2nd, AVS control modules 8 on piece
Adaptive voltage scaling part is broadly divided into two stages, respectively static auto-calibration stage and dynamic duty rank
Section.Wherein initial phase is self-calibration phase after silicon, and electrifying startup is initialized every time once in chip, is closed for calibrating to replicate
Key path is allowed to approach actual critical path, so that replicated critical path can accurately simulate prolonging for actual critical path
Late.Dynamic duty stage, edge detection circuit obtains the delay information of replicated critical path in real time, at the same with threshold set in advance
Value reference point is compared, when the sequential allowance for monitoring be more than the reference point when, can by adjustment sheet outside DC/DC reduce
Supply voltage；When the sequential allowance for monitoring be less than the reference point when, by adjustment sheet outside DC/DC raise supply voltage.
It is illustrated in figure 5 DVFS control power supplys and switches simulation waveform from high to low.Wherein Vcore powers electricity for reality output
Pressure, is modulated by one group of PMOS transistor.C2s represents the closed loop useful signal of whole power selection circuit, and En_I is represented
The control signal of Tlow, h2I and I2h represent switching useful signal from high to low and from low to high respectively, and Result represents ratio
Compared with the output of device, Vref is the reference voltage of comparator, and S [14: 0] is software switch group signal, and data [5: 0] is digital-to-analogue conversion
The input of device.It can be seen that reference voltage of the output of digital analog converter as analog comparator, the comparative result for obtaining is all the time
It is 0, meets under switch mode from high to low, the result of Result is always 0, so by shift register output
PMOS grid control signals are followed successively by height, constantly close transistor, make the contribution of high level fewer and feweri, are connect until being reduced to
Low level conducting when being bordering on 0.6V or so, i.e. signal En_I in Fig. 5 is effective.Final output supply voltage is 0.6V.Fig. 5 is verified
DVFS controls the function of quick power switching.
It is illustrated in figure 6 adaptive supply voltage regulation waveform under conventional voltage.The primary condition of emulation is (SS techniques
Angle, 1.1V, 125 DEG C), voltage is reduced since 1.1V during emulation.The power supply source of chip is provided by the outer source of stable pressure of piece, in emulation
Described using the C model functional module compatible with HSIM netlists.
CLK is clock signal in Fig. 6, and vol_con_0 and vol_con_1 is voltage control signal, and out_reg is monitoring electricity
The output on road, Vout is the outer source of stable pressure virtual voltage output valve of piece.When control signal vol_con_0 is height, vol_con_1 in figure
For it is low when, AVS control reduce voltage；When the output of observation circuit reaches threshold point, (SS, 0.92V, 125 DEG C of corresponding circuits are defeated
Going out) when being 32 ' he000_0000, vol_con_0 is changed into low, and vol_con_1 is changed into high, and AVS controls rise a high voltage, in Fig. 6
Shown in red frame.Fig. 6 demonstrates AVS dynamic calibration processes.
In Fig. 7, voltage-regulation control signal truth table, as volt_con [1: 0]=2 ' b00, voltage keeps currency；
As volt_con [1: 0]=2 ' b10, illustrate that current sequential is more loose, reduction voltage that can be appropriate；As volt_con [1
: 0]=2 ' during b10, illustrate that current sequential is more nervous, it is necessary to it is correct to ensure the function of circuit to rise high voltage.Work as voltage-regulation
In when rising or reducing the stage, the stepping of regulation every time is 20mV.
Claims (3)
1. a kind of fast source voltage regulating system, it is characterised in that：The system includes that main circuit system platform (1), frequency are adjusted
Whole device phase-locked loop pll (2), out-put supply path PMOS switch group (3), piece external power managing chip PMIC (4), performance decision model
AVS control modules (8) on DVFS control modules (7), piece on hardware performance monitoring modular (6), piece on block (5), piece；
Wherein, on piece the output of hardware performance monitoring modular (6) by DVFS control modules on performance decision-making module (5) and piece
(7) input is connected, and the output end of DVFS control modules (7) is connected to frequency adjuster phase-locked loop pll (2) and defeated respectively on piece
Go out the input of power track PMOS switch group (3), on the piece of main circuit system platform (1) in ring oscillator output end and piece
The input of AVS control modules (8) is connected, and the output end of AVS control modules (8) and piece external power managing chip on piece
The input of PMIC (4) is connected；
Described upper hardware performance monitoring modular (6) is the hardware circuit module of chip internal, on main monitoring chip bus
Data transfer and director data information, and performance decision-making module (5) is transmitted this information to, performance decision-making module (5) basis is worked as
Preceding different application scenarios, assess the performance requirement of current processor, while predicting following property development demand to control
The switching of DVFS state machine states；
The out-put supply path PMOS switch group (3) is made up of N number of PMOS switch, and N is greater than 1 integer, its open and
Closure state is controlled according to the look-up table of DVFS systems activation design；
Described upper DVFS control modules (7) mainly includes software switch group, comparator, D/A converting circuit and controller；It is soft
The digit of part switches set matches with PMOS numbers in the out-put supply path PMOS switch group (3), and by phase inverter
Drive the grid of PMOS transistor；The effect of comparator is to realize supply voltage by comparison reference voltage and supply voltage
Calibration；D/A converting circuit provides voltage-regulation stepping for power supply regulation process, while for comparator provides reference voltage, digital-to-analogue
The data signal input of change-over circuit comes from controller；Controller is the core of power selection circuit, for controlling electricity
The sequential of source switching, has different orders under different switch modes；Simultaneously the controller control power selection circuit its
The effective time of his each functional module, each several part is not only set to work in order, and it is complete when whole circuit need not switch
Contract fully, reduces the power dissipation overhead of the circuit.
2. fast source voltage regulating system according to claim 1, it is characterised in that AVS control modules (8) are adopted on piece
The voltage margin left in system design is reduced with adaptive supply voltage regulative mode；The module directly monitors power net
Network, and the value of voltage and reference voltage on power grid compared using the comparator inside power management chip control power supply
The voltage output of managing chip, makes piece external power managing chip PMIC (4) export the magnitude of voltage of calibration, so as to compensate quick electricity
Buckling.
3. the method for carrying out voltage adjustment using the fast source voltage adjustment system described in claim 1 or 2, it is characterised in that
Mainly include the following steps that：
Step 1：Start initial, the vibration time that AVS control modules (8) pass through ring oscillator on monitoring piece on piece in System on Chip/SoC
Number, output voltage adjusts signal to piece external power managing chip PMIC (4), compensates current chip process deviation, carries out AVS static
Calibration；
Step 2：When chip normal work, hardware performance monitoring modular (6) is reflected within certain sampling period on piece
The parameter of current system workload, and DVFS control modules (7) on piece are output control signals to by performance decision-making module (5)；
A certain layer on piece in DVFS control modules (7) selection look-up table meets the voltage/frequency point of current system requirement critical value, together
When output signal control frequency adjuster phase-locked loop pll (2) and out-put supply path PMOS switch group (3)；
Step 3：After frequency adjuster phase-locked loop pll (2) and out-put supply path PMOS switch group are in stable state, to enter
One step reduces voltage margin, the input of magnitude of voltage output and piece external power managing chip PMIC (4) on chip power grid
It is connected, last internal comparator input makes piece external power managing chip PMIc (4) export the magnitude of voltage of calibration, compensates quickly electricity
Buckling, carries out AVS dynamic calibrations.
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