CN112286338B - Chip control method, chip control device, electronic equipment and storage medium - Google Patents
Chip control method, chip control device, electronic equipment and storage medium Download PDFInfo
- Publication number
- CN112286338B CN112286338B CN202011241975.5A CN202011241975A CN112286338B CN 112286338 B CN112286338 B CN 112286338B CN 202011241975 A CN202011241975 A CN 202011241975A CN 112286338 B CN112286338 B CN 112286338B
- Authority
- CN
- China
- Prior art keywords
- voltage
- chip
- fluctuation range
- frequency
- working frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3243—Power saving in microcontroller unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
The embodiment of the application provides a chip control method, a chip control device, electronic equipment and a storage medium, and belongs to the field of computers, wherein the method comprises the following steps: when the power input voltage is the initial voltage, acquiring a first current voltage in the chip; when the first current voltage is smaller than a first voltage threshold value, the working frequency of the chip is reduced, so that the first current voltage of the chip is increased to a second current voltage, and the first voltage threshold value is larger than the lower limit value of the initial voltage fluctuation range of the chip; when the second current voltage is larger than the first voltage threshold, the working frequency of the chip is increased, so that the voltage fluctuation range of the chip is narrowed to a target voltage fluctuation range; reducing the initial voltage according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range to obtain the target voltage; and adjusting the power supply input voltage of the chip to the target voltage. According to the scheme, the power input voltage of the chip is reduced by narrowing the voltage fluctuation range, and the power consumption of the chip is saved.
Description
Technical Field
The present invention relates to the field of computers, and in particular, to a chip control method, a chip control device, an electronic device, and a storage medium.
Background
With the development of science and technology, the performance of electronic devices such as mobile phones, tablet computers, notebook computers, etc. is also continuously improved.
However, with the improvement of the performance of electronic devices, the power consumption of the electronic devices is also continuously improved. For portable electronic devices such as mobile phones and tablet computers, the battery capacity is generally increased to increase the service life, however, the battery capacity can increase the volume and weight of the electronic device, and cannot meet the design requirement of the electronic device for lightness and thinness, so that reducing the power consumption of the electronic device is a long term for increasing the service life of the electronic device.
In the data processing process of the electronic device, the chip such as GPU, CPU and the like consumes a lot of power, so how to safely reduce the power consumption of the chip is a problem to be solved by those skilled in the art.
Disclosure of Invention
The embodiment of the application provides a chip control method, a chip control device, electronic equipment and a storage medium, which can solve the problem of larger power consumption of chips such as a GPU (graphics processing unit), a CPU (Central processing Unit) and the like in the electronic equipment in the prior art.
In order to solve the technical problems, the application is realized as follows:
in a first aspect, an embodiment of the present application provides a method for controlling a chip, where the method includes:
when the power input voltage is the initial voltage, acquiring a first current voltage in the chip;
under the condition that the first current voltage is smaller than a first voltage threshold value, reducing the first working frequency of the chip to a second working frequency so as to increase the first current voltage of the chip to a second current voltage, wherein the first voltage threshold value is larger than the lower limit value of the initial voltage fluctuation range of the chip;
under the condition that the second current voltage is larger than a first voltage threshold value, the second working frequency of the chip is increased to the first working frequency, so that the voltage fluctuation range of the chip is narrowed to a target voltage fluctuation range;
reducing the initial voltage according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range to obtain a target voltage;
and adjusting the power supply input voltage of the chip to the target voltage.
In a second aspect, an embodiment of the present application provides a control device for a chip, where the device includes:
the first acquisition module is used for acquiring a first current voltage in the chip when the power input voltage is an initial voltage;
the first control module is used for reducing the first working frequency of the chip to the second working frequency under the condition that the first current voltage is smaller than a first voltage threshold value so as to increase the first current voltage of the chip to a second current voltage, and the first voltage threshold value is larger than the lower limit value of the initial voltage fluctuation range of the chip;
the second control module is used for increasing the second working frequency of the chip to the first working frequency under the condition that the second current voltage is larger than a first voltage threshold value so as to narrow the voltage fluctuation range of the chip to a target voltage fluctuation range;
the processing module is used for reducing the initial voltage according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range to obtain the target voltage;
and the adjusting module is used for adjusting the power supply input voltage of the chip to the target voltage.
In a third aspect, an embodiment of the present application provides an electronic device, where the electronic device includes a processor, a memory, and a program or an instruction stored on the memory and executable on the processor, where the program or the instruction is executed by the processor to implement the steps of the method for controlling a chip according to the first aspect.
In a fourth aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which, when executed by a processor, implement the steps of the method for controlling a chip according to the first aspect.
In a fifth aspect, an embodiment of the present application provides a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and the processor is configured to execute a program or instructions to implement a control method of the chip according to the first aspect.
The embodiment of the application provides a control method of a chip, a control device of the chip, electronic equipment and a storage medium.
Drawings
Fig. 1 shows a step flowchart of a control method of a chip according to an embodiment of the present application;
fig. 2 shows one of effects of a control method of a chip according to an embodiment of the present application;
FIG. 3 shows a second effect of a control method of a chip according to an embodiment of the present disclosure;
FIG. 4 is a flowchart illustrating steps of another method for controlling a chip according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a comparator according to an embodiment of the present disclosure;
FIG. 6 shows a schematic circuit diagram of a comparator according to an embodiment of the present application;
fig. 7 is a schematic circuit diagram of a control method of a chip according to an embodiment of the present application;
fig. 8 shows a block diagram of a control device of a chip according to an embodiment of the present application;
fig. 9 shows a schematic structural diagram of an electronic device according to an embodiment of the present application;
fig. 10 shows a schematic hardware structure of an electronic device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type and not limited to the number of objects, e.g., the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
The following describes in detail a chip control method, a chip control device, an electronic device, and a storage medium according to embodiments of the present application with reference to the accompanying drawings.
Referring to fig. 1, an embodiment of the present application provides a method for controlling a chip, where the method includes:
It should be noted that, the chip in the embodiment of the present application refers to a data processing chip provided with a voltage margin, where the voltage margin is used to avoid that the operating voltage of the chip is not lower than the safety voltage of the chip when the chip operates normally in the case of voltage fluctuation, that is, the voltage margin is a difference between the minimum operating voltage and the safety voltage of the chip. The initial voltage refers to a rated power input voltage of the chip such that a first present voltage of the chip fluctuates within an initial voltage fluctuation range between the initial voltage and a minimum operating voltage.
In this application embodiment, under the condition that the power input voltage of the chip is initial voltage, the first current voltage of the chip can fluctuate in a larger initial voltage fluctuation range, and the fluctuation range of the chip is narrowed in the scheme of this application at the right time for the chip can fluctuate in a smaller voltage fluctuation range, thereby reducing the working voltage of the chip to reduce the power consumption of the chip.
And step 102, under the condition that the first current voltage is smaller than a first voltage threshold value, reducing the first working frequency of the chip to a second working frequency so as to increase the first current voltage of the chip to a second current voltage, wherein the first voltage threshold value is larger than the lower limit value of the initial voltage fluctuation range of the chip.
In an embodiment of the present application, the first voltage threshold may be obtained by: firstly, setting a chip to work at different working frequencies, then analyzing and counting the working voltages of the chip at the different working frequencies to obtain voltage fluctuation ranges of the chip working at the different working frequencies, and finally, taking the lower limit values of the voltage fluctuation ranges as first voltage threshold values corresponding to the different working frequencies, wherein the first voltage threshold values of the different working frequencies can be slightly larger than the lower limit values of the voltage fluctuation ranges, so that the power input voltage of the chip is ensured to be under the initial voltage, the measured first current voltage can reach the first voltage threshold value, and the voltage fluctuation ranges can be determined according to actual requirements without limitation. The first operating frequency may be a nominal operating frequency of the chip and the second operating frequency may be a partial nominal operating frequency of the chip, e.g., 50%, 75% nominal operating frequency, etc.
Since the operating frequency of the chip and the current voltage in the chip are in negative correlation, the current voltage of the chip can be quickly raised by reducing the operating frequency of the chip.
In the embodiment of the application, after the working frequency of the chip is reduced, the working current is reduced, and under the condition that the input power of the chip is unchanged, the power is equal to the product of the voltage and the current, so that the measured first current voltage can be raised, and is returned to be above the first voltage threshold value, at the moment, the limitation on the working frequency of the chip can be relieved, the working frequency of the chip is raised to the first working frequency before the reduction, and the chip is restored to normal work. This way, the initial voltage fluctuation range of the chip from the initial voltage to the minimum operation voltage is narrowed to the target voltage fluctuation range from the initial voltage to the first voltage threshold.
And 104, reducing the initial voltage according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range to obtain the target voltage.
In this embodiment of the present application, according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range, the voltage margin that the chip can be lifted under the limiting operation may be obtained, and it may be understood that, because the difference between the lower limit value of the initial voltage fluctuation range and the safety voltage is the original voltage margin of the chip, the lower limit value of the target voltage fluctuation range is near the first voltage threshold, and the first voltage threshold is greater than the lower limit value of the initial voltage fluctuation range, the voltage margin under the target voltage fluctuation range may be significantly greater than the voltage margin under the initial voltage fluctuation range. Furthermore, the liftable voltage margin can be used as a reducible value of the power input voltage, and the initial voltage is reduced according to the difference between the two voltage fluctuation ranges, so that the target voltage to which the power input voltage of the chip can be reduced under normal operation can be obtained. It should be noted that, the first voltage threshold is not necessarily the lower limit value of the target voltage fluctuation range, and because the chip is internally provided with an analog circuit, the initial voltage fluctuation range has randomness due to factors such as product quality and wear of the chip, so that the scheme of the scheme is required to accurately determine the lower limit value of the target voltage fluctuation range, that is, the actual liftable voltage margin.
Referring to fig. 2, V1 is an initial voltage of the chip, V2 is a first voltage threshold, V3 is a safe voltage of the chip, U1 is an initial voltage fluctuation range of the chip before limiting the frequency, U2 is a target voltage fluctuation range of the chip after limiting the frequency, and it can be seen that when the first current voltage is smaller than V2, the voltage fluctuation range of the chip is narrowed by limiting the frequency, i.e. the voltage fluctuation range of U1 is narrower relative to the voltage fluctuation range of U2, the difference Δv between U1 and U2 can be used as a liftable voltage margin, and the target voltage can be obtained by subtracting Δv from V1.
In the embodiment of the application, the power input voltage of the chip is reduced from the initial voltage to the target voltage through the control system of the chip, so that the average working voltage of the chip is reduced, and the power consumption of the chip is reduced.
Referring to fig. 3, V4 is a target voltage, and U3 is a voltage fluctuation range when a power supply input voltage of the chip is the target voltage, it can be seen that U3 is significantly lower than a voltage fluctuation range U1 of the chip at an initial voltage as a whole, thereby reducing power consumption of the chip.
According to the control method for the chip, the operating frequency of the chip is limited to narrow the voltage fluctuation range of the chip under the condition that the operating voltage of the chip is lower than the voltage threshold, so that the power supply input voltage of the chip is reduced according to the difference between the voltage fluctuation ranges before and after the operating frequency is limited, the operating voltage of the chip is reduced, and the power consumption of the chip is saved.
Referring to fig. 4, another method for controlling a chip is provided in an embodiment of the present application, where the method includes:
This step is described in detail with reference to step 101, and will not be described here.
Step 202, reducing the first operating frequency of the chip to a second operating frequency under the condition that the first current voltage is smaller than a first voltage threshold, so as to increase the first current voltage of the chip to a second current voltage, wherein the first voltage threshold is larger than the lower limit value of the initial voltage fluctuation range of the chip.
This step may be described in detail with reference to step 102, and will not be described here again.
Step 203, in the case that the second current voltage is greater than the first voltage threshold, raising the second operating frequency of the chip to the first operating frequency so as to narrow the voltage fluctuation range of the chip to a target voltage fluctuation range.
This step is described in detail with reference to step 103, and will not be described here.
In the embodiment of the application, since the initial voltage fluctuation range and the target voltage fluctuation range are both measured under the condition that the power input voltage is the initial voltage, the upper limit value is the initial voltage, the difference between the two voltage fluctuation ranges is mainly represented by the lower limit value, and the difference between the lower limit values of the two voltage fluctuation ranges is just the variable voltage allowance of the chip after limiting the frequency.
And step 205, reducing the initial voltage according to the variable voltage margin to obtain a target voltage.
In the embodiment of the application, the variable voltage margin of the chip can be obtained through the scheme, namely, the power supply input voltage which limits the allowable variation of the working frequency of the chip under the condition of ensuring the normal work of the chip is limited.
According to the embodiment of the application, the input power supply voltage of the chip is reduced by determining the variable voltage margin according to the difference between the lower limit values of the voltage fluctuation range before and after the working frequency limitation, and the power consumption of the chip is reduced.
This step may be described in detail with reference to step 105, and will not be described here again.
In the embodiment of the application, after the power input voltage of the chip is reduced, a droop monitoring mechanism is needed to monitor the third current voltage in the chip in real time when the power input voltage is the target voltage, so that the working voltage of the chip is ensured not to be lower than the safety voltage of the chip, and the chip can work normally.
Step 208, reducing the first operating frequency of the chip to the second operating frequency to raise the third current voltage of the chip to a fourth current voltage if the third current voltage is less than a second voltage threshold, wherein the second voltage threshold is greater than a safe voltage of the chip.
In this embodiment of the present application, the third voltage threshold is a voltage value set above a safety voltage of the chip, and needs to be smaller than the target voltage and larger than the safety voltage, which may be slightly higher than the safety voltage in practical application, and may specifically be determined according to practical requirements, which is not limited herein. Since the third current voltage of the chip is lower than the safety voltage, which can cause abnormal operation of the chip, affect the stability of the chip and even damage the chip, the second voltage threshold needs to be slightly higher than the safety voltage so as to ensure that the third current voltage is not lower than the safety voltage of the chip when fluctuating.
Under the condition that the second current voltage is smaller than the second voltage threshold, the working voltage of the chip is indicated to be close to the safe voltage, and at the moment, the working current of the chip can be increased by limiting the working frequency of the chip, namely reducing the working flatness of the chip from the first working frequency to the second working frequency, and under the condition that the input power is unchanged, the second current voltage of the chip can be pulled up to a fourth current voltage.
In this embodiment of the present application, when the fourth current voltage of the chip is pulled up to above the second voltage threshold, the limitation on the operating frequency of the chip may be removed, that is, the operating frequency of the chip is lifted up to return to the first operating frequency from the second operating frequency, so that the chip resumes normal operation. The limiting and releasing of the working frequency are performed instantaneously, so that the normal work of the chip is not influenced, the working voltage of the chip is not lower than the safety voltage of the chip, and the safety of the chip in reducing the power consumption is ensured in this way.
Optionally, the step 202 or the step 208 may include: and controlling the phase-locked loop frequency divider to output rated output frequency with preset proportion so that the working frequency of the chip is the rated working frequency with preset proportion.
In the embodiment of the present application, a PLL divider (Phase Locked Loop Devider) is a compilable circuit that controls the frequency of a high frequency device by a PLL. The working frequency of the chip can be correspondingly adjusted by controlling the output power of the phase-locked loop frequency divider connected with the chip.
In practical application, the working frequency of half of the chip can be limited, that is, 50% of the working frequency is reduced, in order to achieve this, the pll frequency divider can be controlled to output 50% of the rated output frequency, and of course, the preset ratio of the specific limiting working frequency can be determined according to the actual requirement, which is not limited herein.
The step 203 or step 209 may include: and controlling the phase-locked loop frequency divider to output rated output frequency with preset proportion so as to reduce the first working frequency of the chip to the second working frequency.
In this embodiment of the present application, if limitation of the chip operating frequency needs to be removed, the phase-locked loop frequency divider is controlled to output the rated output frequency, so that the operating frequency of the chip can be recovered to the rated operating frequency, at this time, the first operating frequency is the operating frequency of the chip when the phase-locked loop frequency divider outputs the rated output frequency, and the second operating frequency is the operating frequency of the chip when the phase-locked loop frequency divider outputs the rated output frequency of the preset proportion.
Optionally, the phase-locked loop frequency divider is connected to a comparator, and the step 202 or the step 208 may include: and controlling the comparator to output a first voltage to the phase-locked loop frequency divider so that the phase-locked loop frequency divider outputs a rated output frequency with a preset proportion.
In this embodiment, the comparator is a circuit for discriminating and comparing input signals according to the voltage comparator, referring to fig. 5, vcc (Volt Current Condenser) is a power input voltage, GND (Ground) is a wire Ground, V-is a first comparison voltage, v+ is a second comparison voltage, and Vout is an output voltage of the comparator. The comparator will output a high voltage if V-is greater than V + to perform one logic and a low voltage if V-is less than V + to perform another logic. In the scheme of the application, VCC may be an initial voltage or a target voltage, and V-may be a first voltage threshold and v+ is a first current voltage under the condition that VCC is the initial voltage, so that the first voltage is a high voltage, corresponds to logic for limiting the working frequency, and the second voltage is a low voltage, corresponds to logic for contacting the working frequency, and vice versa. The case where VCC is the target voltage may also refer to the description of the initial voltage, and will not be described here again.
Referring to fig. 6, a circuit schematic of a comparator is shown in which the bias current is the median of the two input currents to be compared, for measuring the effect of the input impedance. Because the input impedance of the actual comparator cannot be infinite, extra voltage difference is generated, and therefore the influence of the impedance is eliminated by inputting bias current, and the working requirement of the comparator is met. Q1 to Q11 are junction field effect transistors, V-and V+ to be compared amplify bias current through front amplifying circuits Q5 and Q6, and then logic operation is carried out on the rear stages Q1, Q9, Q11 and Q10, so that when the voltage of the V-and V+ changes in comparison, quick response can be realized, the output voltage of the comparator changes adaptively, and the output power of the phase-locked loop frequency divider is controlled. Of course, the above description of the comparator is merely illustrative, and more complex comparator circuits may be used to improve the accuracy of the comparator, and may be specifically determined according to practical needs, which is not limited herein.
The step 203 or step 209 may include: and controlling the comparator to output a second voltage to the phase-locked loop frequency divider so that the phase-locked loop frequency divider outputs a rated output frequency.
In this embodiment of the present application, referring to a circuit schematic diagram of a control method of a chip shown in fig. 7, a phase-locked loop frequency divider may be connected to the chip to control an operating frequency of the chip, and further a hardware detection circuit based on a comparator may be connected between the phase-locked loop frequency divider and a power supply, so as to control an output frequency of the phase-locked loop frequency divider.
In the embodiment of the application, the hardware detection circuit is arranged through the comparator to control the phase-locked loop frequency divider, so that the working frequency of the chip is adjusted, and the circuit safety of the chip when the power consumption is reduced is ensured.
According to the control method of the chip, provided by the embodiment of the application, the voltage fluctuation range of the chip is narrowed by limiting the working frequency of the chip under the condition that the working voltage of the chip is lower than the first voltage threshold, so that the power supply input voltage of the chip is reduced according to the difference between the voltage fluctuation ranges before and after limiting the working frequency, the working voltage of the chip is reduced, and the power consumption of the chip is saved. And after the power input voltage of the chip is reduced, the working voltage of the chip is monitored, and the working frequency of the chip is limited in time to pull up the working voltage when the working voltage is smaller than a second voltage threshold, so that the working voltage of the chip is not lower than a safety voltage, and the safety of reducing the power consumption of the chip in the scheme is ensured.
It should be noted that, in the control method of the chip provided in the embodiments of the present application, the execution body may be a control device of the chip, or a control module in the control device of the chip for executing the control method of the chip. In the embodiment of the present application, a method for controlling a chip provided in the embodiment of the present application is described by taking a control method for executing a control method for loading a chip by a control device of the chip as an example.
Referring to fig. 8, the embodiment of the present application further provides a block diagram of a control device 30 of a chip, where the control device of the chip includes:
a first obtaining module 301, configured to obtain a first current voltage in the chip when the power input voltage is an initial voltage;
a first control module 302, configured to reduce, in a case where the first current voltage is less than a first voltage threshold, a first operating frequency of the chip to a second operating frequency, so as to increase the first current voltage of the chip to a second current voltage, where the first voltage threshold is greater than a lower limit value of an initial voltage fluctuation range of the chip;
a second control module 303, configured to raise the second operating frequency of the chip to the first operating frequency in a case where the second current voltage is greater than a first voltage threshold, so as to narrow a voltage fluctuation range of the chip to a target voltage fluctuation range;
a processing module 304, configured to reduce the initial voltage according to a difference between the initial voltage fluctuation range and the target voltage fluctuation range, so as to obtain a target voltage;
and the adjusting module 305 is configured to adjust the power input voltage of the chip to the target voltage.
Optionally, the apparatus further includes:
the second acquisition module is used for acquiring a third current voltage of the chip;
the third control module is used for reducing the first working frequency of the chip to the second working frequency under the condition that the third current voltage is smaller than a second voltage threshold value so as to increase the third current voltage of the chip to a fourth current voltage, and the second voltage threshold value is larger than the safety voltage of the chip;
and the fourth control module is used for increasing the second working frequency of the chip to the first working frequency under the condition that the fourth current voltage is larger than a second voltage threshold value.
Optionally, the processing module 304 is further configured to:
taking the difference between the initial voltage fluctuation range and the lower limit value of the target voltage fluctuation range as a variable voltage allowance;
and reducing the initial voltage according to the variable voltage margin to obtain a target voltage.
Optionally, the first control module 302 is further configured to:
controlling the phase-locked loop frequency divider to output rated output frequency with preset proportion so as to reduce the first working frequency of the chip to the second working frequency;
the second control module 303 is further configured to:
and controlling the phase-locked loop frequency divider to output rated output frequency so as to enable the second working frequency of the chip to rise to the first working frequency.
Optionally, the first control module 302 is further configured to:
controlling the comparator to output a first voltage to the phase-locked loop frequency divider so that the phase-locked loop frequency divider outputs a rated output frequency with a preset proportion;
the second control module 303 is further configured to:
and controlling the comparator to output a second voltage to the phase-locked loop frequency divider so that the phase-locked loop frequency divider outputs a rated output frequency.
According to the control device for the chip, provided by the embodiment of the application, the voltage fluctuation range of the chip is narrowed by limiting the working frequency of the chip under the condition that the working voltage of the chip is lower than the voltage threshold, so that the power supply input voltage of the chip is reduced according to the difference between the voltage fluctuation ranges before and after the working frequency is limited, the working voltage of the chip is reduced, and the power consumption of the chip is saved.
The control device of the chip in the embodiment of the application may be a device, or may be a component, an integrated circuit, or a chip in a terminal. The device may be a mobile electronic device or a non-mobile electronic device. By way of example, the mobile electronic device may be a cell phone, tablet computer, notebook computer, palm computer, vehicle-mounted electronic device, wearable device, ultra-mobile personal computer (ultra-mobile personal computer, UMPC), netbook or personal digital assistant (personal digital assistant, PDA), etc., and the non-mobile electronic device may be a server, network attached storage (Network Attached Storage, NAS), personal computer (personal computer, PC), television (TV), teller machine or self-service machine, etc., and the embodiments of the present application are not limited in particular.
The control device of the chip in the embodiment of the application may be a device with an operating system. The operating system may be an Android operating system, an ios operating system, or other possible operating systems, which are not specifically limited in the embodiments of the present application.
The control device for a chip provided in this embodiment of the present application can implement each process implemented by the control device for a chip in the method embodiment of fig. 1 to fig. 7, and in order to avoid repetition, a detailed description is omitted here.
Optionally, as shown in fig. 9, the embodiment of the present application further provides an electronic device 400, including a processor 401, a memory 402, and a program or an instruction stored in the memory 402 and capable of running on the processor 401, where the program or the instruction implements each process of the control method embodiment of the chip when executed by the processor 401, and the process can achieve the same technical effect, and for avoiding repetition, a description is omitted herein.
The electronic device in the embodiment of the application includes the mobile electronic device and the non-mobile electronic device described above.
Fig. 10 is a schematic hardware structure of an electronic device implementing an embodiment of the present application.
The electronic device 500 includes, but is not limited to: radio frequency unit 501, network module 502, audio output unit 503, input unit 504, sensor 505, display unit 506, user input unit 507, interface unit 508, memory 509, and processor 510.
Those skilled in the art will appreciate that the electronic device 500 may further include a power source (e.g., a battery) for powering the various components, and that the power source may be logically coupled to the processor 510 via a power management system to perform functions such as managing charging, discharging, and power consumption via the power management system. The electronic device structure shown in fig. 9 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than shown, or may combine certain components, or may be arranged in different components, which are not described in detail herein.
Wherein the processor 510 is configured to:
when the power input voltage is the initial voltage, acquiring a first current voltage in the chip;
under the condition that the first current voltage is smaller than a first voltage threshold value, reducing the first working frequency of the chip to a second working frequency so as to increase the first current voltage of the chip to a second current voltage, wherein the first voltage threshold value is larger than the lower limit value of the initial voltage fluctuation range of the chip;
under the condition that the second current voltage is larger than a first voltage threshold value, the second working frequency of the chip is increased to the first working frequency, so that the voltage fluctuation range of the chip is narrowed to a target voltage fluctuation range;
reducing the initial voltage according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range to obtain a target voltage;
and adjusting the power supply input voltage of the chip to the target voltage.
According to the embodiment of the application, the operating frequency of the chip is limited to narrow the voltage fluctuation range of the chip under the condition that the operating voltage of the chip is lower than the voltage threshold, so that the power supply input voltage of the chip is reduced according to the difference between the voltage fluctuation ranges before and after the operating frequency is limited, the operating voltage of the chip is reduced, and the power consumption of the chip is saved.
Optionally, the processor 510 is further configured to:
acquiring a third current voltage of the chip;
reducing the first operating frequency of the chip to the second operating frequency under the condition that the third current voltage is smaller than a second voltage threshold, so as to increase the third current voltage of the chip to a fourth current voltage, wherein the second voltage threshold is larger than a safety voltage of the chip;
and under the condition that the fourth current voltage is larger than a second voltage threshold value, the second working frequency of the chip is increased to the first working frequency.
Optionally, the processor 510 is further configured to:
taking the difference between the initial voltage fluctuation range and the lower limit value of the target voltage fluctuation range as a variable voltage allowance;
and reducing the initial voltage according to the variable voltage margin to obtain a target voltage.
Optionally, the processor 510 is further configured to:
controlling the phase-locked loop frequency divider to output rated output frequency with preset proportion so as to reduce the first working frequency of the chip to the second working frequency;
and controlling the phase-locked loop frequency divider to output rated output frequency so as to enable the second working frequency of the chip to rise to the first working frequency.
Optionally, the processor 510 is further configured to:
controlling the comparator to output a first voltage to the phase-locked loop frequency divider so that the phase-locked loop frequency divider outputs a rated output frequency with a preset proportion;
and controlling the comparator to output a second voltage to the phase-locked loop frequency divider so that the phase-locked loop frequency divider outputs a rated output frequency.
According to the scheme, after the power input voltage of the chip is reduced, the working voltage of the chip is monitored, and the working frequency of the chip is limited in time to pull up the working voltage when the working voltage is smaller than the second voltage threshold, so that the working voltage of the chip is not lower than the safety voltage, and the safety of reducing the power consumption of the chip is ensured.
It should be appreciated that in embodiments of the present application, the input unit 504 may include a graphics processor (Graphics Processing Unit, GPU) 5041 and a microphone 5042, with the graphics processor 5041 processing image data of still pictures or video obtained by an image capturing device (e.g., a camera) in a video capturing mode or an image capturing mode. The display unit 506 may include a display panel 5061, and the display panel 5061 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 507 includes a touch panel 5071 and other input devices 5072. Touch panel 5071, also referred to as a touch screen. Touch panel 5071 may include two parts, a touch detection device and a touch controller. Other input devices 5072 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and so forth, which are not described in detail herein. The memory 509 may be used to store software programs as well as various data including, but not limited to, application programs and an operating system. Processor 510 may integrate an application processor that primarily handles operating systems, user interfaces, applications, etc., with a modem processor that primarily handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 510.
The embodiment of the present application further provides a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or the instruction is executed by a processor, the program or the instruction realizes each process of the control method embodiment of the chip, and the same technical effects can be achieved, so that repetition is avoided, and no description is repeated here.
Wherein the processor is a processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium such as a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.
The embodiment of the application further provides a chip, the chip includes a processor and a communication interface, the communication interface is coupled with the processor, the processor is used for running a program or an instruction, implementing each process of the control method embodiment of the chip, and achieving the same technical effect, so as to avoid repetition, and no redundant description is provided herein.
It should be understood that the chips referred to in the embodiments of the present application may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may also be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk), comprising several instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method described in the embodiments of the present application.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those of ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are also within the protection of the present application.
Claims (8)
1. A method for controlling a chip, the method comprising:
when the power input voltage is the initial voltage, acquiring a first current voltage in the chip;
under the condition that the first current voltage is smaller than a first voltage threshold value, reducing the first working frequency of the chip to a second working frequency so as to increase the first current voltage of the chip to a second current voltage, wherein the first voltage threshold value is larger than the lower limit value of the initial voltage fluctuation range of the chip;
under the condition that the second current voltage is larger than a first voltage threshold value, the second working frequency of the chip is increased to the first working frequency, so that the voltage fluctuation range of the chip is narrowed to a target voltage fluctuation range;
reducing the initial voltage according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range to obtain a target voltage;
adjusting the power supply input voltage of the chip to the target voltage;
after the adjusting the power input voltage of the chip to the target voltage, the method further comprises:
acquiring a third current voltage of the chip;
reducing the first operating frequency of the chip to the second operating frequency under the condition that the third current voltage is smaller than a second voltage threshold, so as to increase the third current voltage of the chip to a fourth current voltage, wherein the second voltage threshold is larger than a safety voltage of the chip;
and under the condition that the fourth current voltage is larger than a second voltage threshold value, the second working frequency of the chip is increased to the first working frequency.
2. The method of claim 1, wherein reducing the initial voltage according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range to obtain the target voltage comprises:
taking the difference between the initial voltage fluctuation range and the lower limit value of the target voltage fluctuation range as a variable voltage allowance;
and reducing the initial voltage according to the variable voltage margin to obtain a target voltage.
3. The method of claim 1, wherein the chip has a phase-locked loop divider connected thereto, the reducing the first operating frequency of the chip to the second operating frequency comprising:
controlling the phase-locked loop frequency divider to output rated output frequency with preset proportion so as to reduce the first working frequency of the chip to the second working frequency;
the step of increasing the second operating frequency of the chip to the first operating frequency includes:
and controlling the phase-locked loop frequency divider to output rated output frequency so as to enable the second working frequency of the chip to rise to the first working frequency.
4. A method according to claim 3, wherein the phase-locked loop frequency divider is connected to a comparator, and the controlling the phase-locked loop frequency divider to output a rated output frequency of a preset proportion comprises:
controlling the comparator to output a first voltage to the phase-locked loop frequency divider so that the phase-locked loop frequency divider outputs a rated output frequency with a preset proportion;
the controlling the phase-locked loop frequency divider to output the rated output frequency comprises:
and controlling the comparator to output a second voltage to the phase-locked loop frequency divider so that the phase-locked loop frequency divider outputs a rated output frequency.
5. A control device for a chip, the device comprising:
the first acquisition module is used for acquiring a first current voltage in the chip when the power input voltage is an initial voltage;
the first control module is used for reducing the first working frequency of the chip to the second working frequency under the condition that the first current voltage is smaller than a first voltage threshold value so as to increase the first current voltage of the chip to a second current voltage, and the first voltage threshold value is larger than the lower limit value of the initial voltage fluctuation range of the chip;
the second control module is used for increasing the second working frequency of the chip to the first working frequency under the condition that the second current voltage is larger than a first voltage threshold value so as to narrow the voltage fluctuation range of the chip to a target voltage fluctuation range;
the processing module is used for reducing the initial voltage according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range to obtain the target voltage;
the adjusting module is used for adjusting the power supply input voltage of the chip to the target voltage;
the device further comprises:
the second acquisition module is used for acquiring a third current voltage of the chip;
the third control module is used for reducing the first working frequency of the chip to the second working frequency under the condition that the third current voltage is smaller than a second voltage threshold value so as to increase the third current voltage of the chip to a fourth current voltage, and the second voltage threshold value is larger than the safety voltage of the chip;
and the fourth control module is used for increasing the second working frequency of the chip to the first working frequency under the condition that the fourth current voltage is larger than a second voltage threshold value.
6. The apparatus of claim 5, wherein the processing module is further configured to:
taking the difference between the initial voltage fluctuation range and the lower limit value of the target voltage fluctuation range as a variable voltage allowance;
and reducing the initial voltage according to the variable voltage margin to obtain a target voltage.
7. An electronic device comprising a processor, a memory and a program or instruction stored on the memory and executable on the processor, which when executed by the processor, implements the steps of the method of controlling a chip as claimed in any one of claims 1 to 4.
8. A readable storage medium, characterized in that the readable storage medium has stored thereon a program or instructions which, when executed by a processor, implement the steps of the control method of a chip according to any of claims 1-4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011241975.5A CN112286338B (en) | 2020-11-09 | 2020-11-09 | Chip control method, chip control device, electronic equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011241975.5A CN112286338B (en) | 2020-11-09 | 2020-11-09 | Chip control method, chip control device, electronic equipment and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112286338A CN112286338A (en) | 2021-01-29 |
| CN112286338B true CN112286338B (en) | 2023-05-05 |
Family
ID=74351764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011241975.5A Active CN112286338B (en) | 2020-11-09 | 2020-11-09 | Chip control method, chip control device, electronic equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112286338B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112947191B (en) * | 2021-02-08 | 2024-07-23 | 联想(北京)有限公司 | Information processing method, information processing device, electronic equipment and storage medium |
| CN113674791B (en) * | 2021-08-25 | 2023-07-25 | 苏州浪潮智能科技有限公司 | Power supply control method, device, equipment and medium of SSD power supply chip |
| CN114035631B (en) * | 2021-11-11 | 2022-07-08 | 郑州机械研究所有限公司 | Method, device, apparatus and medium for controlling heating voltage of wire |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102968655A (en) * | 2011-08-31 | 2013-03-13 | 北京中电华大电子设计有限责任公司 | Operating frequency adjusting method and circuit for contactless card chip |
| CN104808736A (en) * | 2015-04-24 | 2015-07-29 | 深圳市振邦智能科技有限公司 | Method for compensating PWM (Pulse-Width Modulation) control voltage |
| CN106873696A (en) * | 2017-03-20 | 2017-06-20 | 东南大学 | A kind of self adaptation fast source voltage regulating system |
| CN107256078A (en) * | 2017-05-05 | 2017-10-17 | 浙江大华技术股份有限公司 | A kind of method for regulating dynamic voltage frequency and device |
| CN107407942A (en) * | 2015-03-30 | 2017-11-28 | 苹果公司 | Under-voltage detects and property regulation |
| CN107977037A (en) * | 2017-11-17 | 2018-05-01 | 合肥鑫晟光电科技有限公司 | A kind of low-dropout regulator and its control method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110062885A1 (en) * | 2008-05-14 | 2011-03-17 | Koninklijke Philips Electronics N.V. | Method of driving an uhp gas-discharge lamp |
| JP5721915B1 (en) * | 2013-06-26 | 2015-05-20 | 三菱電機株式会社 | Voltage monitoring control system, voltage monitoring control device, measuring device, and voltage monitoring control method |
-
2020
- 2020-11-09 CN CN202011241975.5A patent/CN112286338B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102968655A (en) * | 2011-08-31 | 2013-03-13 | 北京中电华大电子设计有限责任公司 | Operating frequency adjusting method and circuit for contactless card chip |
| CN107407942A (en) * | 2015-03-30 | 2017-11-28 | 苹果公司 | Under-voltage detects and property regulation |
| CN104808736A (en) * | 2015-04-24 | 2015-07-29 | 深圳市振邦智能科技有限公司 | Method for compensating PWM (Pulse-Width Modulation) control voltage |
| CN106873696A (en) * | 2017-03-20 | 2017-06-20 | 东南大学 | A kind of self adaptation fast source voltage regulating system |
| CN107256078A (en) * | 2017-05-05 | 2017-10-17 | 浙江大华技术股份有限公司 | A kind of method for regulating dynamic voltage frequency and device |
| CN107977037A (en) * | 2017-11-17 | 2018-05-01 | 合肥鑫晟光电科技有限公司 | A kind of low-dropout regulator and its control method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112286338A (en) | 2021-01-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112286338B (en) | Chip control method, chip control device, electronic equipment and storage medium | |
| US20170344096A1 (en) | Methods and apparatuses to wake computer systems from sleep states | |
| US20120284543A1 (en) | User input triggered device power management | |
| KR20100124928A (en) | Method of power management | |
| CN109164858B (en) | Method and electronic device for controlling current | |
| CN114050798A (en) | Radio frequency control circuit, radio frequency control method, electronic device, and storage medium | |
| US20160054422A1 (en) | System and Method for Providing an Accurate and Cost-Effective Current Sensor Calibration | |
| CN114123114A (en) | Control method and device of bleeder circuit, bleeder device and electronic equipment | |
| CN112713629A (en) | Charging method and device and electronic equipment | |
| CN113031752A (en) | Chip voltage adjusting method, performance testing method and device and electronic equipment | |
| CN112787607A (en) | Power supply circuit, power supply control method, electronic device, and storage medium | |
| WO2022206646A1 (en) | Power source chip testing circuit, power source chip testing method and apparatus, and electronic device | |
| CN111697556A (en) | Operation control method of electrical equipment and terminal equipment | |
| US20180188754A1 (en) | Voltage droop mitigation circuit for power supply network | |
| CN112367099B (en) | Clock signal processing method and device and electronic equipment | |
| US10146726B2 (en) | Motherboard and electronic device using the same | |
| CN112462667B (en) | Split type high-power source control method and system | |
| CN112328070A (en) | Charging control method, charging control device and electronic equipment | |
| CN113691967B (en) | Bluetooth scanning frequency adjusting method and device | |
| US20140215203A1 (en) | Protection device, protection method and electronic system thereof | |
| CN113010004A (en) | Abnormal power consumption processing method and device and electronic equipment | |
| CN112965551A (en) | Heating control method and device for loudspeaker | |
| CN112216888A (en) | Charging method and device and electronic equipment | |
| CN113676271B (en) | Method and device for switching antennas | |
| CN113572497B (en) | Antenna structure and control method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |