CN112286338A - Chip control method, chip control device, electronic device, and storage medium - Google Patents
Chip control method, chip control device, electronic device, and storage medium Download PDFInfo
- Publication number
- CN112286338A CN112286338A CN202011241975.5A CN202011241975A CN112286338A CN 112286338 A CN112286338 A CN 112286338A CN 202011241975 A CN202011241975 A CN 202011241975A CN 112286338 A CN112286338 A CN 112286338A
- Authority
- CN
- China
- Prior art keywords
- voltage
- chip
- fluctuation range
- frequency
- working frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3243—Power saving in microcontroller unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the application provides a chip control method, a chip control device, an electronic device and a storage medium, which belong to the field of computers, and the method comprises the following steps: when the input voltage of the power supply is an initial voltage, acquiring a first current voltage in the chip; when the first current voltage is smaller than a first voltage threshold value, reducing the working frequency of the chip to increase the first current voltage of the chip to a second current voltage, wherein the first voltage threshold value is larger than the lower limit value of the initial voltage fluctuation range of the chip; when the second current voltage is larger than the first voltage threshold, the working frequency of the chip is increased, so that the voltage fluctuation range of the chip is narrowed to a target voltage fluctuation range; reducing the initial voltage according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range to obtain a target voltage; and adjusting the power supply input voltage of the chip to a target voltage. According to the scheme, the power supply input voltage of the chip is reduced by narrowing the voltage fluctuation range, and the power consumption of the chip is saved.
Description
Technical Field
The present disclosure relates to the field of computers, and in particular, to a chip control method, a chip control device, an electronic device, and a storage medium.
Background
With the development of science and technology, the performance of electronic devices such as mobile phones, tablet computers, notebook computers and the like is also continuously improved.
However, along with the improvement of the performance of electronic devices, the power consumption of electronic devices is also increasing. For portable electronic devices such as mobile phones and tablet computers, increasing battery capacity is usually adopted to increase the service life, however, the battery capacity increases the volume and weight of the electronic device and cannot meet the design requirement of the electronic device for pursuing lightness and thinness, so that it is a long time to increase the service life of the electronic device to reduce the power consumption of the electronic device.
In the data processing process of the electronic device, a large amount of power is consumed by chips such as a GPU and a CPU, so how to safely reduce the power consumption of the chips becomes a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
Embodiments of the present application provide a chip control method, a chip control device, an electronic device, and a storage medium, which can solve the problem in the prior art that power consumption of chips such as a GPU and a CPU in the electronic device is large.
In order to solve the technical problem, the present application is implemented as follows:
in a first aspect, an embodiment of the present application provides a method for controlling a chip, where the method includes:
when the input voltage of the power supply is an initial voltage, acquiring a first current voltage in the chip;
when the first current voltage is smaller than a first voltage threshold value, reducing the first working frequency of the chip to a second working frequency so as to increase the first current voltage of the chip to a second current voltage, wherein the first voltage threshold value is larger than the lower limit value of the initial voltage fluctuation range of the chip;
under the condition that the second current voltage is larger than a first voltage threshold value, the second working frequency of the chip is increased to the first working frequency, so that the voltage fluctuation range of the chip is narrowed to a target voltage fluctuation range;
reducing the initial voltage according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range to obtain a target voltage;
and adjusting the power supply input voltage of the chip to the target voltage.
In a second aspect, an embodiment of the present application provides a control apparatus for a chip, where the apparatus includes:
the first obtaining module is used for obtaining a first current voltage in the chip when the power supply input voltage is an initial voltage;
the first control module is used for reducing the first working frequency of the chip to a second working frequency under the condition that the first current voltage is smaller than a first voltage threshold value so as to increase the first current voltage of the chip to a second current voltage, and the first voltage threshold value is larger than the lower limit value of the initial voltage fluctuation range of the chip;
the second control module is used for increasing the second working frequency of the chip to the first working frequency under the condition that the second current voltage is larger than a first voltage threshold value so as to narrow the voltage fluctuation range of the chip to a target voltage fluctuation range;
the processing module is used for reducing the initial voltage according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range to obtain a target voltage;
and the adjusting module is used for adjusting the power supply input voltage of the chip to the target voltage.
In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor, a memory, and a program or an instruction stored on the memory and executable on the processor, and when the program or the instruction is executed by the processor, the method for controlling a chip according to the first aspect is implemented.
In a fourth aspect, the present application provides a readable storage medium, on which a program or instructions are stored, and when the program or instructions are executed by a processor, the program or instructions implement the steps of the control method of the chip according to the first aspect.
In a fifth aspect, an embodiment of the present application provides a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and the processor is configured to execute a program or instructions to implement the control method of the chip according to the first aspect.
The embodiment of the application provides a chip control method, a chip control device, electronic equipment and a storage medium, and the scheme narrows the voltage fluctuation range of a chip by limiting the working frequency of the chip under the condition that the working voltage of the chip is lower than a voltage threshold value, so that the power input voltage of the chip is reduced according to the difference between the voltage fluctuation ranges before and after the working frequency limitation, the working voltage of the chip is reduced, and the power consumption of the chip is saved.
Drawings
Fig. 1 is a flowchart illustrating steps of a method for controlling a chip according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram illustrating an effect of a chip control method according to an embodiment of the present disclosure;
fig. 3 is a second schematic diagram illustrating an effect of a chip control method according to an embodiment of the present application;
FIG. 4 is a flowchart illustrating steps of another chip control method according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a comparator according to an embodiment of the present application;
FIG. 6 is a schematic circuit diagram of a comparator according to an embodiment of the present application;
fig. 7 is a circuit diagram illustrating a control method of a chip according to an embodiment of the present disclosure;
fig. 8 is a block diagram illustrating a control apparatus of a chip according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
fig. 10 is a schematic diagram illustrating a hardware structure of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be practiced in sequences other than those illustrated or described herein, and that the terms "first," "second," and the like are generally used herein in a generic sense and do not limit the number of terms, e.g., the first term can be one or more than one. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.
A chip control method, a chip control device, an electronic device, and a storage medium provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Referring to fig. 1, an embodiment of the present application provides a chip control method, where the method includes:
It should be noted that the chip in the embodiment of the present application refers to a data processing chip provided with a voltage margin, where the voltage margin is used to avoid that the operating voltage of the chip is not lower than the safe voltage for normal operation of the chip when the voltage fluctuation occurs during normal operation of the chip, that is, the voltage margin is a difference between the minimum operating voltage and the safe voltage of the chip. The initial voltage refers to the rated power supply input voltage of the chip, so that the first current voltage of the chip can fluctuate within the fluctuation range of the initial voltage between the initial voltage and the minimum working voltage.
In the embodiment of the application, under the condition that the power input voltage of the chip is the initial voltage, the first current voltage of the chip fluctuates within a larger fluctuation range of the initial voltage, and the fluctuation range of the chip is narrowed in the scheme of the application, so that the chip can fluctuate within a smaller voltage fluctuation range, and the working voltage of the chip is reduced to reduce the power consumption of the chip.
And 102, reducing the first working frequency of the chip to a second working frequency under the condition that the first current voltage is smaller than a first voltage threshold value so as to increase the first current voltage of the chip to a second current voltage, wherein the first voltage threshold value is larger than the lower limit value of the initial voltage fluctuation range of the chip.
In the embodiment of the present application, the first voltage threshold may be obtained by: firstly, setting the chip to work under different working frequencies, then, analyzing and counting the working voltages of the chip under different working frequencies, thereby obtaining voltage fluctuation ranges of the chip working under different working frequencies, and finally, taking the lower limit values of the voltage fluctuation ranges as the first voltage threshold values corresponding to different working frequencies, wherein the first voltage threshold values of different working frequencies can also be slightly larger than the lower limit values of the voltage fluctuation ranges, so as to ensure that the measured first current voltage can reach the first voltage threshold value under the initial voltage of the power input voltage of the chip, and the method can be specifically determined according to actual requirements, and is not limited here. The first operating frequency may be a nominal operating frequency of the chip and the second operating frequency may be a partial nominal operating frequency of the chip, such as 50%, 75% of the nominal operating frequency, and so on.
Since the working frequency of the chip and the current voltage in the chip are in a negative correlation relationship, the current voltage of the chip can be quickly raised by reducing the working frequency of the chip.
In the embodiment of the application, after the working frequency of the chip is reduced, the working current is also reduced, and under the condition that the input power of the chip is not changed, the power is equal to the product of the voltage and the current, so that the measured first current voltage can be increased to return to be above the first voltage threshold, at this time, the limitation on the working frequency of the chip can be removed, the working frequency of the chip is increased to the first working frequency before reduction, and the chip recovers to normal work. This way, the initial voltage fluctuation range of the chip from the initial voltage to the minimum operating voltage is narrowed to the target voltage fluctuation range from the initial voltage to the first voltage threshold.
And 104, reducing the initial voltage according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range to obtain a target voltage.
In the embodiment of the present application, the voltage margin that can be increased by the chip under the limited operation can be obtained according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range, and it can be understood that, because the difference between the lower limit value of the initial voltage fluctuation range and the safe voltage is the original voltage margin of the chip, and the lower limit value of the target voltage fluctuation range is near the first voltage threshold, and the first voltage threshold is greater than the lower limit value of the initial voltage fluctuation range, the voltage margin under the target voltage fluctuation range is significantly greater than the voltage margin under the initial voltage fluctuation range. Furthermore, the liftable voltage margin can be used as a reducible value of the power input voltage, and the initial voltage is reduced according to the difference between the two voltage fluctuation ranges, so that the target voltage to which the power input voltage of the chip can be reduced under normal operation can be obtained. It should be noted that the first voltage threshold is not necessarily a lower limit of the target voltage fluctuation range, and since the chip is internally provided with an analog circuit, and the initial voltage fluctuation range has randomness due to factors such as product quality and consumption of the chip, the scheme of the present disclosure is required to accurately determine the lower limit of the target voltage fluctuation range, that is, the actual voltage margin that can be increased.
Referring to fig. 2, V1 is an initial voltage of the chip, V2 is a first voltage threshold, V3 is a safe voltage of the chip, U1 is an initial voltage fluctuation range of the chip before limiting the frequency, U2 is a target voltage fluctuation range of the chip after limiting the frequency, it can be seen that when the first current voltage is less than V2, the voltage fluctuation range of the chip is narrowed by limiting the frequency pull-up voltage, i.e. the voltage fluctuation range of U1 is narrower relative to U2, Δ V, which is a difference between U1 and U2, can be used as a liftable voltage margin, and the target voltage can be obtained by subtracting Δ V from V1.
In the embodiment of the application, the control system of the chip reduces the power supply input voltage of the chip from the initial voltage to the target voltage, so that the average working voltage of the chip is reduced, and the power consumption of the chip is reduced.
Referring to fig. 3, V4 is a target voltage, and U3 is a voltage fluctuation range when the power input voltage of the chip is the target voltage, and it can be seen that U3 is significantly lower as a whole than the voltage fluctuation range U1 of the chip at the initial voltage, thereby reducing power consumption of the chip.
According to the control method of the chip, the working frequency of the chip is limited under the condition that the working voltage of the chip is lower than the voltage threshold value to narrow the voltage fluctuation range of the chip, so that the power supply input voltage of the chip is reduced according to the difference between the voltage fluctuation ranges before and after the working frequency limitation, the working voltage of the chip is reduced, and the power consumption of the chip is saved.
Referring to fig. 4, an embodiment of the present application provides another chip control method, where the method includes:
This step can refer to the detailed description of step 101, which is not repeated herein.
Step 202, when the first current voltage is smaller than a first voltage threshold, reducing the first operating frequency of the chip to a second operating frequency to increase the first current voltage of the chip to a second current voltage, where the first voltage threshold is greater than a lower limit value of an initial voltage fluctuation range of the chip.
This step can refer to the detailed description of step 102, which is not repeated here.
Step 203, raising the second working frequency of the chip to the first working frequency when the second current voltage is greater than a first voltage threshold value, so as to narrow the voltage fluctuation range of the chip to a target voltage fluctuation range.
This step can refer to the detailed description of step 103, which is not repeated herein.
In the embodiment of the application, since the initial voltage fluctuation range and the target voltage fluctuation range are both measured under the condition that the power supply input voltage is the initial voltage, the upper limit value is the initial voltage, the difference between the two voltage fluctuation ranges is mainly reflected in the lower limit value, and the difference between the lower limit values of the two voltage fluctuation ranges is just the variable voltage margin of the chip after the frequency is limited.
And step 205, reducing the initial voltage according to the variable voltage margin to obtain a target voltage.
In the embodiment of the application, the variable voltage margin of the chip can be obtained through the scheme, namely, the power supply input voltage which allows the variation of the working frequency of the chip is limited under the condition that the normal operation of the chip is ensured.
According to the embodiment of the application, the input power supply voltage of the chip is reduced by determining the variable voltage margin according to the difference between the lower limit values of the voltage fluctuation ranges before and after the working frequency limitation, and the power consumption of the chip is reduced.
This step can refer to the detailed description of step 105, which is not repeated here.
In this embodiment of the present application, after the power input voltage of the chip is reduced, a droop monitoring mechanism needs to be adopted to monitor the third current voltage in the chip when the power input voltage is the target voltage in real time, so as to ensure that the working voltage of the chip is not lower than the safe voltage of the chip, and the chip can normally work.
And 208, reducing the first working frequency of the chip to the second working frequency to increase the third current voltage of the chip to a fourth current voltage under the condition that the third current voltage is smaller than a second voltage threshold, wherein the second voltage threshold is larger than the safe voltage of the chip.
In this embodiment of the application, the third voltage threshold is a voltage value set above the safe voltage of the chip, and needs to be smaller than the target voltage and larger than the safe voltage, and may be slightly higher than the safe voltage in practical application, and may specifically be determined according to practical requirements, which is not limited here. Because the third current voltage of the chip is lower than the safe voltage, the chip works abnormally, the stability of the chip is affected, and even the chip is damaged, the second voltage threshold needs to be slightly higher than the safe voltage, so that the third current voltage is not lower than the safe voltage of the chip when fluctuating.
Under the condition that the second current voltage is smaller than the second voltage threshold, the working voltage of the chip is about to approach the safe voltage, at the moment, the working current of the chip can be increased by limiting the working frequency of the chip, namely reducing the working flatness of the chip from the first working frequency to the second working frequency, and under the condition that the input power is unchanged, the second current voltage of the chip can be increased to the fourth current voltage.
In this embodiment of the present application, when the fourth current voltage of the chip is pulled up to be higher than the second voltage threshold, the limitation on the operating frequency of the chip may be removed, that is, the operating frequency of the chip is raised back to the first operating frequency from the second operating frequency, so that the chip recovers to normal operation. Because the limitation and the removal of the working frequency are carried out instantly, the normal work of the chip can not be influenced, the working voltage of the chip can be ensured not to be lower than the safe voltage of the chip, and the safety of the chip in the process of reducing power consumption is ensured by the mode.
Optionally, step 202 or step 208 may include: and controlling the phase-locked loop frequency divider to output a rated output frequency of a preset proportion, so that the working frequency of the chip is the rated working frequency of the preset proportion.
In the embodiment of the present application, a Phase Locked Loop divider (PLL divider) is a interpretable circuit for controlling the frequency of a high frequency device. The working frequency of the chip can be correspondingly adjusted by controlling the output power of the phase-locked loop frequency divider connected with the chip.
In practical application, half of the operating frequency of the chip may be limited, that is, the operating frequency is reduced by 50%, in order to achieve this, the pll frequency divider may be controlled to output a rated output frequency of 50%, and of course, the specific preset ratio for limiting the operating frequency may be determined according to actual requirements, which is not limited here.
The step 203 or the step 209 may include: and controlling the phase-locked loop frequency divider to output a rated output frequency with a preset proportion so as to reduce the first working frequency of the chip to a second working frequency.
In the embodiment of the present application, if the limitation on the operating frequency of the chip needs to be removed, the operating frequency of the chip can be recovered to the rated operating frequency by controlling the pll divider to output the rated output frequency, where the first operating frequency is the operating frequency of the chip when the pll divider outputs the rated output frequency, and the second operating frequency is the operating frequency of the chip when the pll divider outputs the rated output frequency in the preset proportion.
Optionally, the phase-locked loop divider is connected to a comparator, and step 202 or step 208 may include: and controlling the comparator to output a first voltage to the phase-locked loop frequency divider so that the phase-locked loop frequency divider outputs a rated output frequency with a preset proportion.
In the embodiment of the present application, the comparator is a circuit for discriminating and comparing the input signal according to the voltage comparator, referring to fig. 5, vcc (voltage) is a power input voltage, gnd (ground) is a ground of an electric wire, V-is a first comparison voltage, V + is a second comparison voltage, and Vout is an output voltage of the comparator. The comparator outputs a high voltage to perform one logic if V-is greater than V + and outputs a low voltage to perform another logic if V-is less than V +. In the scheme of the application, VCC may be an initial voltage or a target voltage, where V-may be a first voltage threshold and V + is a first current voltage under the condition that VCC is the initial voltage, so that the first voltage is a high voltage and corresponds to logic that limits operating frequency, the second voltage is a low voltage and corresponds to logic that contacts operating frequency, and otherwise, the replacement may be performed. The description of VCC as the initial voltage may also be referred to in the case of VCC as the target voltage, and is not repeated here.
Referring to fig. 6, a circuit schematic of a comparator is shown, wherein the bias current is the median of the two input currents to be compared, and is used to measure the effect of the input impedance. Because the input impedance of an actual comparator cannot be infinite, an additional voltage difference is generated, and therefore, the influence of the impedance needs to be eliminated by inputting a bias current, and the working requirement of the comparator is met. Q1 to Q11 are junction field effect transistors, and V-and V + which need to be compared are amplified by the front-electrode amplifying circuits Q5 and Q6 and then are subjected to logic operation at the rear stages Q1, Q9, Q11 and Q10, so that the voltage comparison of the V-and V + can be quickly responded when the voltage comparison is changed, the output voltage of the comparator is adaptively changed, and the output power of the phase-locked loop frequency divider is controlled. Of course, the above description of the comparator is only an exemplary illustration, and a more complex comparator circuit may be adopted to improve the precision of the comparator, which may be determined according to actual requirements, and is not limited herein.
The step 203 or the step 209 may include: and controlling the comparator to output a second voltage to the phase-locked loop frequency divider so that the phase-locked loop frequency divider outputs a rated output frequency.
In the embodiment of the present application, referring to fig. 7, a circuit diagram of a chip control method is shown, where a phase-locked loop frequency divider may be connected to the chip to control an operating frequency of the chip, and a hardware detection circuit based on a comparator may be further connected between the phase-locked loop frequency divider and a power supply to control an output frequency of the phase-locked loop frequency divider.
According to the embodiment of the application, the hardware detection circuit is arranged through the comparator to control the phase-locked loop frequency divider, so that the working frequency of the chip is adjusted, and the circuit safety of the chip in reducing power consumption is guaranteed.
According to the control method of the chip provided by the embodiment of the application, the voltage fluctuation range of the chip is narrowed by limiting the working frequency of the chip under the condition that the working voltage of the chip is lower than the first voltage threshold, so that the power supply input voltage of the chip is reduced according to the difference between the voltage fluctuation ranges before and after the working frequency limitation, the working voltage of the chip is reduced, and the power consumption of the chip is saved. And after the power input voltage of the chip is reduced, the working voltage of the chip is monitored, and the working frequency of the chip is limited in time to pull up the working voltage when the working voltage is smaller than the second voltage threshold value, so that the working voltage of the chip is not lower than the safe voltage, and the safety of reducing the power consumption of the chip is ensured.
In the chip control method provided in the embodiment of the present application, the execution main body may be a control device of the chip, or a control module for executing the chip control method in the control device of the chip. In the embodiment of the present application, a method for controlling a chip provided in the embodiment of the present application is described by taking as an example a method for a control device of the chip to execute a control of loading the chip.
Referring to fig. 8, an embodiment of the present application further provides a block diagram of a control device 30 of a chip, where the control device of the chip includes:
a first obtaining module 301, configured to obtain a first current voltage in a chip when a power input voltage is an initial voltage;
a first control module 302, configured to reduce the first operating frequency of the chip to a second operating frequency to increase the first current voltage of the chip to a second current voltage when the first current voltage is smaller than a first voltage threshold, where the first voltage threshold is greater than a lower limit value of an initial voltage fluctuation range of the chip;
the second control module 303 is configured to increase the second operating frequency of the chip to the first operating frequency when the second current voltage is greater than a first voltage threshold, so as to narrow a voltage fluctuation range of the chip to a target voltage fluctuation range;
a processing module 304, configured to reduce the initial voltage according to a difference between the initial voltage fluctuation range and a target voltage fluctuation range to obtain a target voltage;
an adjusting module 305, configured to adjust the power input voltage of the chip to the target voltage.
Optionally, the apparatus further includes:
the second obtaining module is used for obtaining a third current voltage of the chip;
a third control module, configured to reduce the first operating frequency of the chip to a second operating frequency to increase a third current voltage of the chip to a fourth current voltage when the third current voltage is less than a second voltage threshold, where the second voltage threshold is greater than a safe voltage of the chip;
and the fourth control module is used for increasing the second working frequency of the chip to the first working frequency under the condition that the fourth current voltage is greater than a second voltage threshold value.
Optionally, the processing module 304 is further configured to:
taking the difference between the initial voltage fluctuation range and the lower limit value of the target voltage fluctuation range as a variable voltage margin;
and reducing the initial voltage according to the variable voltage margin to obtain a target voltage.
Optionally, the first control module 302 is further configured to:
controlling the phase-locked loop frequency divider to output a rated output frequency with a preset proportion so as to reduce the first working frequency of the chip to a second working frequency;
the second control module 303 is further configured to:
and controlling the phase-locked loop frequency divider to output a rated output frequency so as to enable the second working frequency of the chip to be increased to the first working frequency.
Optionally, the first control module 302 is further configured to:
controlling the comparator to output a first voltage to the phase-locked loop frequency divider so that the phase-locked loop frequency divider outputs a rated output frequency with a preset proportion;
the second control module 303 is further configured to:
and controlling the comparator to output a second voltage to the phase-locked loop frequency divider so that the phase-locked loop frequency divider outputs a rated output frequency.
According to the control device of the chip, the voltage fluctuation range of the chip is narrowed by limiting the working frequency of the chip under the condition that the working voltage of the chip is lower than the voltage threshold, so that the power supply input voltage of the chip is reduced according to the difference between the voltage fluctuation ranges before and after the working frequency limitation, the working voltage of the chip is reduced, and the power consumption of the chip is saved.
The control device of the chip in the embodiment of the present application may be a device, or may be a component in a terminal, an integrated circuit, or a chip. The device can be mobile electronic equipment or non-mobile electronic equipment. By way of example, the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palm top computer, a vehicle-mounted electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a Personal Digital Assistant (PDA), and the like, and the non-mobile electronic device may be a server, a Network Attached Storage (NAS), a Personal Computer (PC), a Television (TV), a teller machine or a self-service machine, and the like, and the embodiments of the present application are not particularly limited.
The control device of the chip in the embodiment of the present application may be a device having an operating system. The operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, and embodiments of the present application are not limited specifically.
The control device of the chip provided in the embodiment of the present application can implement each process implemented by the control device of the chip in the method embodiments of fig. 1 to fig. 7, and is not described here again to avoid repetition.
Optionally, as shown in fig. 9, an electronic device 400 is further provided in this embodiment of the present application, and includes a processor 401, a memory 402, and a program or an instruction stored in the memory 402 and executable on the processor 401, where the program or the instruction is executed by the processor 401 to implement each process of the chip control method embodiment, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here.
It should be noted that the electronic device in the embodiment of the present application includes the mobile electronic device and the non-mobile electronic device described above.
Fig. 10 is a schematic diagram of a hardware structure of an electronic device implementing an embodiment of the present application.
The electronic device 500 includes, but is not limited to: a radio frequency unit 501, a network module 502, an audio output unit 503, an input unit 504, a sensor 505, a display unit 506, a user input unit 507, an interface unit 508, a memory 509, a processor 510, and the like.
Those skilled in the art will appreciate that the electronic device 500 may further include a power supply (e.g., a battery) for supplying power to various components, and the power supply may be logically connected to the processor 510 via a power management system, so as to implement functions of managing charging, discharging, and power consumption via the power management system. The electronic device structure shown in fig. 9 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than those shown, or combine some components, or arrange different components, and thus, the description is not repeated here.
Wherein, the processor 510 is configured to:
when the input voltage of the power supply is an initial voltage, acquiring a first current voltage in the chip;
when the first current voltage is smaller than a first voltage threshold value, reducing the first working frequency of the chip to a second working frequency so as to increase the first current voltage of the chip to a second current voltage, wherein the first voltage threshold value is larger than the lower limit value of the initial voltage fluctuation range of the chip;
under the condition that the second current voltage is larger than a first voltage threshold value, the second working frequency of the chip is increased to the first working frequency, so that the voltage fluctuation range of the chip is narrowed to a target voltage fluctuation range;
reducing the initial voltage according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range to obtain a target voltage;
and adjusting the power supply input voltage of the chip to the target voltage.
According to the embodiment of the application, the voltage fluctuation range of the chip is narrowed by limiting the working frequency of the chip under the condition that the working voltage of the chip is lower than the voltage threshold, so that the power supply input voltage of the chip is reduced according to the difference between the voltage fluctuation ranges before and after the working frequency is limited, the working voltage of the chip is reduced, and the power consumption of the chip is saved.
Optionally, the processor 510 is further configured to:
acquiring a third current voltage of the chip;
when the third current voltage is smaller than a second voltage threshold, reducing the first working frequency of the chip to the second working frequency so as to increase the third current voltage of the chip to a fourth current voltage, wherein the second voltage threshold is larger than the safe voltage of the chip;
and under the condition that the fourth current voltage is greater than a second voltage threshold value, increasing the second working frequency of the chip to the first working frequency.
Optionally, the processor 510 is further configured to:
taking the difference between the initial voltage fluctuation range and the lower limit value of the target voltage fluctuation range as a variable voltage margin;
and reducing the initial voltage according to the variable voltage margin to obtain a target voltage.
Optionally, the processor 510 is further configured to:
controlling the phase-locked loop frequency divider to output a rated output frequency with a preset proportion so as to reduce the first working frequency of the chip to a second working frequency;
and controlling the phase-locked loop frequency divider to output a rated output frequency so as to enable the second working frequency of the chip to be increased to the first working frequency.
Optionally, the processor 510 is further configured to:
controlling the comparator to output a first voltage to the phase-locked loop frequency divider so that the phase-locked loop frequency divider outputs a rated output frequency with a preset proportion;
and controlling the comparator to output a second voltage to the phase-locked loop frequency divider so that the phase-locked loop frequency divider outputs a rated output frequency.
This scheme is still through after the power input voltage who reduces the chip, through implementing the monitoring to the operating voltage of chip, in time limits the operating frequency of chip and pulls up operating voltage when operating voltage is less than the second voltage threshold value to the operating voltage who has guaranteed the chip can not be less than safe voltage, has guaranteed the security that this scheme reduces the chip consumption.
It should be understood that in the embodiment of the present application, the input Unit 504 may include a Graphics Processing Unit (GPU) 5041 and a microphone 5042, and the Graphics processor 5041 processes image data of still pictures or videos obtained by an image capturing device (such as a camera) in a video capturing mode or an image capturing mode. The display unit 506 may include a display panel 5061, and the display panel 5061 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 507 includes a touch panel 5071 and other input devices 5072. A touch panel 5071, also referred to as a touch screen. The touch panel 5071 may include two parts of a touch detection device and a touch controller. Other input devices 5072 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which are not described in further detail herein. The memory 509 may be used to store software programs as well as various data including, but not limited to, application programs and operating systems. Processor 510 may integrate an application processor, which primarily handles operating systems, user interfaces, applications, etc., and a modem processor, which primarily handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into processor 510.
The embodiment of the present application further provides a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or the instruction is executed by a processor, the program or the instruction implements each process of the above chip control method embodiment, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here.
The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and so on.
The embodiment of the present application further provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to execute a program or an instruction to implement each process of the control method embodiment of the chip, and can achieve the same technical effect, and is not described herein again to avoid repetition.
It should be understood that the chips mentioned in the embodiments of the present application may also be referred to as system-on-chip, system-on-chip or system-on-chip, etc.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Further, it should be noted that the scope of the methods and apparatus of the embodiments of the present application is not limited to performing the functions in the order illustrated or discussed, but may include performing the functions in a substantially simultaneous manner or in a reverse order based on the functions involved, e.g., the methods described may be performed in an order different than that described, and various steps may be added, omitted, or combined. In addition, features described with reference to certain examples may be combined in other examples.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present application.
While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for controlling a chip, the method comprising:
when the input voltage of the power supply is an initial voltage, acquiring a first current voltage in the chip;
when the first current voltage is smaller than a first voltage threshold value, reducing the first working frequency of the chip to a second working frequency so as to increase the first current voltage of the chip to a second current voltage, wherein the first voltage threshold value is larger than the lower limit value of the initial voltage fluctuation range of the chip;
under the condition that the second current voltage is larger than a first voltage threshold value, the second working frequency of the chip is increased to the first working frequency, so that the voltage fluctuation range of the chip is narrowed to a target voltage fluctuation range;
reducing the initial voltage according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range to obtain a target voltage;
and adjusting the power supply input voltage of the chip to the target voltage.
2. The method of claim 1, further comprising, after the adjusting the power supply input voltage of the chip to the target voltage:
acquiring a third current voltage of the chip;
when the third current voltage is smaller than a second voltage threshold, reducing the first working frequency of the chip to the second working frequency so as to increase the third current voltage of the chip to a fourth current voltage, wherein the second voltage threshold is larger than the safe voltage of the chip;
and under the condition that the fourth current voltage is greater than a second voltage threshold value, increasing the second working frequency of the chip to the first working frequency.
3. The method of claim 1, wherein reducing the initial voltage according to a difference between the initial voltage fluctuation range and a target voltage fluctuation range to obtain a target voltage comprises:
taking the difference between the initial voltage fluctuation range and the lower limit value of the target voltage fluctuation range as a variable voltage margin;
and reducing the initial voltage according to the variable voltage margin to obtain a target voltage.
4. The method of claim 1, wherein the chip is coupled to a phase-locked loop divider, and wherein reducing the first operating frequency of the chip to the second operating frequency comprises:
controlling the phase-locked loop frequency divider to output a rated output frequency with a preset proportion so as to reduce the first working frequency of the chip to a second working frequency;
the raising the second operating frequency of the chip to the first operating frequency includes:
and controlling the phase-locked loop frequency divider to output a rated output frequency so as to enable the second working frequency of the chip to be increased to the first working frequency.
5. The method of claim 4, wherein the phase-locked loop divider is connected to a comparator, and wherein controlling the phase-locked loop divider to output a predetermined percentage of the nominal output frequency comprises:
controlling the comparator to output a first voltage to the phase-locked loop frequency divider so that the phase-locked loop frequency divider outputs a rated output frequency with a preset proportion;
the controlling the phase-locked loop frequency divider to output the rated output frequency comprises the following steps:
and controlling the comparator to output a second voltage to the phase-locked loop frequency divider so that the phase-locked loop frequency divider outputs a rated output frequency.
6. A control device for a chip, the device comprising:
the first obtaining module is used for obtaining a first current voltage in the chip when the power supply input voltage is an initial voltage;
the first control module is used for reducing the first working frequency of the chip to a second working frequency under the condition that the first current voltage is smaller than a first voltage threshold value so as to increase the first current voltage of the chip to a second current voltage, and the first voltage threshold value is larger than the lower limit value of the initial voltage fluctuation range of the chip;
the second control module is used for increasing the second working frequency of the chip to the first working frequency under the condition that the second current voltage is larger than a first voltage threshold value so as to narrow the voltage fluctuation range of the chip to a target voltage fluctuation range;
the processing module is used for reducing the initial voltage according to the difference between the initial voltage fluctuation range and the target voltage fluctuation range to obtain a target voltage;
and the adjusting module is used for adjusting the power supply input voltage of the chip to the target voltage.
7. The apparatus of claim 6, further comprising:
the second obtaining module is used for obtaining a third current voltage of the chip;
a third control module, configured to reduce the first operating frequency of the chip to a second operating frequency to increase a third current voltage of the chip to a fourth current voltage when the third current voltage is less than a second voltage threshold, where the second voltage threshold is greater than a safe voltage of the chip;
and the fourth control module is used for increasing the second working frequency of the chip to the first working frequency under the condition that the fourth current voltage is greater than a second voltage threshold value.
8. The apparatus of claim 6, wherein the processing module is further configured to:
taking the difference between the initial voltage fluctuation range and the lower limit value of the target voltage fluctuation range as a variable voltage margin;
and reducing the initial voltage according to the variable voltage margin to obtain a target voltage.
9. An electronic device, comprising a processor, a memory and a program or instructions stored on the memory and executable on the processor, which when executed by the processor implement the steps of the control method of the chip according to any one of claims 1 to 5.
10. A readable storage medium, characterized in that it stores thereon a program or instructions which, when executed by a processor, implement the steps of the control method of a chip according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011241975.5A CN112286338B (en) | 2020-11-09 | 2020-11-09 | Chip control method, chip control device, electronic equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011241975.5A CN112286338B (en) | 2020-11-09 | 2020-11-09 | Chip control method, chip control device, electronic equipment and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112286338A true CN112286338A (en) | 2021-01-29 |
| CN112286338B CN112286338B (en) | 2023-05-05 |
Family
ID=74351764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011241975.5A Active CN112286338B (en) | 2020-11-09 | 2020-11-09 | Chip control method, chip control device, electronic equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112286338B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112947191A (en) * | 2021-02-08 | 2021-06-11 | 联想(北京)有限公司 | Information processing method, information processing device, electronic equipment and storage medium |
| CN113674791A (en) * | 2021-08-25 | 2021-11-19 | 苏州浪潮智能科技有限公司 | Power supply control method, device, equipment and medium for SSD power supply chip |
| CN114035631A (en) * | 2021-11-11 | 2022-02-11 | 郑州机械研究所有限公司 | Method, device, apparatus and medium for controlling heating voltage of wire |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110062885A1 (en) * | 2008-05-14 | 2011-03-17 | Koninklijke Philips Electronics N.V. | Method of driving an uhp gas-discharge lamp |
| CN102968655A (en) * | 2011-08-31 | 2013-03-13 | 北京中电华大电子设计有限责任公司 | Operating frequency adjusting method and circuit for contactless card chip |
| CN104808736A (en) * | 2015-04-24 | 2015-07-29 | 深圳市振邦智能科技有限公司 | Method for compensating PWM (Pulse-Width Modulation) control voltage |
| US20160204614A1 (en) * | 2013-06-26 | 2016-07-14 | Mitsubishi Electric Corporation | Voltage monitoring control system, voltage monitoring control device, measurement device, and voltage monitoring control method |
| CN106873696A (en) * | 2017-03-20 | 2017-06-20 | 东南大学 | A kind of self adaptation fast source voltage regulating system |
| CN107256078A (en) * | 2017-05-05 | 2017-10-17 | 浙江大华技术股份有限公司 | A kind of method for regulating dynamic voltage frequency and device |
| CN107407942A (en) * | 2015-03-30 | 2017-11-28 | 苹果公司 | Under-voltage detects and property regulation |
| CN107977037A (en) * | 2017-11-17 | 2018-05-01 | 合肥鑫晟光电科技有限公司 | A kind of low-dropout regulator and its control method |
-
2020
- 2020-11-09 CN CN202011241975.5A patent/CN112286338B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110062885A1 (en) * | 2008-05-14 | 2011-03-17 | Koninklijke Philips Electronics N.V. | Method of driving an uhp gas-discharge lamp |
| CN102968655A (en) * | 2011-08-31 | 2013-03-13 | 北京中电华大电子设计有限责任公司 | Operating frequency adjusting method and circuit for contactless card chip |
| US20160204614A1 (en) * | 2013-06-26 | 2016-07-14 | Mitsubishi Electric Corporation | Voltage monitoring control system, voltage monitoring control device, measurement device, and voltage monitoring control method |
| CN107407942A (en) * | 2015-03-30 | 2017-11-28 | 苹果公司 | Under-voltage detects and property regulation |
| CN104808736A (en) * | 2015-04-24 | 2015-07-29 | 深圳市振邦智能科技有限公司 | Method for compensating PWM (Pulse-Width Modulation) control voltage |
| CN106873696A (en) * | 2017-03-20 | 2017-06-20 | 东南大学 | A kind of self adaptation fast source voltage regulating system |
| CN107256078A (en) * | 2017-05-05 | 2017-10-17 | 浙江大华技术股份有限公司 | A kind of method for regulating dynamic voltage frequency and device |
| CN107977037A (en) * | 2017-11-17 | 2018-05-01 | 合肥鑫晟光电科技有限公司 | A kind of low-dropout regulator and its control method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112947191A (en) * | 2021-02-08 | 2021-06-11 | 联想(北京)有限公司 | Information processing method, information processing device, electronic equipment and storage medium |
| CN113674791A (en) * | 2021-08-25 | 2021-11-19 | 苏州浪潮智能科技有限公司 | Power supply control method, device, equipment and medium for SSD power supply chip |
| CN113674791B (en) * | 2021-08-25 | 2023-07-25 | 苏州浪潮智能科技有限公司 | Power supply control method, device, equipment and medium of SSD power supply chip |
| CN114035631A (en) * | 2021-11-11 | 2022-02-11 | 郑州机械研究所有限公司 | Method, device, apparatus and medium for controlling heating voltage of wire |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112286338B (en) | 2023-05-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112286338B (en) | Chip control method, chip control device, electronic equipment and storage medium | |
| US9230507B2 (en) | System and method for transitioning an electronic device from a first power mode to a second power mode | |
| EP3349325B1 (en) | Charging method, charging device and terminal | |
| CN109164858B (en) | Method and electronic device for controlling current | |
| KR20100124928A (en) | Method of power management | |
| US20130179965A1 (en) | Information Processing Device and Method for Switching Password Input Mode | |
| US20140115514A1 (en) | User-specific mobile computing device resource management | |
| WO2023061333A1 (en) | Bleeder circuit control method and apparatus, bleeder device, and electronic device | |
| CN114050798A (en) | Radio frequency control circuit, radio frequency control method, electronic device, and storage medium | |
| CN112367099B (en) | Clock signal processing method and device and electronic equipment | |
| CN112713629A (en) | Charging method and device and electronic equipment | |
| CN112422735B (en) | Information prompting method and device | |
| CN112462667B (en) | Split type high-power source control method and system | |
| US20140089696A1 (en) | Method for controlling power mode switching | |
| CN113031752A (en) | Chip voltage adjusting method, performance testing method and device and electronic equipment | |
| CN111404242A (en) | Charging method, charging device, storage medium and mobile terminal | |
| CN110767946B (en) | Method and device for controlling discharging of mobile terminal and mobile terminal | |
| WO2022253178A1 (en) | Method and apparatus for prompting level of charge | |
| CN113691967A (en) | Bluetooth scanning frequency adjusting method and device | |
| CN114222355A (en) | Terminal power saving display method and device and electronic equipment | |
| CN112965551A (en) | Heating control method and device for loudspeaker | |
| CN112216888A (en) | Charging method and device and electronic equipment | |
| CN111309224A (en) | Sound effect adjusting method and device, storage medium and mobile terminal | |
| CN111224380A (en) | Power supply protection circuit, device and equipment | |
| CN114025419B (en) | Method and device for adjusting radio frequency power, electronic equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |