CN106873696B - A kind of adaptive fast source voltage regulating system - Google Patents
A kind of adaptive fast source voltage regulating system Download PDFInfo
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- CN106873696B CN106873696B CN201710167757.3A CN201710167757A CN106873696B CN 106873696 B CN106873696 B CN 106873696B CN 201710167757 A CN201710167757 A CN 201710167757A CN 106873696 B CN106873696 B CN 106873696B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The invention discloses a kind of adaptive fast source voltage regulating system, joint dynamic voltage frequency adjusts (DVFS) and two kinds of regulation strategies of adaptive voltage scaling (AVS), is realized respectively by the relatively slow AVS fine tunings two parts of DVFS Fast Coarses mediation.It is characterized in that：The system includes main circuit system platform, frequency adjuster phase-locked loop pll, out-put supply path PMOS switch group, piece external power managing chip PMIC, performance decision-making module, hardware performance monitoring modular on piece, DVFS control modules on piece, AVS control modules on piece.This method and system reduce the operating voltage and frequency of chip simultaneously, reduce the nargin of chip voltage, compensate for the influence of quick voltage change, reduce the power dissipation overhead of chip.
Description
Technical field
The present invention relates to a kind of voltage-regulation mode, is related to digital integrated electronic circuit, more particularly to a kind of low power dissipation design skill
Art.
Background technology
Low-power Technology (Low power technology) is used for solving power consumption problem, and power problemses are to determine to rub
Can you continue applicable single factor by law.Low-power Technology can be divided into system-level, logic level from different levels, circuit-level,
Domain level, process level.Present invention design belongs to System-Level Low Power Consumption Design technology.In recent years, as integrated circuit (IC) works
Frequency, integrated level, the continuous improvement of complexity, IC power consumption quickly increases, and the raising of power consumption brings a series of reality
Problem：Causing IC running temperatures to rise can cause the operational factor of semiconductor circuit to be drifted about, and influence IC normal works；Power consumption increase
The chip life-span can be shortened by causing IC running temperatures to rise；Requirement to system cooling, not only increases system cost, and limit
The further raising of systematic function.
In recent years, both at home and abroad to dynamic voltage frequency adjust (DVFS) technology research application it is quite varied and into
Ripe, traditional DVFS modes are realized using opened loop control, after the completion of chip design, set voltage and frequency in the form of a lookup table
The corresponding relation of rate, corresponding working frequency and voltage are then chosen to search according to the actual working state of chip.
The research for adaptive voltage scaling (AVS) technology and application are also very active in the world.Based on on-line monitoring
AVS technologies influence of the PVT factors to circuit is all attributed to the change of path delay, it is single then to design sequential monitoring in slice
Member monitoring key path time sequence, according to the key path time sequence monitored, whether anxiety carries out voltage-regulation.Therefore monitor single
Can member really reflect that the delay of true critical path is directly connected to the accuracy of voltage-regulation.
With being continuously increased for integrated level, the fluctuation of supply voltage is increasing, and the fluctuation of supply voltage is mainly pressed by IR
Drop (IR drop) and induced noise di/dt (IR droop) cause.IR pressure drops are that the dead resistance of electric power network is flowed through by electric current
It is caused, and di/dt noises be due to then parasitic capacitance, resistance combine stray inductance cause.The time of these power supply noises
Constant is generally between nanosecond and microsecond.This requires monitoring unit to have high sample rate, and requires high voltage
Adjust feedback speed.Based on monitoring key path time sequence AVS methods voltage-regulation feedback network generally by I2C interface with
Outside power management chip connection, its voltage-regulation speed is by I2C transmission speeds and the electricity of external power source managing chip
The limitation of pressure regulation stabilized speed, it usually needs the time of some microseconds.
Based on subject matter recited above, the invention provides on a kind of joint DVFS and piece AVS it is quick self-adapted
Supply voltage regulating system, quick voltage fluctuation can be successfully managed.
The content of the invention
Goal of the invention：It is an object of the present invention to provide a kind of quick voltage regulating system, carrys out quick compensation chips in work
The influence of PVT (Process, Voltage, the Temperature) deviation being subject in work, it can mainly compensate the ripple of supply voltage
It is dynamic.This method overcomes the governing speed problem of AVS regulations, can be widely applied to dedicated IC chip and processing
Device chip.
Technical scheme：Quick voltage frequency regulating system of the present invention, including hardware and software two parts, Hardware Subdivision
Divide by AVS on PLL, PMOS switch group, piece external power managing chip PMIC, hardware performance monitoring modular, DVFS control modules, piece
Control module forms.Software section is made up of performance layer decision-making module and supply frequency management module.
DVFS and AVS joint regulations strategy is realized by the relatively slow AVS fine tunings two parts of DVFS Fast Coarses mediation respectively.
Associated working pattern between the two is：From upper layer software (applications) to property needed for the specified register of hardware circuit write-in current processor
Energy state, the parameter of DVFS control modules is configured, and the switching to multiple power supplies rail is realized by DVFS control modules, the process is simultaneously
The output valve of the outer source of stable pressure of piece is not changed.On piece AVS control modules by monitor the pressure of key path time sequence to piece outside
The output of source of stable pressure is adjusted, so as to change the operating voltage of current chip.
Concrete technical scheme is as follows：
System includes main circuit system platform, frequency adjuster phase-locked loop pll, out-put supply path PMOS switch group, piece
External power managing chip PMIC, performance decision-making module, hardware performance monitoring modular on piece, DVFS control modules on piece, AVS on piece
Control module；
Wherein, on piece hardware performance monitoring modular output by performance decision-making module with piece DVFS control modules it is defeated
Enter end to be connected, the output end of DVFS control modules is connected to frequency adjuster phase-locked loop pll and out-put supply path respectively on piece
The input of PMOS switch group, on the piece of main circuit system platform ring oscillator output end with piece AVS control modules it is defeated
Enter end to be connected, and the output end of AVS control modules is connected with piece external power managing chip PMIC input on piece；
Described upper hardware performance monitoring modular is the hardware circuit module of chip internal, main to monitor on chip bus
Data transfer and director data information, and performance decision-making module is transmitted this information to, performance decision-making module is according to current different
Application scenarios, the performance requirement of current processor is assessed, while following property development demand is predicted by algorithm, to control
The switching of DVFS state machine states；
The out-put supply path PMOS switch group is made up of N number of PMOS switch, and N is greater than 1 integer, its open and
Closure state controls according to the look-up table of DVFS systems activation design；
Described upper DVFS control module mainly includes software switch group, comparator, D/A converting circuit and controller；It is soft
The digit of part switches set matches with PMOS number in the out-put supply path PMOS switch group, and passes through inverter drive
The grid of PMOS transistor；The effect of comparator is that the school of supply voltage is realized by comparison reference voltage and supply voltage
It is accurate；D/A converting circuit adjusts process for power supply and provides voltage-regulation stepping, while provides reference voltage for comparator, and digital-to-analogue turns
The data signal input for changing circuit comes from controller；Controller is the core of power selection circuit, for controlling power supply
The sequential of switching, there is different orders under different switch modes；Simultaneously the controller control power selection circuit other
The effective time of each functional module, not only each several part is set to work in order, and it is complete when whole circuit need not switch
Close, reduce the power dissipation overhead of the circuit.
The main circuit system platform is the SoC chip for including an embedded type CPU processor.Carrying out different applications
, can be by configuring different voltage/frequencies due to different different to the demand of core performance using calculation process during calculation process
Rate point reduces unnecessary power dissipation overhead.
The frequency adjuster phase-locked loop pll provides different frequencies for system.In modern electronic technology, in order to obtain
High-precision frequency of oscillation, generally use quartz oscillator.But the frequency of quartz oscillator does not allow malleable, and sharp
Different system clock frequencys can be easily obtained with phaselocked loop.PLL is dynamically configured by DVFS control modules in the present invention
Parameter be met the system clock frequency of different application scene.
The out-put supply path PMOS switch group realizes the switching between different electrical power voltage rails.Led to by N group power supplys
Cross PMOS switch group and realize and be connected with one of which power supply, because switching is very quick, can be used to voltage and be switched fast.In chip
The power remove of portion's difference voltage domain needs power gating unit (Power-Gating Cell, also referred to as MTCMOS) to realize.Can
To select deenergization (VDD) or ground (VSS) connection to realize Power-Gating, both Power-Gating Cell
Header-Switch and Footer-Switch is referred to as by image.Intend using in the form of Header-Switch in the present invention
The power track cut-out that PMOS is implemented without.
Described external power managing chip PMIC is chip power supply with I2C interface.On the one hand, PMIC adaptations chip currently should
Appropriate voltage is dynamically configured with demand, reduces the power dissipation overhead of chip as far as possible；On the other hand, PMIC is by directly monitoring core
The power grid magnitude of voltage of piece, intense adjustment adaptively is carried out to current voltage compared with reference voltage, to compensate fast electric
The influence of buckling.Adaptive supply voltage regulation is by directly monitoring electric power network, and using inside power management chip
Comparator compare the value of voltage and reference voltage on power grid, to control the voltage output of power management chip, make PMIC
The magnitude of voltage of calibration is exported, so as to compensate quick voltage change.
The performance decision-making module is mainly realized by software, and the work of current system is obtained by hardware performance monitoring module
Make loading condition, the current desired voltage/frequency value of system is obtained by existing algorithm.PMOS switch group open and shut off by
Current desired voltage is worth to, and PLL parameter configuration is determined by the frequency values needed for current system.
Described upper hardware performance monitoring module is that (hardware circuit needs timer and counting within certain sampling period
Device) by Monitoring Data bus and instruction bus respectively, finally give CPI (Clock cycle Per Instruction, table
Show the instruction average clock periodicity for performing some program) value judge the workload of current system.
Described upper DVFS control module mainly by the workload information monitored, selects the electricity for being adapted to present load
Source path and the different parameters for configuring PLL simultaneously, so as to set the voltage/frequency of suitable current work load point.In the present invention
System performance requirements are divided into three levels, are arranged to the form of look-up table, are selected for DVFS control modules.
The method that described upper AVS control module employs static regulation plus dynamic regulation, greatly accelerates governing speed.
At the beginning of chip starts, current chip process deviation is monitored using ring oscillator on piece, passes through I2C protocol integrated test system external power sources
Managing chip dynamic adjusts the operating voltage of chip, suppresses the influence of process deviation.PMIC outside piece is then utilized in chip operation
Voltage change on monitoring power grid in real time, so as to which dynamic debugging system operating voltage is to reduce the influence of voltage deviation.Directly
Connect the comparator inside using power management chip and compare on power grid the value of voltage and reference voltage to control power management
The voltage output of chip, voltage can automatic adjusument and the sampling period it is short, further reduce the time sequence allowances that bring of PVT, so as to
VDD is reduced to reduce power consumption.
Brief description of the drawings
Fig. 1 is the system architecture diagram as first embodiment of the invention；
Fig. 2 is the system platform figure as first embodiment of the invention system architecture diagram；
Fig. 3 is as DVFS of the present invention and AVS associated working ideographs；
Fig. 4 is the hardware circuit realization as DVFS of the present invention and AVS joint regulation strategies；
Fig. 5 is to switch simulation waveform from low to high as DVFS of the present invention control power supplys
Fig. 6 be as AVS of the present invention under conventional voltage voltage-regulation simulation waveform
Fig. 7 is as AVS voltage-regulations control signal truth table of the present invention
Embodiment
Technical solution of the present invention is described in detail below in conjunction with the accompanying drawings, but protection scope of the present invention is not limited to
The embodiment.
Embodiment：
Fig. 1 is the system architecture diagram of the embodiment of the present invention, realizes quick voltage regulation, significantly reduces power consumption
Expense, and can quickly compensate quick voltage change.The system includes main circuit system platform 1；Frequency adjuster phaselocked loop
PLL2；Out-put supply path PMOS switch group 3；Piece external power managing chip PMIC4；Performance layer decision-making module 5；Hardware on piece
Can monitoring modular 6；DVFS control modules 7 on piece；AVS control modules 8 on piece.
Wherein, the bus signals of main circuit system platform 1 are output to the input of hardware performance monitoring modular 6 on piece.Piece
External power managing chip PMIC4 is that main circuit system platform 1 is powered by out-put supply path PMOS switch group 3.Main circuit system
The power supply of system platform 1 is the input of comparator in piece external power managing chip PMIC 4.The input of DVFS control modules 7 is on piece
The end value that the output of hardware performance monitoring modular 6 obtains by performance decision-making module on piece.DVFS control modules 7 is defeated on piece
Go out the input control signal for frequency adjuster phase-locked loop pll 2 and out-put supply path PMOS switch group 3.AVS controls mould on piece
The input signal of block 8 be main circuit system platform 1 monitoring path timing information, output signal connection sheet external power managing chip
PMIC4 input.
The main circuit system platform 1 is the SoC chip for including an embedded type CPU processor, and the chip is public using ARM
Take charge of the Advanced Microcontroller Bus Architecture (Advanced Microcontroller Bus Architecture, AMBA) of research and development
Structure, includes Cortex-M3 kernels, embedded SRAM (Embedded Static Random Access
Memory, ESRAM), Advanced Encryption Standard (Advanced Encryption Standard, AES) module, universal asynchronous receiving-transmitting
Device (Universal Asynchronous Receiver/Transmitter, UART) and Advanced High-Performance Bus
(Advanced High Performance Bus, AHB), advanced peripheral bus (Advanced Peripheral Bus,
APB).The main circuit system platform is when carrying out different application calculation process, because different application calculation process is to kernel
The demand of performance is different, can reduce unnecessary power dissipation overhead by configuring different voltage/frequency points.
DVFS and AVS joint regulations strategy is realized by the relatively slow AVS fine tunings two parts of DVFS Fast Coarses mediation respectively.
Associated working pattern between the two is：From upper layer software (applications) to property needed for the specified register of hardware circuit write-in current processor
Energy state, the parameter of DVFS control modules is configured, and the switching to multiple power supplies rail is realized by DVFS control modules, the process is simultaneously
The output valve of the outer source of stable pressure of piece is not changed.AVS control modules reduce system design using adaptive supply voltage regulative mode
In the voltage margin that leaves.The module directly monitors electric power network, by monitor the pressure of key path time sequence to piece outside
The output of source of stable pressure is adjusted, so as to change the operating voltage of current chip.The structure chart of DVFS and AVS joint regulation strategies
As shown in Figure 2：
The detailed operation flow of the present invention is as follows.
The first step：Before System on Chip/SoC startup, AVS control modules 8 are being tested by ring oscillator on monitoring piece on piece
When PMIC voltage set into write-in look-up table, set voltage inclined to compensate current chip technique according to ring oscillator result
Difference.This process is referred to as AVS static calibrations.When ring oscillator concussion number is relatively fewer, illustrate that now process corner is poor, should
When according to the higher voltage of look-up table setting；When ring oscillator concussion number is relatively more, illustrate that now process corner is preferable,
Relatively low voltage should be set according to look-up table.
Second step, during chip operation, it is current to obtain reflection within certain sampling period for hardware performance monitoring modular on piece
The parameter of system workload, and DVFS control modules are output control signals to by performance decision-making module.
3rd step, a certain layer on piece in DVFS control modules selection look-up table meet the electricity of current system requirement critical value
Pressure/Frequency point, while opening and shutting off for PLL and PMOS switch group is respectively configured.
4th step, triggers internal set signal flag while system platform performance requirement changes, this signal represents performance
Demand is improved or reduced.
5th step, after PLL and power switch PMOS groups are in stable state, further to reduce voltage margin, it will adopt
Voltage, for controlling the voltage output of power management chip, makes compared with the value of reference voltage on the power grid collected
The magnitude of voltage of PMIC output calibrations is to compensate quick voltage change.This process is referred to as AVS dynamic calibrations.Two of which voltage
Compare using the comparator inside PMIC power management chips to realize.
Two key modules that the fast source voltage regulating system of the present invention is related to are introduced separately below.
First, DVFS control modules 7 on piece
As shown in Fig. 4 dotted portions, quick DVFS handover module main functions are selection power supplys on piece, wherein mainly including
Software switch group, comparator, digital analog converter and controller, power supply selection function is completed together with PMOS switch group.Software is opened
The digit of pass group matches with PMOS number in the out-put supply path PMOS switch group 3, and passes through inverter drive
The grid of PMOS transistor；The effect of comparator is that the school of supply voltage is realized by comparison reference voltage and supply voltage
It is accurate；D/A converting circuit adjusts process for power supply and provides voltage-regulation stepping, while provides reference voltage for comparator, and digital-to-analogue turns
The data signal input for changing circuit comes from controller；Controller is the core of power selection circuit, for controlling power supply
The sequential of switching, there is different orders under different switch modes；Simultaneously the controller control power selection circuit other
The effective time of each functional module, not only each several part is set to work in order, and it is complete when whole circuit need not switch
Close, reduce the power dissipation overhead of the circuit.
When DVFS is adjusted, upper layer software (applications) system (performance decision-making module) can be assessed according to current different application scenarios
The performance requirement of current processor, while following property development demand is predicted by existing algorithm.By controlling bottom circuit
In special register group (register in Fig. 4), write different performance demand under corresponding state value.The register group will match somebody with somebody
The parameter of DVFS control modules is put, and then realizes and supply frequency regulation is carried out to chip circuit.The register control DVFS of chip
State machine state switch, when obtained after coding h2I signals it is effective when, show now to need to be switched to low-load from high load condition
State, current adjustment state are changed into VLOW.Controller enables each funtion part of power supply selecting module, and constantly to number
Weighted-voltage D/A converter inputs data signal, reference voltage of the analog voltage for being allowed to export as comparator.The other end of comparator
For the output voltage of power selection circuit, the output control of comparator software switch group is opened and broken, while software switch group
Control opening and breaking for power gating switch element again, eventually through power gating unit open and the regulation power supply selection circuit that breaks
Voltage output, realize the switching of voltage from high to low.Wherein Clk be power selection circuit working frequency, h2I be voltage from
High to Low switching useful signal, I2h are that voltage switches useful signal to height, and Vcore is the final output result of the circuit.
2nd, AVS control modules 8 on piece
Adaptive voltage scaling part is broadly divided into two stages, respectively static auto-calibration stage and dynamic duty rank
Section.Wherein initial phase is self-calibration phase after silicon, and electrifying startup is initialized every time once in chip, is closed for calibrating to replicate
Key path is allowed to approach actual critical path, so that replicated critical path can accurately simulate prolonging for actual critical path
Late.Dynamic duty stage, edge detection circuit obtain the delay information of replicated critical path in real time, at the same with threshold set in advance
Value reference point is compared, and when the sequential allowance monitored is more than the reference point, can be reduced by the DC/DC outside adjustment sheet
Supply voltage；When the sequential allowance monitored is less than the reference point, by adjustment sheet outside DC/DC rise supply voltage.
It is illustrated in figure 5 DVFS control power supplys and switches simulation waveform from high to low.Wherein Vcore is reality output power supply electricity
Pressure, is modulated by one group of PMOS transistor.C2s represents the closed loop useful signal of whole power selection circuit, and En_I is represented
Tlow control signal, h2I and I2h represent to switch useful signal from high to low and from low to high, Result expression ratios respectively
Compared with the output of device, Vref is the reference voltage of comparator, and S [14: 0] is software switch group signal, and data [5: 0] is digital-to-analogue conversion
The input of device.It can be seen that reference voltage of the output of digital analog converter as analog comparator, obtained comparative result is all the time
For 0, meet under switch mode from high to low, Result result is always 0, so passes through shift register output
PMOS grid control signals are followed successively by height, constantly close transistor, make the contribution of high level fewer and fewer, are connect until being reduced to
Low level turns on when being bordering on 0.6V or so, i.e. signal En_I in Fig. 5 is effective.Final output supply voltage is 0.6V.Fig. 5 is verified
The function of DVFS control quick power switchings.
It is illustrated in figure 6 adaptive supply voltage under conventional voltage and adjusts waveform.The primary condition of emulation is (SS techniques
Angle, 1.1V, 125 DEG C), voltage reduces since 1.1V during emulation.The power supply source of chip is provided by source of stable pressure outside piece, in emulation
Described using the C model functional module compatible with HSIM netlists.
CLK is clock signal in Fig. 6, and vol_con_0 and vol_con_1 are voltage control signal, and out_reg is monitoring electricity
The output on road, Vout are the outer source of stable pressure virtual voltage output valve of piece.When control signal vol_con_0 is high, vol_con_1 in figure
For it is low when, AVS control reduce voltage；When the output of observation circuit reaches threshold point, (SS, 0.92V, circuit is defeated corresponding to 125 DEG C
Go out) when being 32 ' he000_0000, vol_con_0 is changed into low, and vol_con_1 is changed into high, AVS control rise voltages, in Fig. 6
Shown in red frame.Fig. 6 demonstrates AVS dynamic calibration processes.
In Fig. 7, voltage-regulation control signal truth table, as volt_con [1: 0]=2 ' b00, voltage keeps currency；
As volt_con [1: 0]=2 ' b10, illustrate that current sequential is more loose, reduction voltage that can be appropriate；As volt_con [1
: 0]=2 ' during b10, illustrate current sequential more anxiety, it is necessary to raise voltage to ensure that the function of circuit is correct.Work as voltage-regulation
In when rising or reducing the stage, the stepping adjusted every time is 20mV.
Claims (3)
- A kind of 1. fast source voltage regulating system, it is characterised in that：The system includes main circuit system platform（1）, frequency adjust Whole device phase-locked loop pll（2）, out-put supply path PMOS switch group（3）, piece external power managing chip PMIC（4）, performance decision model Block（5）, hardware performance monitoring modular on piece（6）, DVFS control modules on piece（7）, AVS control modules on piece（8）；Wherein, hardware performance monitoring modular on piece（6）Output pass through performance decision-making module（5）With DVFS control modules on piece （7）Input be connected, DVFS control modules on piece（7）Output end be connected to frequency adjuster phase-locked loop pll respectively（2）With it is defeated Go out power track PMOS switch group（3）Input, main circuit system platform（1）Piece on ring oscillator output end and piece AVS control modules（8）Input be connected, and AVS control modules on piece（8）Output end and piece external power managing chip PMIC（4）Input be connected；Described upper hardware performance monitoring modular（6）It is the hardware circuit module of chip internal, it is main to monitor on chip bus Data transfer and director data information, and transmit this information to performance decision-making module（5）, performance decision-making module（5）According to work as Preceding different application scenarios, assess the performance requirement of current processor, while predict the property development demand in future, to control The switching of DVFS state machine states；The out-put supply path PMOS switch group（3）By N number of PMOS switch form, N is greater than 1 integer, its open and Closure state controls according to the look-up table of DVFS systems activation design；Described upper DVFS control module（7）Mainly include software switch group, comparator, D/A converting circuit and controller；It is soft The digit of part switches set and the out-put supply path PMOS switch group（3）Middle PMOS number matches, and passes through phase inverter Drive the grid of PMOS transistor；The effect of comparator is to realize supply voltage by comparison reference voltage and supply voltage Calibration；D/A converting circuit adjusts process for power supply and provides voltage-regulation stepping, while provides reference voltage, digital-to-analogue for comparator The data signal input of change-over circuit comes from controller；Controller is the core of power selection circuit, for controlling electricity The sequential of source switching, has different orders under different switch modes；Simultaneously the controller control power selection circuit its The effective time of his each functional module, not only each several part is set to work in order, and it is complete when whole circuit need not switch Contract fully, reduce the power dissipation overhead of the circuit.
- 2. fast source voltage regulating system according to claim 1, it is characterised in that AVS control modules on piece（8）Adopt The voltage margin left in system design is reduced with adaptive supply voltage regulative mode；AVS control modules on piece（8）Directly Electric power network is monitored, and the value of voltage and reference voltage on power grid is compared using the comparator inside power management chip, To control the voltage output of power management chip, make piece external power managing chip PMIC（4）The magnitude of voltage of calibration is exported, so as to mend Repay quick voltage change.
- 3. the method that the fast source voltage regulating system described in application claim 1 or 2 carries out voltage adjustment, it is characterised in that Mainly include the following steps that：Step 1：Start initial, AVS control modules on piece in System on Chip/SoC（8）Pass through the vibration time of ring oscillator on monitoring piece Number, output voltage adjust signal to piece external power managing chip PMIC（4）, current chip process deviation is compensated, it is static to carry out AVS Calibration；Step 2：When chip normal work, hardware performance monitoring modular on piece（6）Reflected within certain sampling period The parameter of current system workload, and by performance decision-making module（5）Output control signals to DVFS control modules on piece（7）； DVFS control modules on piece（7）A certain layer in selection look-up table meets the voltage/frequency point of current system requirement critical value, together When output signal control frequency adjuster phase-locked loop pll（2）With out-put supply path PMOS switch group（3）；Step 3：When frequency adjuster phase-locked loop pll（2）After being in stable state with out-put supply path PMOS switch group, to enter One step reduces voltage margin, magnitude of voltage output and piece external power managing chip PMIC on chip power grid（4）Input It is connected, last internal comparator input makes piece external power managing chip PMIC（4）The magnitude of voltage of calibration is exported, compensates quickly electricity Buckling, carry out AVS dynamic calibrations.
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| CN113504826B (en) * | 2021-08-04 | 2023-04-14 | 上海壁仞智能科技有限公司 | Dynamic voltage frequency adjusting circuit and dynamic voltage frequency adjusting method |
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| CN102411395B (en) * | 2011-08-08 | 2014-02-05 | 东南大学 | Dynamic voltage-regulating system based on on-chip monitoring and voltage forecasting |
| US9323320B2 (en) * | 2012-05-18 | 2016-04-26 | Mediatek Singapore Pte. Ltd. | Weighted control in a voltage scaling system |
| KR20140030823A (en) * | 2012-09-04 | 2014-03-12 | 삼성전자주식회사 | Soc performing dynamic voltage and frequency scaling policies using 3d workload and method using the same |
| CN102879631A (en) * | 2012-09-18 | 2013-01-16 | 华为技术有限公司 | Voltage detection device, system and method |
| CN105183062B (en) * | 2015-08-13 | 2016-09-07 | 东南大学 | Adaptive voltage scaling system based on on-line monitoring and monitoring path screening technique |
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