CN106814305B - A kind of SIP module test method based on piece Embedded micro-system - Google Patents
A kind of SIP module test method based on piece Embedded micro-system Download PDFInfo
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- CN106814305B CN106814305B CN201611205402.0A CN201611205402A CN106814305B CN 106814305 B CN106814305 B CN 106814305B CN 201611205402 A CN201611205402 A CN 201611205402A CN 106814305 B CN106814305 B CN 106814305B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/3167—Testing of combined analog and digital circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
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- General Physics & Mathematics (AREA)
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- Tests Of Electronic Circuits (AREA)
Abstract
A kind of SIP module test method based on piece Embedded micro-system is written and read whole addresses of all memory cells first with the CPU element inside SIP module, to test the correctness of memory cell；Then internal closing self-test is carried out to SIP module innernal CPU unit and external auxiliary is tested, to verify the correctness of CPU element；SIP module inside FPGA is tested finally by innernal CPU unit and outside FPGA.The method of the present invention is not on the basis of improving SIP module design complexities, effectively SIP module function, interconnected are tested, the demand for meeting the full Test coverage of SIP module to the full extent improves testing efficiency on the basis of guaranteeing SIP module correctness.
Description
Technical field
The present invention relates to a kind of SIP module test method, especially a kind of SIP module based on piece Embedded micro-system
Test method belongs to IC design field.
Background technique
Requirement with user to electronic system or complete electronic set grows to even greater heights, and electronic system or complete electronic set are towards more
Function, high-performance, miniaturization, lightness, portability, high speed, low-power consumption and highly reliable direction are developed.SIP(system in
A package, system in package) technology, by the circuit integration of a variety of different function within an encapsulation, for realizing certain
Substantially complete function.As the effective ways for promoting monolithic processor function, SIP obtains industry and greatly pays close attention to, in recent years
To obtain very fast development.
Since the concept source of SIP is in the design of encapsulation, most research is all directed to the encapsulation process of SIP module.SIP
Module on processor architecture, and with ASIC (application specific integrated circuit, it is dedicated integrated
Circuit) there are certain difference, traditional ATE (automatic test equipment, automatic test equipment) test mode needle
To the integrated circuit of simple function, Test coverage will lead to not when testing for the SIP module based on piece Embedded micro-system
Entirely, testing efficiency is low.
Summary of the invention
In the present invention technology solve the problems, such as be: overcome the deficiencies in the prior art proposes a kind of to decline based on piece insertion
The SIP module test method of system, this method is not on the basis of improving SIP module design complexities, effectively to SIP module
Function, interconnected are tested, and meet the demand of the full Test coverage of SIP module to the full extent, are guaranteeing SIP module just
On the basis of true property, testing efficiency is improved.
The technical solution of the invention is as follows: a kind of SIP module test method based on piece Embedded micro-system, including
The following steps:
(1) using the CPU element inside SIP module, whole addresses of all memory cells are written and read, with
Test the correctness of memory cell；
(2) internal closing self-test is carried out to SIP module innernal CPU unit and external auxiliary is tested, to verify CPU element
Correctness；
(3) following test is carried out to SIP module inside FPGA:
By external FPGA to FPGA input clock inside SIP module, and check internal FPGA's by external FPGA
Whether lock signal locks, to test the correctness of internal FPGA working frequency；
Using MARCH C algorithm, by CPU element, internally whole addresses of the configurable RAM of FPGA are written and read behaviour
Make, to test the correctness of configurable RAM；
Crystal oscillator provides input frequency, and internal FPGA carries out different degrees of frequency multiplication, checks internal FPGA by external PPGA
Lock signal, separately verify under low frequency mode and high frequency mode whether internal FPGA works normally, to test delay locked loop
Correctness.
The SIP module, outside FPGA and peripheral circuit are arranged on hardware test platform, the hardware test platform
Electric signal, earth signal, clock signal are provided for SIP module, outside FPGA and peripheral circuit, and realizes that plate grade interconnects.
In the step (2), the implementation method of inside closing self-test are as follows: data are written to CPU element internal register,
Whether the function to be realized according to internal register, the data read in conjunction with logic judgment verifying from internal register are correct；
The implementation method of external auxiliary test are as follows: by peripheral circuit to CPU element input stimulus, CPU element acquisition or
Output signal is acquired by external FPGA, and CPU is judged by input stimulus, output signal and the internal logic being pre-designed
Whether unit design is correct.
The method that whole addresses of all memory cells are written and read in the step (1) are as follows:
(4.1) CPU element is memory first half memory space loading code, is deposited with realizing to memory latter half
The storage all units in space are written and read；
(4.2) read-write cycle is changed, all units of memory latter half memory space is written and read；
(4.3) CPU element is memory latter half memory space loading code, to realize to first half memory space
All units are written and read；
(4.4) read-write cycle is changed, all units of memory first half memory space is written and read.The present invention
Beneficial effect compared with prior art is:
(1) the invention proposes the SIP modules based on piece Embedded micro-system of complete set to test design cycle, fills out
The blank for having mended current SIP module test design cycle, it is incomplete to compensate for traditional ATE test mode Test coverage, test effect
The low defect of rate, meets the demand of the full Test coverage of SIP module to the full extent, on the basis for guaranteeing SIP module correctness
On, improve testing efficiency.
(2) present invention test design on, not only only account for SIP module test integrality, while by testing efficiency,
Within the scope of testing cost, test necessity etc. are taken into consideration, therefore on the basis of Complete test, to memory cell
Test is optimized, and by the way that code is written to one half space of memory, realizes the read-write operation to the other half memory space, greatly
The efficiency and test validity for improving test greatly reduce test redundancy and testing time.
Detailed description of the invention
Fig. 1 is hardware test platform design diagram of the present invention.
Specific embodiment
The method of the invention is based on design side, and production link is not within invention scope.The present invention uses SIP
The test design method of module includes two parts: hardware test platform design and software test conceptual design.Two parts are set
Involving between meter is larger, needs to coordinate simultaneously to carry out.
Fig. 1 is hardware test platform design diagram of the invention, and peripheral circuit is full page (including device under test) offer
System resource (electric signal, earth signal, clock signal etc.) and the interconnection of plate grade；CPU pin is connect with inside FPGA in SIP module,
CPU and FPGA respective pins can be tested；External fpga chip receives SIP module part output signal, and accesses output signal
As a result, being read for test macro.
A kind of SIP module test method based on piece Embedded micro-system, including the following steps:
(1) hardware test platform is designed, SIP module, outside FPGA and peripheral circuit are arranged in hardware test platform
On, hardware test platform is SIP module, outside FPGA and peripheral circuit provide electric signal, earth signal, clock signal, and real
Existing plate grade interconnection.
(2) using the CPU element inside SIP module, whole addresses of all memory cells are written and read, with
Test the correctness of memory cell；
The method being written and read to whole addresses of all memory cells is as follows:
(a) CPU element is memory first half memory space loading code, and to latter half memory space, each is deposited
0x55 is written simultaneously in storage unit, and reads the data of each storage unit simultaneously, stores sky to memory latter half to realize
Between all units be written and read；
(b) read-write cycle is changed, 0xAA is written to each storage unit of latter half memory space, and read each deposit
The data of storage unit；
(c) CPU element is memory latter half memory space loading code, and to first half memory space, each is deposited
0x55 is written simultaneously in storage unit, and reads the data of each storage unit, to realize to memory first half memory space institute
There is unit to be written and read；
(d) read-write cycle is changed, 0xAA is written to all units of memory first half memory space, and read each deposit
The data of storage unit.
By write-in data and data comparison is read, unanimously then Memory Storage Unit function is correct；Otherwise incorrect.
(3) internal closing self-test is carried out to SIP module innernal CPU unit and external auxiliary is tested, to verify CPU element
Correctness；
The implementation method of inside closing self-test are as follows: data are written to CPU element internal register, according to internal register
Whether the function to be realized, the data read in conjunction with logic judgment verifying from internal register are correct；
Such as by taking the timer in CPU element as an example, judge timer it is enabled/whether forbidden energy function correct:
The judgement of timer ena-bung function: CPU element configuration is interrupted and carry interrupt handling routine；Enabled timer is simultaneously continuous
Timer count register value is read, if the numerical value constantly changes, interrupt handling routine is interrupted and entered to final generate, this
Test passes through；If phenomenon is not inconsistent with above-mentioned expected results, this test crash.
The judgement of timer forbidden energy function: constantly reading timer count register value, which will not generate variation and have no
Method generates interruption, this test passes through；If phenomenon is not inconsistent with above-mentioned expected results, this test crash.
Such as by taking the house dog in CPU element as an example, judge whether house dog tally function is correct:
House dog is configured, house dog is not enabled, the read-write operation of multiple groups different data is carried out to house dog counter register,
If data of reading back and write-in Data Matching, this test pass through；If mismatching, this test crash.
House dog is configured, house dog is enabled；Repeatedly read-write timer count register, if repeatedly reading data display counting
The variation of register count value, and final generation system reset signal, this test pass through；If counter register count value is without change
Change, or can not generation system reset signal, this test crash.
The implementation method of external auxiliary test are as follows: peripheral circuit, can be straight for CPU element to CPU element input stimulus
The functional module for reading data is connect, CPU element obtains the output signal of the corresponding function module by reading internal register；
The functional module of data cannot be directly read for CPU element, external FPGA acquires output signal, and CPU element returns
Read the output signal of external FPGA acquisition；
By input stimulus, output signal and the internal logic being pre-designed, judge whether CPU element design is correct.
Such as by taking the A/D conversion module in CPU element as an example, judge whether A/D conversion function is correct:
Being inputted by peripheral circuit to A/D conversion module is fixed level (3.3V/0V), and A/D conversion module carries out level
Conversion；CPU element reads back change data, is compared with default value；If change data can connect with default value error
It receives range (1%), this test passes through；If change data and default value error are in acceptable outer, this test crash.
Such as by taking the GPIO module in CPU element as an example, judge whether GPIO module output function is correct:
By configuring external fpga logic circuit, realize that 16 tunnel user IO of GPIO module is connected with FPGA pin, FPGA draws
Foot signal condition maps in internal register；16 tunnel user IO are set for output, FPGA pin is input；Pass through peripheral circuit
It to GPIO module input stimulus, is exported by user IO and gives external FPGA more kinds of output signals combinations, CPU element is by FPGA pin
Input signal is read back；By the data read back compared with initial data, if data are consistent, this test passes through；It, should if data are not inconsistent
Item test crash.
(3) following test is carried out to SIP module inside FPGA:
By external FPGA to FPGA input clock inside SIP module, and check internal FPGA's by external FPGA
Whether lock signal locks, and locking then illustrates that the working frequency test of internal FPGA passes through, and does not otherwise pass through.
Such as it can reach to the FPGA input clock 25MHz inside SIP module by two frequencys multiplication three times by external FPGA
200MHz, external FPGA check whether lock signal locks, and the test of the function can be completed.
Using MARCH C algorithm, by CPU element, internally whole addresses of the configurable RAM of FPGA are written and read behaviour
Make, to test the correctness of configurable RAM.
Crystal oscillator provides input frequency, and internal FPGA carries out different degrees of frequency multiplication, checks internal FPGA by external PPGA
Lock signal, separately verify under low frequency mode and high frequency mode whether internal FPGA works normally, if normally, be delayed lock
Phase ring is correct.If abnormal, delay locked loop is incorrect.
Such as: there are two operating mode, low frequency mode (25M-90MHz) and high frequency modes (60M-190MHz) by DLL, and crystal oscillator is defeated
Entering frequency is 25MHz, by two frequencys multiplication to 50MHz, by checking Lock signal testing low frequency mode 25MHz and 50MHz
Under lower and high frequency mode 100MHz, whether internal FPGA be can work normally, if can be with, delay locked loop be correct,
If there is a mode internal FPGA cisco unity malfunction, then delay locked loop design is incorrect.
Realize above-mentioned different test function by different programming languages when test: (SPARC converges embedded assembler code
Compile) it designs and is tested mainly for units such as SIP module inside IU, FPU and TRAP；Embedded type C language design mainly for
SIP module innernal CPU function items, SRAM, SDRAM, Flash, FPGA assembly unit, interconnector and part pin connect progress
Test；Hardware language (Verilog/VHDL) design is mainly responsible for FPGA and onboard external fpga chip inside configuration SIP module,
It is configured to the logic circuit of test software needs, is realized to SIP module part output function, the connection of part pin and part
The test of line.
The present invention as needed configures FPGA inside onboard fpga chip and SIP module to pre-designed logic electricity
Road is executed by software-hardware synergism, realizes that the global function for SIP module is tested.This method is not improving SIP module design again
On the basis of miscellaneous degree, effectively SIP module function, interconnected, external pin etc. are tested, met to the full extent
The demand of the full Test coverage of SIP module improves testing efficiency, is effectively ensured on the basis of guaranteeing SIP module correctness
The coverage rate of test, completeness and efficiency.
The content that description in the present invention is not described in detail belongs to the well-known technique of professional and technical personnel in the field.
Claims (4)
1. a kind of SIP module test method based on piece Embedded micro-system, it is characterised in that include the following steps:
(1) CPU element for utilizing SIP module, is written and read whole addresses of all memory cells, to test storage
The correctness of device unit；
(2) internal closing self-test is carried out to SIP module CPU element and external auxiliary is tested, to verify the correct of CPU element
Property；
(3) following test is carried out to SIP module inside FPGA:
By external FPGA to FPGA input clock inside SIP module, and check that the lock of internal FPGA believes by external FPGA
Number whether lock, to test the correctness of internal FPGA working frequency；
Using MARCH C algorithm, by CPU element, internally whole addresses of the configurable RAM of FPGA are written and read,
To test the correctness of configurable RAM；
Crystal oscillator provides input frequency, and internal FPGA carries out different degrees of frequency multiplication, checks internal FPGA's by external PPGA
Lock signal, separately verifies whether internal FPGA under low frequency mode and high frequency mode works normally, to test delay locked loop
Correctness.
2. a kind of SIP module test method based on piece Embedded micro-system according to claim 1, feature exist
In: the SIP module, outside FPGA and peripheral circuit are arranged on hardware test platform, and the hardware test platform is SIP
Module, outside FPGA and peripheral circuit provide electric signal, earth signal, clock signal, and realize that plate grade interconnects.
3. a kind of SIP module test method based on piece Embedded micro-system according to claim 1, feature exist
In: in the step (2), the implementation method of inside closing self-test are as follows: data are written to CPU element internal register, according to
Whether the function to be realized of internal register, the data read in conjunction with logic judgment verifying from internal register are correct；
The implementation method of external auxiliary test are as follows: by peripheral circuit to CPU element input stimulus, CPU element acquires or passes through
External FPGA acquisition output signal judges CPU element by input stimulus, output signal and the internal logic being pre-designed
It whether correct designs.
4. a kind of SIP module test method based on piece Embedded micro-system according to claim 1, feature exist
In: the method that whole addresses of all memory cells are written and read in the step (1) are as follows:
(1.1) CPU element is memory first half memory space loading code, stores sky to memory latter half to realize
Between all units be written and read；
(1.2) read-write cycle is changed, all units of memory latter half memory space is written and read；
(1.3) CPU element is memory latter half memory space loading code, all to first half memory space to realize
Unit is written and read；
(1.4) read-write cycle is changed, all units of memory first half memory space is written and read.
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| CN108693465A (en) * | 2018-03-30 | 2018-10-23 | 北京联想核芯科技有限公司 | A kind of test control method, circuit and system |
| CN111277449B (en) * | 2018-12-05 | 2021-08-13 | 中国移动通信集团广西有限公司 | Safety testing method and device for voice service equipment |
| CN109557459A (en) * | 2018-12-20 | 2019-04-02 | 北京时代民芯科技有限公司 | A kind of jtag test method of SiP system and its inside chip based on jtag test |
| CN109633415B (en) * | 2018-12-28 | 2021-08-10 | 泰斗微电子科技有限公司 | Abnormal chip identification method and equipment |
| CN111856916A (en) * | 2019-04-30 | 2020-10-30 | 联合汽车电子有限公司 | External clock diagnosis method |
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| WO2006061668A1 (en) * | 2004-12-07 | 2006-06-15 | Infineon Technologies Ag | Test time reduction for multi-chip modules (mcm) and for system-in-packages (sip) |
| US7535214B2 (en) * | 2007-04-12 | 2009-05-19 | Chroma Ate Inc | Apparatus for testing system-in-package devices |
| JP2009074921A (en) * | 2007-09-20 | 2009-04-09 | Panasonic Corp | Semiconductor device |
| TW201031937A (en) * | 2009-02-20 | 2010-09-01 | Aiconn Technology Corp | Batch testing method for a SIP device and batch testing system thereof |
| TWI439710B (en) * | 2009-11-18 | 2014-06-01 | Univ Nat Sun Yat Sen | Testing device for a passive component embedded in sip |
| CN103969572B (en) * | 2013-02-05 | 2017-05-17 | 泰斗微电子科技有限公司 | SIP (system in package) chip testing platform and method |
| CN105279321B (en) * | 2015-10-10 | 2019-02-01 | 北京时代民芯科技有限公司 | A kind of SIP module design method based on plate level verification test macro |
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