CN109557459A - A kind of jtag test method of SiP system and its inside chip based on jtag test - Google Patents
A kind of jtag test method of SiP system and its inside chip based on jtag test Download PDFInfo
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- CN109557459A CN109557459A CN201811564790.0A CN201811564790A CN109557459A CN 109557459 A CN109557459 A CN 109557459A CN 201811564790 A CN201811564790 A CN 201811564790A CN 109557459 A CN109557459 A CN 109557459A
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- jtag
- chip
- test
- sip
- protocol
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318597—JTAG or boundary scan test of memory devices
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
Abstract
The jtag test method of the present invention relates to a kind of SiP system and its inside chip based on jtag test.The SiP includes the chip of jtag test access port, at least two obedience JTAG protocols, it is denoted as the first JTAG chip and last bit JTAG chip, the test input of jtag test access port is connected on the jtag test input terminal of the first JTAG chip, the first JTAG chip jtag test output end is connected with last bit JTAG chip testing input terminal, last bit JTAG chip testing output end is connected to the test output terminal of jtag test access port, constitutes the jtag test link of SiP；Other chips to be measured are if the chip for obeying JTAG protocol in SIP, then in the jtag test link for inserting it into SIP in such a way that boundary scan cell interconnects；If the chip or Logic Cluster for disobeying JTAG protocol, then the boundary scan cell of itself and the chip for obeying JTAG protocol is interconnected, test data transmission is carried out by the jtag test link of SIP.The present invention completes the transmission of functional test data by JTAG link, realizes inside chip test.
Description
Technical field
The present invention is a kind of SiP system and its inside chip test method based on jtag test, is to survey plate grade JTAG
Examination technological borrowing is applied to the test method in SiP module testing.
Background technique
System in package (Systemin Package, SIP) is quickly grown in recent years, is miniaturization of electronic products, light
Quantify, the important implementation of multifunction, has become important Advanced Packaging and system integration technology.SIP module will not
The circuit (majority is chip (Bare-die), can also be chip and discrete component) of same type is integrated in the same encapsulation,
Passive device function in part is realized in high density interconnection substrate, realizes interconnection and mechanical erection, is finally completed and is all or in part
The function of system, the circuit that integrates can be different function, different process, different conditions, greatly reduce the system integration
Difficulty and requirement improve engineering and realize feasibility, realize heterogeneous integration.
Because SIP designing technique is originally derived from encapsulation design, at present focus mostly on the research of SIP module in envelope
Dress process is related, such as interconnects implementation, baseplate material, and for SiP module testing also in the theoretical discussion stage, without work
Journeyization research, also none targetedly test method.
Summary of the invention
Technology of the invention solves the problems, such as: in place of overcome the deficiencies in the prior art, providing a kind of based on jtag test
The jtag test method of SiP system and its inside chip, for realizing for completely enclosed in SiP or half completely enclosed chip
Effective efficiency test, while hardware platform needed for test is simple, testing scheme planning efficiency is high, optimizes function in SiP module
The problem that test approaches are more, test is complicated.
The technical solution of the invention is as follows: a kind of SiP system based on jtag test, the SiP includes jtag test
The chip of access port, at least two obedience JTAG protocols, is denoted as the first JTAG chip and last bit JTAG chip, and jtag test is visited
Ask that the test input TDI of port is connected on the jtag test input terminal TDI of the first JTAG chip, the first JTAG chip JTAG
Test output terminal TDO is connected with last bit JTAG chip testing input terminal TDI, and last bit JTAG chip testing output end TDO is connected to
The test output terminal TDO of jtag test access port constitutes the jtag test link of SiP；Other chips to be measured are if clothes in SIP
From the chip of JTAG protocol, then boundary scan cell interconnect by way of insert it into SIP jtag test link in；If
It is for the chip or Logic Cluster for disobeying JTAG protocol, then it is mutual with the boundary scan cell for the chip for obeying JTAG protocol
Even, test data transmission is carried out by the jtag test link of SIP.
The Logic Cluster is comprising one and more than one chip, for realizing the chipset of specific function.
If the chip for disobeying JTAG protocol is the chip comprising DFT or BIST, by the port of DFT or BIST
It is connected with the boundary scan cell for the chip for obeying JTAG protocol.
The Logic Cluster for disobeying JTAG protocol passes through the side of input port and output port and the chip for obeying JTAG protocol
Boundary's scanning element is connected.
Another technical solution of the invention is: the jtag test method of above-mentioned SiP internal system chip, this method
Include the following steps:
(1), in plate grade jtag test software, the test model of each chip in SiP is established；The test model of the chip
Including logic port, pin mapping, design for Measurability information；
(2), according to chip interconnected relationship in SIP, chip testing model each in SiP is interconnected, constitutes SIP system testing mould
Type；
(3), it is chip under test preparatory function test file in SiP according to the testing requirement of chip under test in SiP, and matches
Set corresponding functional test model；The functional test file includes being written by JTAG into chip under test or Logic Cluster
Data inside data and the chip under test read by JTAG mouthfuls；
(4), operation function test model executes corresponding functional test, completes to survey by JTAG mouthfuls of observation test results
Examination.
Preferably, to the chip testings for obeying JTAG protocol all in SIP system testing model before executing step (3)
Model successively carries out integrity test and interconnecting test, guarantees that jtag test mechanism and JTAG link function are just in SiP module
Often.
Preferably, in the step (1), when chip is to obey the chip of JTAG protocol in SiP, the design for Measurability
Information refers to: the setting of jtag test port, command register and test data register, wherein test data register includes side
Boundary's scanning element；
When chip is the chip for disobeying JTAG protocol in SiP, the design for Measurability information refer to DFT or
BIST。
Preferably, for the chip for obeying JTAG protocol, the functional test model includes passing through available chip-scale
The write-in and reading of jtag test vector realization data.
Preferably, for that can survey chip comprising DFT or BIST, the functional test model includes the JTAG by SiP
The boundary scan cell tested on the JTAG chip that link-access and DFT or BIST are interconnected realizes the write-in and reading of data.
Preferably, for Logic Cluster, the functional test model include by the jtag test link-access of SiP with
Boundary scan cell on the JTAG chip of Logic Cluster interconnection realizes the write-in and reading of data.
Compared with the prior art, the invention has the advantages that:
(1), based on jtag port and boundary scan link realize testing mechanism outside module to the access of SiP inside modules with
Control improves the controllability and accessibility of SiP inside modules；
(2) the jtag test link for passing through SiP module is realized logical with testing mechanism outside SiP to being realized based on JTAG link
The control of the chip functions test of letter, does not increase new test structure, can directly make in the SiP module for designed completion
With；
(3) by that can survey classification to chip and execute chip-scale functional test to chip can be surveyed, it can be deduced that each function items
Test coverage and SiP module functional test coverage rate, can analyze based on test data and fault model be out of order in detail
Feelings, the test data and test result quantified.
Detailed description of the invention
Fig. 1 is that the embodiment of the present invention is formed based on the SiP system structure of jtag test；
Fig. 2 is the embodiment of the present invention based on chip function test method schematic diagram in the SiP system of jtag test.
Specific embodiment
Below in conjunction with drawings and examples, the present invention is described in detail.
The jtag test method of the invention proposes a kind of SiP system and its inside chip based on jtag test.The party
Method passes through embedded core in SiP module for the characteristic that chip in SiP module is completely enclosed or is partly completely enclosed in system encapsulation
Test of the meter realization to SiP inside modules chip, boundary scan cell and jtag test port using chip are connected in piece
Realize data path.
SiP system based on jtag test includes the chip of jtag test access port, at least two obedience JTAG protocols,
It is denoted as the first JTAG chip and last bit JTAG chip, the test input TDI of jtag test access port is connected to the first JTAG
On the jtag test input terminal TDI of chip, the first JTAG chip jtag test output end TDO and last bit JTAG chip testing are inputted
TDI is held to be connected, last bit JTAG chip testing output end TDO is connected to the test output terminal TDO of jtag test access port, constitutes
The jtag test link of SiP；Other chips to be measured are if the chip for obeying JTAG protocol in SiP, according to the JTAG chip testing
Input terminal TDI connection previous stage JTAG chip testing output end TDO, the JTAG chip testing output end TDI connection rear stage
The principle of JTAG chip testing output end TDI inserts it into the jtag test link of SiP；If disobeying JTAG protocol
The boundary scan cell of itself and the chip for obeying JTAG protocol is interconnected, passes through the jtag test chain of SiP by chip or Logic Cluster
Road carries out test data transmission.The Logic Cluster is comprising one and more than one chip, for realizing the core of specific function
Piece group.
If the chip for disobeying JTAG protocol is the chip comprising DFT or BIST, by the port of DFT or BIST
It is connected with the boundary scan cell for the chip for obeying JTAG protocol.
The Logic Cluster for disobeying JTAG protocol passes through the side of input port and output port and the chip for obeying JTAG protocol
Boundary's scanning element is connected.
Fig. 1 is a certain specific embodiment of SiP system of the present invention.As shown in Figure 1, the SiP system includes that JTAG is surveyed
Trial signal end 1, jtag test access controller 2, the first chip 3, the second chip 5, chip cluster 6, third chip 7, fourth chip
8, fifth chip 9, the 6th chip 10, each chip directly pass through internet 4 and are connected.
Wherein, the first chip 3, the second chip 5, fourth chip 8, fifth chip 9 are the chip for obeying JTAG protocol；First
Chip 3, fifth chip 9 are respectively the first first place JTAG chip and last bit first place JTAG chip, constitute the jtag test chain of SIP
Road；Logic Cluster 6 includes the 7th chip 6-1 and the 8th chip 6-2, and the 7th chip 6-1 and the 8th chip 6-2 are to disobey JTAG
The chip of agreement, the 7th chip 6-1 with
The boundary scan cell of fifth chip 9 is connected；Third chip 7 is that some includes disobeying for BIST or DFT
The chip of JTAG protocol, it is connected by BIST or DFT test interface 7_1 with the boundary scan cell of fourth chip 8, thus even
On knot to JTAG link.
6th chip 10 is in SiP system include BIST or DFT structure the chip for disobeying JTAG protocol, but the chip
BIST or DFT structured testing interface 11 be drawn out to outside SiP system.It is tested by this test mouth.
Based on above-mentioned SiP system, the present invention provides a kind of chip jtag test method in SiP, this method includes as follows
Step:
(1), in plate grade jtag test software, the test model of each chip in SiP is established；The test model of the chip
Including logic port, pin mapping, design for Measurability information；
When chip is to obey the chip of JTAG protocol in SiP, the design for Measurability information refers to: jtag test port
Setting, command register and test data register, wherein test data register includes boundary scan cell；
When chip is the chip for disobeying JTAG protocol in SiP, the design for Measurability information refer to DFT or
BIST。
(2), according to chip interconnected relationship in SIP, chip testing model each in SiP is interconnected, constitutes SIP system testing mould
Type；
SIP has been established to the chip testing models for obeying JTAG protocol all in SIP system testing model, has successively been carried out
Whole property test and interconnecting test guarantee that jtag test mechanism and JTAG link function are normal in SiP module.Specific test method
Are as follows:
(2.1), to the chip testing model running integrity tests for obeying JTAG protocol all in SIP system testing model
And authentication enters step (2.2) if integrity test and authentication pass through, integrity test and identity are tested
Any one of card does not pass through, then return step (2) checks whether chip testing model is corresponding with chip information in SiP, if confirmation mould
Type is errorless, then is tested chip in SiP and breaks down, if confirmation modelling is wrong, modification model re-execute the steps (2.1)；
(2.2), the SiP interconnecting test based on jtag test is run on SIP system testing model, if interconnecting test is logical
It crosses and enters step (3), if not by guaranteeing check whether interference networks information and SiP system are right in SIP system testing model
Answer, check whether the hardware connection between test machine and tested SiP system correct, if none accidentally, be tested SiP occur therefore
Barrier re-execute the steps (2.2) after modifying model or corrigendum connection if confirmation is wrong；
It (3), is chip under test in SiP for functional test file, and configure according to the testing requirement of chip under test in SiP
Corresponding functional test model；The functional test file includes the number being written by JTAG into chip under test or Logic Cluster
According to by JTAG mouthfuls read chip under test inside data；
(4), operation function test model executes corresponding functional test, completes to survey by JTAG mouthfuls of observation test results
Examination.
For the chip for obeying JTAG protocol, the functional test model includes passing through available chip-scale JTAG hardware knot
The write-in and reading of structure realization data.
For that can survey chip comprising DFT or BIST, the functional test model includes the jtag test link by SiP
The boundary scan cell on JTAG chip that access is interconnected with DFT or BIST realizes the write-in and reading of data.
For Logic Cluster, the functional test model includes the jtag test link-access and the logic by SiP
Boundary scan cell on the JTAG chip of cluster interconnection realizes the write-in and reading of data.
As shown in Fig. 2, being the detailed process that the present invention implements test, for the 8th chip 6_2 in SiP system in Fig. 1
(SRAM), the detailed process of testing examination is as follows in fact:
(1), it collects each chip design information and establishes the test mould of each chip in SiP in plate grade jtag test software
Type；The Logic Cluster test model comprising logic port, pin mapping is established for the 8th chip 6_2；
(2), SiP module design information in Fig. 1, including module design for Measurability information, interconnection network topological structure are collected,
Corresponding SiP system test modules are established in plate grade jtag test software；
(2.1), it runs integrity test and authentication enters if integrity test and authentication pass through
Step (2.2), any one of integrity test and authentication do not pass through, then return step (2) checks chip testing model and SiP
Whether interior chip information corresponds to, if confirmation model is errorless, is tested chip in SiP and breaks down, if confirmation modelling is wrong,
Modification model re-execute the steps (2.1)；
(2.2), the SiP interconnecting test based on jtag test is run on SIP system testing model, if interconnecting test is logical
It crosses and enters step (3), if not by guaranteeing check whether interference networks information and SiP system are right in SIP system testing model
Answer, check whether the hardware connection between test machine and tested SiP system correct, if none accidentally, be tested SiP occur therefore
Barrier re-execute the steps (2.2) after modifying model or corrigendum connection if confirmation is wrong；
(3), according to the testing requirement of the 8th chip 6_2, prepare the functional test text based on March C+ algorithm for chip
Part, and the interconnected relationship of the jtag test of clear SiP and Logic Cluster and control model, completion functional test mould in test file
Type configuration；
(4), the functional test model of the 8th chip 6_2 is run, SRAM functional test is executed, is tested by JTAG mouthfuls of observations
As a result test is completed.
It is not described in detail in this specification and partly belongs to common sense well known to those skilled in the art.
Claims (10)
1. a kind of SiP system based on jtag test, the SiP includes jtag test access port, at least two obedience JTAG
The chip of agreement is denoted as the first JTAG chip and last bit JTAG chip, the test input TDI connection of jtag test access port
On the jtag test input terminal TDI of the first JTAG chip, the first JTAG chip jtag test output end TDO and last bit JTAG core
Built-in testing input terminal TDI is connected, and last bit JTAG chip testing output end TDO is connected to the test output of jtag test access port
TDO is held, the jtag test link of SiP is constituted；Other chips to be measured then pass through side if the chip for obeying JTAG protocol in SIP
The mode of boundary's scanning element interconnection inserts it into the jtag test link of SIP；If the chip for disobeying JTAG protocol or
Person's Logic Cluster then interconnects the boundary scan cell of itself and the chip for obeying JTAG protocol, by the jtag test link of SIP into
The transmission of row test data.
2. based on a kind of SiP system based on jtag test described in claim 1, it is characterised in that the Logic Cluster be comprising
One and more than one chip, for realizing the chipset of specific function.
3. a kind of SiP system based on jtag test according to claim 1, it is characterised in that: if disobeying JTAG
The chip of agreement is that the chip comprising DFT perhaps BIST then by the port of DFT or BIST and obeys the chip of JTAG protocol
Boundary scan cell is connected.
4. a kind of SiP system based on jtag test according to claim 1, it is characterised in that: disobey JTAG protocol
Logic Cluster be connected by input port and output port with the boundary scan cell of the chip of obedience JTAG protocol.
5. the jtag test method of SiP internal system chip as described in claim 1, it is characterised in that include the following steps:
(1), in plate grade jtag test software, the test model of each chip in SiP is established；The test model of the chip includes
Logic port, pin mapping, design for Measurability information；
(2), according to chip interconnected relationship in SIP, chip testing model each in SiP is interconnected, constitutes SIP system testing model；
(3), it is chip under test preparatory function test file in SiP according to the testing requirement of chip under test in SiP, and configures phase
The functional test model answered；The functional test file includes the data being written by JTAG into chip under test or Logic Cluster
With the data inside the chip under test by JTAG mouthfuls of readings；
(4), operation function test model executes corresponding functional test, completes test by JTAG mouthfuls of observation test results.
6. the jtag test method based on the SiP internal system chip described in claim 5, it is characterised in that executing step
(3) before in SIP system testing model it is all obey JTAG protocols chip testing models, successively carry out integrity test with
Interconnecting test guarantees that jtag test mechanism and JTAG link function are normal in SiP module.
7. the jtag test method based on the SiP internal system chip described in claim 5, it is characterised in that the step (1)
In, when chip is to obey the chip of JTAG protocol in SiP, the design for Measurability information refers to: the setting of jtag test port,
Command register and test data register, wherein test data register includes boundary scan cell；
When chip is the chip for disobeying JTAG protocol in SiP, the design for Measurability information refers to DFT or BIST.
8. the jtag test method based on the SiP internal system chip described in claim 5, it is characterised in that for obedience JTAG
The chip of agreement, the functional test model include the write-in and reading that data are realized by available chip-scale jtag test vector
It takes.
9. the jtag test method based on the SiP internal system chip described in claim 5, it is characterised in that for including DFT
Perhaps it includes mutual by the jtag test link-access and DFT or BIST of SiP that BIST, which can survey the chip functional test model,
Boundary scan cell on JTAG chip even realizes the write-in and reading of data.
10. the jtag test method based on the SiP internal system chip described in claim 5, it is characterised in that for Logic Cluster
For, the functional test model includes by the jtag test link-access of SiP and the JTAG chip of Logic Cluster interconnection
Boundary scan cell realize data write-in and reading.
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Application publication date: 20190402 |
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