CN106814305A - A kind of SIP module method of testing based on Embedded micro-system on piece - Google Patents
A kind of SIP module method of testing based on Embedded micro-system on piece Download PDFInfo
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- CN106814305A CN106814305A CN201611205402.0A CN201611205402A CN106814305A CN 106814305 A CN106814305 A CN 106814305A CN 201611205402 A CN201611205402 A CN 201611205402A CN 106814305 A CN106814305 A CN 106814305A
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- sip module
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/3167—Testing of combined analog and digital circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
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- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
A kind of SIP module method of testing based on Embedded micro-system on piece, first with the CPU element inside SIP module, the whole addresses to all memory cells are written and read operation, to test the correctness of memory cell；Then internal closing self-test and external auxiliary test are carried out to SIP module innernal CPU unit, to verify the correctness of CPU element；SIP module inside FPGA is tested finally by innernal CPU unit and outside FPGA.The inventive method is not on the basis of SIP module design complexities are improved, effectively SIP module function, interconnected are tested, the demand of the full Test coverage of SIP module is met to the full extent, on the basis of SIP module correctness is ensured, improves testing efficiency.
Description
Technical field
The present invention relates to a kind of SIP module method of testing, particularly a kind of SIP module based on Embedded micro-system on piece
Method of testing, belongs to IC design field..
Background technology
Requirement with user to electronic system or complete electronic set grows to even greater heights, and electronic system or complete electronic set are towards more
Function, high-performance, miniaturization, lightness, portability, high speed, low-power consumption and highly reliable direction are developed.SIP(system in
A package, system in package) technology, the circuit of various difference in functionalitys is integrated within an encapsulation, for realizing certain
Substantially complete function.Used as the effective ways of lifting monolithic processor function, SIP obtains industry and greatly pays close attention to, in recent years
To obtain very fast development.
Because the concept source of SIP is in the design of encapsulation, most research is all directed to the encapsulation process of SIP module.SIP
Module on processor architecture, and with ASIC (application specific integrated circuit, it is special integrated
Circuit) there are certain difference, traditional ATE (automatic test equipment, automatic test equipment) test mode pin
To the integrated circuit of simple function, Test coverage can be caused not when being tested for the SIP module based on Embedded micro-system on piece
Entirely, testing efficiency is low.
The content of the invention
The problem of technology solution is in the present invention：Overcome the deficiencies in the prior art, propose that one kind is declined based on insertion on piece
The SIP module method of testing of system, the method on the basis of SIP module design complexities are not improved, effectively to SIP module
Function, interconnected are tested, and the demand of the full Test coverage of SIP module is met to the full extent, are ensureing SIP module just
On the basis of true property, testing efficiency is improve.
Technical solution of the invention is：A kind of SIP module method of testing based on Embedded micro-system on piece, including
The following steps：
(1) using the CPU element inside SIP module, the whole addresses to all memory cells are written and read operation, with
Test the correctness of memory cell；
(2) internal closing self-test and external auxiliary test are carried out to SIP module innernal CPU unit, to verify CPU element
Correctness；
(3) following test is carried out to SIP module inside FPGA：
By outside FPGA to SIP module inside FPGA input clocks, and check internal FPGA's by outside FPGA
Whether lock signals lock, to test the correctness of internal FPGA working frequencies；
Using MARCH C algorithms, by CPU element, internally whole addresses of the configurable RAM of FPGA are written and read behaviour
Make, to test the correctness of configurable RAM；
Crystal oscillator provides incoming frequency, and internal FPGA carries out different degrees of frequency multiplication, internal FPGA is checked by outside PPGA
Lock signals, separately verify under low frequency mode and high frequency mode internal FPGA whether normal work, to test delay locked loop
Correctness.
The SIP module, outside FPGA and peripheral circuit are arranged on hardware test platform, the hardware test platform
For SIP module, outside FPGA and peripheral circuit provide electric signal, earth signal, clock signal, and realize board-level interconnected.
In the step (2), the implementation method of inside closing self-test is：Data are write to CPU element internal register,
According to the function to be realized of internal register, whether the data read from internal register with reference to logic judgment checking are correct；
External auxiliary test implementation method be：By peripheral circuit to CPU element input stimulus, CPU element collection or
Output signal is gathered by outside FPGA, by input stimulus, output signal and the internal logic being pre-designed, CPU is judged
Whether unit design is correct.
The method that in the step (1) whole addresses of all memory cells are written and read with operation is：
(4.1) CPU element is memory first half memory space loading code, to realize depositing memory latter half
The storage all units in space are written and read operation；
(4.2) read-write cycle is changed, operation is written and read to the memory all units of latter half memory space；
(4.3) CPU element is memory latter half memory space loading code, to realize to first half memory space
All units are written and read operation；
(4.4) read-write cycle is changed, operation is written and read to the memory all units of first half memory space.The present invention
Beneficial effect compared with prior art is：
(1) present invention proposes the SIP module test design cycle based on Embedded micro-system on piece of complete set, fills out
The blank that current SIP module tests design cycle is mended, it is incomplete to compensate for traditional ATE test mode Test coverages, test effect
The low defect of rate, meets the demand of the full Test coverage of SIP module to the full extent, is ensureing the basis of SIP module correctness
On, improve testing efficiency.
(2) present invention test design on, not only only account for SIP module test integrality, while by testing efficiency,
Within the scope of testing cost, test necessity etc. are taken into consideration, therefore on the basis of Complete test, to memory cell
Test is optimized, and code is write by the half space of memory one, realizes the read-write operation to second half memory space, greatly
The big efficiency and test validity that improve test, reduces test redundancy and the testing time.
Brief description of the drawings
Fig. 1 is hardware test platform design diagram of the present invention.
Specific embodiment
, based on design side, production link is not within invention scope for the method for the invention.The present invention uses SIP
The test method for designing of module includes two parts：Hardware test platform is designed and software test conceptual design.Two parts set
Involve larger, it is necessary to coordinate to carry out simultaneously between meter.
Fig. 1 is hardware test platform design diagram of the invention, and peripheral circuit is provided for justifying (including device under test)
System resource (electric signal, earth signal, clock signal etc.) and board-level interconnected；CPU pins are connected with inside FPGA in SIP module,
CPU and FPGA respective pins can be tested；Outside fpga chip receives SIP module part output signal, and accesses output signal
As a result, read for test system.
A kind of SIP module method of testing based on Embedded micro-system on piece, comprises the following steps：
(1) hardware test platform is designed, SIP module, outside FPGA and peripheral circuit is arranged in hardware test platform
On, hardware test platform is SIP module, outside FPGA and peripheral circuit provide electric signal, earth signal, clock signal, and in fact
Existing board-level interconnected.
(2) using the CPU element inside SIP module, the whole addresses to all memory cells are written and read operation, with
Test the correctness of memory cell；
The method that whole addresses of all memory cells are written and read with operation is as follows：
A () CPU element is memory first half memory space loading code, to latter half memory space, each is deposited
Storage unit writes 0x55 simultaneously, and reads the data of each memory cell simultaneously, to realize storing empty to memory latter half
Between all units be written and read operation；
B () changes read-write cycle, to latter half memory space each memory cell write-in 0xAA, and read each and deposit
The data of storage unit；
C () CPU element is memory latter half memory space loading code, to first half memory space, each is deposited
Storage unit writes 0x55 simultaneously, and reads the data of each memory cell, to realize to memory first half memory space institute
There is unit to be written and read operation；
D () changes the read-write cycle, write 0xAA to all units of memory first half memory space, and read each and deposit
The data of storage unit.
By writing data and reading Data Comparison, unanimously then Memory Storage Unit function is correct；It is otherwise incorrect.
(3) internal closing self-test and external auxiliary test are carried out to SIP module innernal CPU unit, to verify CPU element
Correctness；
Inside closing self-test implementation method be：Data are write to CPU element internal register, according to internal register
Whether the function to be realized, the data read from internal register with reference to logic judgment checking are correct；
Such as by taking the timer in CPU element as an example, judge whether timer enable/forbidden energy function is correct：
Timer ena-bung function judges：CPU element configuration is interrupted and carry interrupt handling routine；Enable timer simultaneously continuous
Timer count register value is read, if the numerical value is continually changing, finally produces and interrupt and enter interrupt handling routine, this
Test passes through；If phenomenon is not inconsistent with above-mentioned expected results, this test crash.
Timer forbidden energy function judges：Timer count register value is constantly read, the value will not produce change to have no
Method produces interruption, this test to pass through；If phenomenon is not inconsistent with above-mentioned expected results, this test crash.
Such as by taking the house dog in CPU element as an example, judge whether house dog tally function is correct：
Configuration house dog, does not enable house dog, and the read-write operation of multigroup different pieces of information is carried out to house dog counter register,
If data of reading back and write-in Data Matching, this test pass through；If mismatching, this test crash.
Configuration house dog, enables house dog；Timer count register is repeatedly read and write, if repeatedly reading data display counting
Register count value changes, and final generation system reset signal, this test pass through；If counter register count value is without change
Change, or cannot generation system reset signal, this test crash.
External auxiliary test implementation method be：Peripheral circuit, can be straight for CPU element to CPU element input stimulus
The functional module for reading data is connect, CPU element obtains the output signal of the corresponding function module by reading internal register；
For the functional module that CPU element can not directly read data, outside FPGA gathers output signal, and CPU element is returned
Read the output signal of outside FPGA collections；
By input stimulus, output signal and the internal logic being pre-designed, judge whether CPU element design is correct.
Such as by taking the A/D modular converters in CPU element as an example, judge whether A/D translation functions are correct：
It is fixed level (3.3V/0V) to be input into A/D modular converters by peripheral circuit, and A/D modular converters enter line level
Conversion；CPU element reads back change data, is compared with default value；If change data can connect with default value error
Scope (1%) is received, this test passes through；If change data is with default value error in acceptable outer, this test crash.
Such as by taking the GPIO modules in CPU element as an example, judge whether GPIO modules output function is correct：
By configuring outside fpga logic circuit, realize that the tunnel user IO of GPIO modules 16 is connected with FPGA pins, FPGA draws
Pin signal condition is mapped in internal register；It is output to set 16 tunnel user IO, and FPGA pins are input；By peripheral circuit
To GPIO module input stimulus, exported by user IO and combined to many kinds of output signals of outside FPGA, CPU element is by FPGA pins
Input signal is read back；By the data read back compared with initial data, if data are consistent, this test passes through；If data are not inconsistent, should
Item test crash.
(3) following test is carried out to SIP module inside FPGA：
By outside FPGA to SIP module inside FPGA input clocks, and check internal FPGA's by outside FPGA
Whether lock signals lock, and locking then illustrates that the working frequency test of internal FPGA passes through, and does not pass through otherwise.
Such as be can reach by three two frequencys multiplication to the FPGA input clock 25MHz inside SIP module by outside FPGA
200MHz, outside FPGA check whether lock signals lock, you can complete the test of the function.
Using MARCH C algorithms, by CPU element, internally whole addresses of the configurable RAM of FPGA are written and read behaviour
Make, to test the correctness of configurable RAM.
Crystal oscillator provides incoming frequency, and internal FPGA carries out different degrees of frequency multiplication, internal FPGA is checked by outside PPGA
Lock signals, separately verify under low frequency mode and high frequency mode internal FPGA whether normal work, if normally, time delay lock
Phase ring is correct.If abnormal, delay locked loop is incorrect.
Such as：DLL has two mode of operations, low frequency mode (25M-90MHz) and high frequency mode (60M-190MHz), and crystal oscillator is defeated
Enter frequency for 25MHz, by two frequencys multiplication to 50MHz, by checking Lock signal testing low frequency modes 25MHz and 50MHz
Under lower and high frequency mode 100MHz, whether internal FPGA can be with normal work, if can be with, delay locked loop be correct,
If a mode internal FPGA cisco unity malfunction, then delay locked loop design is incorrect.
Above-mentioned different test function is realized by different programming languages during test：(SPARC converges embedded assembler code
Compile) design and tested mainly for units such as SIP module inside IU, FPU and TRAP；Embedded type C language design mainly for
The connection of SIP module innernal CPU function items, SRAM, SDRAM, Flash, FPGA assembly unit, interconnector and part pin is carried out
Test；Hardware language (Verilog/VHDL) design is main to be responsible for configuration SIP module inside FPGA and onboard outside fpga chip,
The logic circuit of test software needs is configured to, is realized to SIP module part output function, the connection of part pin and part
The test of line.
Onboard fpga chip and SIP module inside FPGA are configured to pre-designed logic electricity by the present invention as needed
Road, is performed by software-hardware synergism, realizes being tested for the global function of SIP module.The method is not improving SIP module design again
On the basis of miscellaneous degree, effectively SIP module function, interconnected, external pin etc. are tested, met to the full extent
The demand of the full Test coverage of SIP module, on the basis of SIP module correctness is ensured, improves testing efficiency, is effectively ensured
The coverage rate of test, completeness and efficiency.
The content not being described in detail in description of the invention belongs to the known technology of professional and technical personnel in the field.
Claims (4)
1. a kind of SIP module method of testing based on Embedded micro-system on piece, it is characterised in that comprise the following steps：
(1) using the CPU element inside SIP module, the whole addresses to all memory cells are written and read operation, to test
The correctness of memory cell；
(2) internal closing self-test and external auxiliary test are carried out to SIP module innernal CPU unit, to verify CPU element just
True property；
(3) following test is carried out to SIP module inside FPGA：
By outside FPGA to SIP module inside FPGA input clocks, and check that the lock of internal FPGA believes by outside FPGA
Number whether lock, to test the correctness of internal FPGA working frequencies；
Using MARCH C algorithms, by CPU element, internally whole addresses of the configurable RAM of FPGA are written and read operation,
To test the correctness of configurable RAM；
Crystal oscillator provides incoming frequency, and internal FPGA carries out different degrees of frequency multiplication, checks internal FPGA's by outside PPGA
Lock signals, separately verify under low frequency mode and high frequency mode internal FPGA whether normal work, to test delay locked loop
Correctness.
2. a kind of SIP module method of testing based on Embedded micro-system on piece according to claim 1, its feature exists
In：The SIP module, outside FPGA and peripheral circuit are arranged on hardware test platform, and the hardware test platform is SIP
Module, outside FPGA and peripheral circuit provide electric signal, earth signal, clock signal, and realize board-level interconnected.
3. a kind of SIP module method of testing based on Embedded micro-system on piece according to claim 1, its feature exists
In：In the step (2), the implementation method of inside closing self-test is：Data are write to CPU element internal register, according to
Whether the function to be realized of internal register, the data read from internal register with reference to logic judgment checking are correct；
External auxiliary test implementation method be：By peripheral circuit to CPU element input stimulus, CPU element is gathered or passed through
Outside FPGA gathers output signal, by input stimulus, output signal and the internal logic being pre-designed, judges CPU element
Whether design is correct.
4. a kind of SIP module method of testing based on Embedded micro-system on piece according to claim 1, its feature exists
In：The method that in the step (1) whole addresses of all memory cells are written and read with operation is：
(4.1) CPU element is memory first half memory space loading code, to realize storing empty to memory latter half
Between all units be written and read operation；
(4.2) read-write cycle is changed, operation is written and read to the memory all units of latter half memory space；
(4.3) CPU element is memory latter half memory space loading code, all to first half memory space to realize
Unit is written and read operation；
(4.4) read-write cycle is changed, operation is written and read to the memory all units of first half memory space.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108693465A (en) * | 2018-03-30 | 2018-10-23 | 北京联想核芯科技有限公司 | A kind of test control method, circuit and system |
| CN109557459A (en) * | 2018-12-20 | 2019-04-02 | 北京时代民芯科技有限公司 | A kind of jtag test method of SiP system and its inside chip based on jtag test |
| CN109633415A (en) * | 2018-12-28 | 2019-04-16 | 泰斗微电子科技有限公司 | A kind of recognition methods and equipment of abnormal chips |
| CN111277449A (en) * | 2018-12-05 | 2020-06-12 | 中国移动通信集团广西有限公司 | Safety testing method and device for voice service equipment |
| CN111856916A (en) * | 2019-04-30 | 2020-10-30 | 联合汽车电子有限公司 | External clock diagnosis method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006061668A1 (en) * | 2004-12-07 | 2006-06-15 | Infineon Technologies Ag | Test time reduction for multi-chip modules (mcm) and for system-in-packages (sip) |
| JP2009074921A (en) * | 2007-09-20 | 2009-04-09 | Panasonic Corp | Semiconductor device |
| US20100213950A1 (en) * | 2009-02-20 | 2010-08-26 | Aiconn Technology Corporation | System in package batch test method and batch test system thereof |
| TWI376517B (en) * | 2007-04-12 | 2012-11-11 | Chroma Ate Inc | Apparatus for testing system-in-package (sip) devices |
| TWI439710B (en) * | 2009-11-18 | 2014-06-01 | Univ Nat Sun Yat Sen | Testing device for a passive component embedded in sip |
| CN103969572A (en) * | 2013-02-05 | 2014-08-06 | 东莞市泰斗微电子科技有限公司 | SIP (system in package) chip testing platform and method |
| CN105279321A (en) * | 2015-10-10 | 2016-01-27 | 北京时代民芯科技有限公司 | SIP (System In Package) module design method based on board level verification and test system |
-
2016
- 2016-12-23 CN CN201611205402.0A patent/CN106814305B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006061668A1 (en) * | 2004-12-07 | 2006-06-15 | Infineon Technologies Ag | Test time reduction for multi-chip modules (mcm) and for system-in-packages (sip) |
| TWI376517B (en) * | 2007-04-12 | 2012-11-11 | Chroma Ate Inc | Apparatus for testing system-in-package (sip) devices |
| JP2009074921A (en) * | 2007-09-20 | 2009-04-09 | Panasonic Corp | Semiconductor device |
| US20100213950A1 (en) * | 2009-02-20 | 2010-08-26 | Aiconn Technology Corporation | System in package batch test method and batch test system thereof |
| TWI439710B (en) * | 2009-11-18 | 2014-06-01 | Univ Nat Sun Yat Sen | Testing device for a passive component embedded in sip |
| CN103969572A (en) * | 2013-02-05 | 2014-08-06 | 东莞市泰斗微电子科技有限公司 | SIP (system in package) chip testing platform and method |
| CN105279321A (en) * | 2015-10-10 | 2016-01-27 | 北京时代民芯科技有限公司 | SIP (System In Package) module design method based on board level verification and test system |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108693465A (en) * | 2018-03-30 | 2018-10-23 | 北京联想核芯科技有限公司 | A kind of test control method, circuit and system |
| CN111277449A (en) * | 2018-12-05 | 2020-06-12 | 中国移动通信集团广西有限公司 | Safety testing method and device for voice service equipment |
| CN111277449B (en) * | 2018-12-05 | 2021-08-13 | 中国移动通信集团广西有限公司 | Safety testing method and device for voice service equipment |
| CN109557459A (en) * | 2018-12-20 | 2019-04-02 | 北京时代民芯科技有限公司 | A kind of jtag test method of SiP system and its inside chip based on jtag test |
| CN109633415A (en) * | 2018-12-28 | 2019-04-16 | 泰斗微电子科技有限公司 | A kind of recognition methods and equipment of abnormal chips |
| CN109633415B (en) * | 2018-12-28 | 2021-08-10 | 泰斗微电子科技有限公司 | Abnormal chip identification method and equipment |
| CN111856916A (en) * | 2019-04-30 | 2020-10-30 | 联合汽车电子有限公司 | External clock diagnosis method |
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| Publication number | Publication date |
|---|---|
| CN106814305B (en) | 2019-06-04 |
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