CN106932705A - A kind of system in package multi-chip interconnects method of testing and device - Google Patents
A kind of system in package multi-chip interconnects method of testing and device Download PDFInfo
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- CN106932705A CN106932705A CN201511020240.9A CN201511020240A CN106932705A CN 106932705 A CN106932705 A CN 106932705A CN 201511020240 A CN201511020240 A CN 201511020240A CN 106932705 A CN106932705 A CN 106932705A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2803—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] by means of functional tests, e.g. logic-circuit-simulation or algorithms therefor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
Abstract
The embodiment of the invention discloses a kind of system in package multi-chip interconnection method of testing, for system in package chip, the system in package chip at least includes the first nude film and the second nude film interconnected with first nude film, first nude film includes joint test working group jtag interface with second nude film, and first nude film forms the JTAG structures connected with second nude film；Including：The port of first nude film is set to output, the port of second nude film is set to input；First measurement vector is input into by the port of second nude film, the first output vector of the port output of first nude film is gathered；According to first output vector and the default first contrast vector, determine whether the system in package chip breaks down.Further, the embodiment of the invention also discloses a kind of system in package multi-chip interconnection test device.
Description
Technical field
The present invention relates to the chip testing technology of integrated circuit fields, more particularly to a kind of system in package multicore
Piece interconnects method of testing and device.
Background technology
With the development of integrated circuit, the encapsulation technology of chip increasingly pursue miniaturization, it is multi-functional and it is low into
This, therefore SiP (System in Package, system in package) arises at the historic moment.
The SiP is by the chip of various functions, including the integrated chip such as processor, memory in an envelope
In dress, a substantially complete function is realized.Compared with traditional individual packages, SiP can be carried to greatest extent
The integrated level of silicon chip high, and the effective area of silicon chip is utilized with minimum cost；Chip chamber can also be reduced
Electrical pathways length, so as to improve the performance of device；In addition, SiP also allows for the integrated of isomery, can be by
Analog circuit, digital circuit, RF and memory are integrated together.
But, SIP chip internals are integrated with multiple nude films, are connected with each other between each nude film.Traditional core
Chip test method only can carry out independent test when testing SiP chips to each nude film, it is ensured that
The test result of each nude film, it is impossible to test the interconnection between each nude film, have impact on SIP chips
Accuracy rate.
The content of the invention
In order to solve the above technical problems, the embodiment of the present invention is expected to provide a kind of system in package multi-chip interconnection
Method of testing and device, it is possible to increase the accuracy that system in package multi-chip is tested when interconnecting.
The technical proposal of the invention is realized in this way：
On the one hand, the embodiment of the present invention provides a kind of system in package multi-chip interconnection method of testing, for being
Irrespective of size encapsulates chip, and the system in package chip at least includes the first nude film and interconnected with first nude film
The second nude film, first nude film and second nude film include joint test working group jtag interface,
And first nude film forms the JTAG structures connected with second nude film；Including：
The port of first nude film is set to output, the port of second nude film is set to input；
First measurement vector is input into by the port of second nude film, the port of first nude film is gathered
First output vector of output；
According to first output vector and the default first contrast vector, the system in package chip is determined
Whether break down.
Optionally, it is described vectorial according to first output vector and the default first contrast, determine the system
Irrespective of size encapsulation chip whether break down including：
If first output vector is identical with the described first contrast vector, the system in package chip is determined
Do not break down；
If first output vector is different from the described first contrast vector, the system in package chip is determined
Break down.
Optionally, vector is contrasted according to first output vector and default first described, it is determined that described
After whether system in package chip breaks down, methods described also includes：
The port of first nude film is set to input, the port of second nude film is set to output；
Second measurement vector is input into by the port of first nude film, the port of second nude film is gathered
Second output vector of output；
According to second output vector and the default second contrast vector, the system in package chip is determined
Whether break down.
Optionally, it is described vectorial according to second output vector and the default second contrast, determine the system
Irrespective of size encapsulation chip whether break down including：
If second output vector is identical with the described second contrast vector, the system in package chip is determined
Do not break down；
If second output vector is different from the described second contrast vector, the system in package chip is determined
Break down.
On the other hand, the embodiment of the present invention provides a kind of system in package multi-chip interconnection test device, is used for
Test system level encapsulation chip, the system in package chip at least includes the first nude film and naked with described first
Second nude film of piece interconnection, first nude film includes joint test working group JTAG with second nude film
Interface, and first nude film forms the JTAG structures connected with second nude film；Described device includes：
Setting unit, for the port of first nude film to be set into output, the port of second nude film
It is set to input；
Collecting unit, for the first measurement vector to be input into by the port of second nude film, collection is described
First output vector of the port output of the first nude film；
Determining unit, for according to first output vector and the default first contrast vector, it is determined that described
Whether system in package chip breaks down.
Optionally, the determining unit specifically for：
If first output vector is identical with the described first contrast vector, the system in package chip is determined
Do not break down；
If first output vector is different from the described first contrast vector, the system in package chip is determined
Break down.
Optionally, the setting unit is additionally operable to for the port of first nude film to be set to input, described the
The port of two nude films is set to output；
The collecting unit is additionally operable to be input into the second measurement vector by the port of first nude film, collection
Second output vector of the port output of second nude film；
The determining unit is additionally operable to according to second output vector and the default second contrast vector, it is determined that
Whether the system in package chip breaks down.
Optionally, the determining unit specifically for：
If second output vector is identical with the described second contrast vector, the system in package chip is determined
Do not break down；
If second output vector is different from the described second contrast vector, the system in package chip is determined
Break down.
The embodiment of the present invention provides a kind of interconnection of system in package multi-chip method of testing and device, methods described
For test system level encapsulation chip, the system in package chip at least includes the first nude film and with described the
Second nude film of one nude film interconnection, first nude film includes jtag interface with second nude film, and
First nude film forms the JTAG structures connected with second nude film；The system in package multi-chip
Interconnection method of testing includes：The port of first nude film is set to output, the port of second nude film
It is set to input；First measurement vector is input into by the port of second nude film, described first is gathered naked
First output vector of the port output of piece；According to first output vector and the default first contrast vector,
Determine whether the system in package chip breaks down.Compared to prior art, by jtag test side
Method, can to system in package chip in multiple nude films between interconnection test, test out described many
Whether effectively connected between individual nude film, and then improve the system in package chip of multi-chip interconnection and tested
When test failure coverage rate, while also improving the accuracy tested system in package chip.
Brief description of the drawings
Fig. 1 is that a kind of flow of system in package multi-chip interconnection method of testing provided in an embodiment of the present invention is shown
It is intended to 1；
Fig. 2 is a kind of connection diagram of system in package chip provided in an embodiment of the present invention；
Fig. 3 is that a kind of flow of system in package multi-chip interconnection method of testing provided in an embodiment of the present invention is shown
It is intended to 2；
Fig. 4 is the structural representation that system in package multi-chip provided in an embodiment of the present invention interconnects test device.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly
Chu, it is fully described by.
The embodiment of the present invention provides a kind of system in package multi-chip interconnection method of testing, for system in package
Chip, the system in package chip at least includes the first nude film and second naked with what first nude film was interconnected
Piece, first nude film includes joint test working group jtag interface with second nude film, and described
First nude film forms the JTAG structures connected with second nude film；The system in package chip can also
Referred to as SIP chips.As shown in figure 1, the system in package multi-chip interconnection method of testing includes：
Step 101, the port of first nude film is set to output, the port of second nude film is set
It is input.
Example, as shown in Fig. 2 the system in package chip 20 can include the first nude film 201 and with
Second nude film 202；First nude film 201 includes jtag port 2011, boundary scan cell (boundary
Scan cell, B/S cell) 2012, B/S cell 2013, B/S cell 2014, B/S cell 2015, B/S cell
2016, B/S cell 2017, the jtag port 2011 include TDI (test data input) 2011a,
TDO (test data output) 2011b, TMS (test pattern selection) 2011c, TCK (test clock
Input) 2011d, TRST (test reset) 2011e；Second nude film 202 includes jtag port 2021,
Boundary scan cell B/S cell 2022, B/S cell 2023, B/S cell 2024, B/S cell 2025, B/S
Cell 2026, B/S cell 2027, the jtag port 2021 include TDI 2021a, TDO 2021b,
TMS 2021c、TCK 2021d、TRST 2021e.Understand, system in package chip 20 has 12
B/S cell, two jtag ports.
Wherein, the TDO 2011b of the jtag port 2011 that first nude film 201 includes and described second
The TDI 2011a connections of the jtag port 2021 that nude film 202 includes, what first nude film 201 included
The jtag port 2021 that the TMS 2011c of jtag port 2011 include with second nude film 202
TMS 2021c connections, the TCK 2011d of the jtag port 2011 that first nude film 201 includes and institute
State the TCK 2021d connections of the jtag port 2021 that the second nude film 202 includes, first nude film 201
Including jtag port 2011 the jtag ports that include with second nude film 202 of TRST 2011e
2021 TRST 2021e connections；B/S cell 2013, B/S cell 2014, B/S cell 2015, B/S cell
2016 connect respectively at B/S cell 2023, B/S cell 2024, B/S cell 2025, B/S cell 2026,
I.e. described first nude film 201 forms the JTAG structures connected with second nude film 202.
Assuming that B/S cell 2012 and B/S cell 2022 are respectively the first nude film 201 and the second nude film 202
The control boundary scan cell of all of the port input and output attribute, when it is low level to control boundary scan cell
The input and output attribute for representing all of the port of chip is output, when it is high level to control boundary scan cell
The input and output attribute for representing all of the port of chip is input.Specifically, can be by B/S cell 2012
Input low level, output is set to by all of the port of first nude film；By defeated to B/S cell 2022
Enter high level, all of the port of second nude film is set to input.
It should be noted that system in package chip 20 is merely illustrative in the embodiment of the present invention, it is actual
The first nude film 201 can include N number of B/S cell in, and the second nude film 202 can include M B/S cell,
The N, the M is the integer more than 6, wherein i-th B/S cell of the first nude film 201 is to jth
Individual B/S cell are connected with i-th B/S cell to j-th B/S cell of the second nude film 202, the i, j
Meet 0 ＜ i ＜ j ＜ min (N, M).
Step 102, the port input that the first measurement vector is passed through into second nude film, collection described first
First output vector of the port output of nude film.
Example, vectorial a is the port complete 1 for controlling the first nude film 201, is equivalent to the second nude film 202
Coupling part port input 1, the first test vector can be 01111x1xxxxx, will first test to
Amount is input into by the port of second nude film 202 in sequence, and it is defeated to gather the port of the first nude film 201
The first output vector for going out.Wherein, 0 to represent B/S cell be low level, and 1 to represent B/S cell be high level,
It can be high level or low level that x represents B/S cell.
Or, vectorial b is the port full 0 for controlling the first nude film of nude film 201, is equivalent to the second nude film 202
Coupling part port input 0, the first test vector can be 00000x1xxxxx.
Or, vectorial c is to control the port of the first nude film of nude film 201 for 0x55, is equivalent to the second nude film
202 coupling part port input 0x55, the first test vector can be 00101x1xxxxx.
Or, vectorial d is to control the port of the first nude film of nude film 201 for 0xAA, is equivalent to naked to second
The coupling part port input 0xAA of piece 202, the first test vector can be 01010x1xxxxx.
Step 103, according to first output vector and default first contrast vector, determine the system
Whether level encapsulation chip breaks down.
Example, the first output vector can be contrasted with the default first contrast vector, if described the
One output vector is identical with the described first contrast vector, determines that the system in package chip 20 does not break down；
If first output vector is different from the described first contrast vector, the system in package chip 20 is determined
Break down.
For example, when the first test vector is 01111x1xxxxx, default first contrast vector is
xxxxxxx1111x.First nude film 201 and the second nude film 202 are able to detect that using first test vector
Between whether there is short circuit problem.If the first output vector of the port output of the first nude film 201 and first pair
It is more identical than vector, illustrate do not exist short circuit problem between the first nude film 201 and the second nude film 202；If first
First output vector of the port output of nude film 201 is different from the first contrast vector, illustrates the first nude film 201
There is short circuit problem between the second nude film 202.
Or, for example, when the first test vector is 00000x1xxxxx, default first contrast vector is
xxxxxxx0000x.First nude film 201 and the second nude film 202 are able to detect that using first test vector
Between with the presence or absence of breaking problem.If the first output vector of the port output of the first nude film 201 and first pair
It is more identical than vector, illustrate between the first nude film 201 and the second nude film 202 in the absence of breaking problem；If first
First output vector of the port output of nude film 201 is different from the first contrast vector, illustrates the first nude film 201
There are problems that open circuit between the second nude film 202.
Or, for example, when the first test vector is 00101x1xxxxx, default first contrast vector is
xxxxxxx0101x；When the first test vector is 01010x1xxxxx, default first contrast vector is
xxxxxxx1010x.It is able to detect that the first nude film 201 is naked with second using the test vector of above-mentioned two first
Whether there is bridge joint problem between piece 202.
So, by jtag test method, can to system in package chip in multiple nude films it
Between interconnection tested, test out and whether effectively connect, and then improve multicore between the multiple nude film
Test failure coverage rate when the system in package chip of piece interconnection is tested, while also improving to system
The accuracy that level encapsulation chip is tested.
Further, as shown in figure 3, being contrasted according to first output vector and default first described
Vector, after determining whether the system in package chip 20 breaks down, methods described also includes：
Step 104, the port of first nude film is set to input, the port of second nude film is set
It is output.
Specifically, can be by the input high levels of B/S cell 2012, by all ends of first nude film
Mouth is set to input；By to the input low levels of B/S cell 2022, by all of the port of second nude film
It is set to output.
Step 105, the port input that the second measurement vector is passed through into first nude film, collection described second
Second output vector of the port output of nude film.
Example, vectorial e is the port complete 1 for controlling the first nude film 201, is equivalent to the second nude film 202
Coupling part port input 1, the second test vector can be 1xxxxx01111x, will second test to
Amount is input into by the port of first nude film 201 in sequence, and it is defeated to gather the port of the second nude film 202
The second output vector for going out.
Or, vector f is the port full 0 for controlling the first nude film 201, is equivalent to the company to the second nude film 202
Section ports input 0 is connect, the second test vector can be 1xxxxx00000x.
Or, vectorial g is to control the port of the first nude film 201 for 0x55, is equivalent to the second nude film 202
Coupling part port input 0x55, the second test vector can be 1xxxxx01010x.
Or, vectorial k is to control the port of the first nude film 201 for 0xAA, is equivalent to the second nude film 202
Coupling part port input 0xAA, the second test vector can be 1xxxxx00101x.
Step 106, according to second output vector and default second contrast vector, determine the system
Whether level encapsulation chip breaks down.
Example, the second output vector can be contrasted with the default second contrast vector, if described the
Two output vectors are identical with the described second contrast vector, determine that the system in package chip 20 does not break down；
If second output vector is different from the described second contrast vector, the system in package chip 20 is determined
Break down.
For example, when the second test vector is 1xxxxx01111x, default second contrast vector is
x1111xxxxxxx.First nude film 201 and the second nude film 202 are able to detect that using second test vector
Between whether there is short circuit problem.If the second output vector of the port output of the second nude film 202 and second pair
It is more identical than vector, illustrate do not exist short circuit problem between the first nude film 201 and the second nude film 202；If second
Second output vector of the port output of nude film 202 is different from the second contrast vector, illustrates the first nude film 201
There is short circuit problem between the second nude film 202.
Or, for example, when the second test vector is 1xxxxx00000x, default second contrast vector is
x0000xxxxxxx.First nude film 201 and the second nude film 202 are able to detect that using second test vector
Between with the presence or absence of breaking problem.
Or, for example, when the second test vector is 1xxxxx01010x, default second contrast vector is
x1010xxxxxxx；When the second test vector is 1xxxxx00101x, default second contrast vector is
x0101xxxxxxx.It is able to detect that the first nude film 201 is naked with second using the test vector of above-mentioned two second
Whether there is bridge joint problem between piece 202.
If it should be noted that the interconnection of three nude films, can be by the TDO of the second nude film and the 3rd chip
TDI is connected, and successively by the TMS of the second nude film, the TMS, TCK of TCK and TRST and the 3rd chip
With TRST connections, three series connection of nude film are thus formed, then can be completed to three using above-mentioned steps
The test of the system in package chip of individual nude film.Wherein specific annexation may be referred to shown in Fig. 2, this
Inventive embodiments will not be described here.
The embodiment of the present invention provides a kind of system in package multi-chip interconnection method of testing, for test system level
Encapsulation chip, the system in package chip at least includes the first nude film and interconnected with first nude film the
Two nude films, first nude film and second nude film include jtag interface, and first nude film with
Second nude film forms the JTAG structures of series connection；The system in package multi-chip interconnects method of testing bag
Include：The port of first nude film is set to output, the port of second nude film is set to input；Will
First measurement vector is input into by the port of second nude film, gathers the port output of first nude film
First output vector；According to first output vector and the default first contrast vector, the system is determined
Whether level encapsulation chip breaks down.Compared to prior art, by jtag test method, can be to being
The interconnection between multiple nude films in irrespective of size encapsulation chip is tested, and testing out between the multiple nude film is
No effective connection, and then improve the test failure when system in package chip of multi-chip interconnection is tested
Coverage rate, while also improving the accuracy tested system in package chip.
The embodiment of the present invention provides a kind of system in package multi-chip interconnection test device 40, for test system
Level encapsulation chip, the system in package chip at least include the first nude film and with first nude film interconnect
Second nude film, first nude film includes joint test working group jtag interface with second nude film,
And first nude film forms the JTAG structures connected with second nude film；Characterized in that, the dress
Putting 40 includes：
Setting unit 401, for the port of first nude film to be set into output, second nude film
Port is set to input.
Collecting unit 402, for the first measurement vector to be input into by the port of second nude film, collection
First output vector of the port output of first nude film.
Determining unit 403, for contrasting vector according to first output vector and default first, it is determined that
Whether the system in package chip breaks down.
So, by jtag test method, can to system in package chip in multiple nude films it
Between interconnection tested, test out and whether effectively connect, and then improve multicore between the multiple nude film
Test failure coverage rate when the system in package chip of piece interconnection is tested, while also improving to system
The accuracy that level encapsulation chip is tested.
Further, the determining unit 403 specifically for：If first output vector and described first
Contrast vector is identical, determines that the system in package chip does not break down；If first output vector with
The first contrast vector is different, determines that the system in package chip breaks down.
Further, the setting unit 401 is additionally operable to for the port of first nude film to be set to input,
The port of second nude film is set to output；The collecting unit 402 is additionally operable to the second measurement vector is logical
The port input of first nude film is crossed, the second output vector of the port output of second nude film is gathered；
The determining unit 403 is additionally operable to according to second output vector and the default second contrast vector, it is determined that
Whether the system in package chip breaks down.
Further, the determining unit 403 specifically for：If second output vector and described second
Contrast vector is identical, determines that the system in package chip does not break down；If second output vector with
The second contrast vector is different, determines that the system in package chip breaks down.
It should be noted that first, it is apparent to those skilled in the art that, it is description
Conveniently and succinctly, the device of foregoing description and the specific work process of unit, may be referred to preceding method implementation
Corresponding process in example, will not be repeated here.
Second, in actual applications, the setting unit 401, the collecting unit 402 and the determination
Unit 403 can be by the central processing unit in system in package multi-chip interconnection test device 40
(Central Processing Unit, CPU), microprocessor (Micro Processor Unit, MPU), number
Word signal processor (Digital Signal Processor, DSP) or field programmable gate array (Field
Programmable Gate Array, FPGA) etc. realize.
The embodiment of the present invention provides a kind of system in package multi-chip interconnection test device, including：Setting unit,
For the port of first nude film to be set into output, the port of second nude film is set to input；Adopt
Collection unit, for the first measurement vector to be input into by the port of second nude film, gathers described first naked
First output vector of the port output of piece；Order unit, for according to first output vector with it is default
First contrast vector, determines whether the system in package chip breaks down.Compared to prior art, lead to
Cross jtag test method, can to system in package chip in multiple nude films between interconnection test,
Test out and whether effectively connect between the multiple nude film, and then improve the system in package of multi-chip interconnection
Test failure coverage rate when chip is tested, while also improve testing system in package chip
Accuracy.The above, only presently preferred embodiments of the present invention is not intended to limit of the invention
Protection domain.
Claims (8)
1. a kind of system in package multi-chip interconnects method of testing, for system in package chip, the system
Level encapsulation chip at least includes the first nude film and the second nude film interconnected with first nude film, and described first is naked
Piece and second nude film include joint test working group jtag interface, and first nude film with it is described
Second nude film forms the JTAG structures of series connection；It is characterised in that it includes：
The port of first nude film is set to output, the port of second nude film is set to input；
First measurement vector is input into by the port of second nude film, the port of first nude film is gathered
First output vector of output；
According to first output vector and the default first contrast vector, the system in package chip is determined
Whether break down.
2. method according to claim 1, it is characterised in that described according to first output vector
With default first contrast vector, determine the system in package chip whether break down including：
If first output vector is identical with the described first contrast vector, the system in package chip is determined
Do not break down；
If first output vector is different from the described first contrast vector, the system in package chip is determined
Break down.
3. method according to claim 1 and 2, it is characterised in that described defeated according to described first
Outgoing vector and the default first contrast vector, after determining whether the system in package chip breaks down,
Methods described also includes：
The port of first nude film is set to input, the port of second nude film is set to output；
Second measurement vector is input into by the port of first nude film, the port of second nude film is gathered
Second output vector of output；
According to second output vector and the default second contrast vector, the system in package chip is determined
Whether break down.
4. method according to claim 3, it is characterised in that described according to second output vector
With default second contrast vector, determine the system in package chip whether break down including：
If second output vector is identical with the described second contrast vector, the system in package chip is determined
Do not break down；
If second output vector is different from the described second contrast vector, the system in package chip is determined
Break down.
5. a kind of system in package multi-chip interconnection test device, described for test system level encapsulation chip
System in package chip at least includes the first nude film and the second nude film interconnected with first nude film, described the
One nude film and second nude film include joint test working group jtag interface, and first nude film with
Second nude film forms the JTAG structures of series connection；Characterized in that, described device includes：
Setting unit, for the port of first nude film to be set into output, the port of second nude film
It is set to input；
Collecting unit, for the first measurement vector to be input into by the port of second nude film, collection is described
First output vector of the port output of the first nude film；
Determining unit, for according to first output vector and the default first contrast vector, it is determined that described
Whether system in package chip breaks down.
6. device according to claim 5, it is characterised in that the determining unit specifically for：
If first output vector is identical with the described first contrast vector, the system in package chip is determined
Do not break down；
If first output vector is different from the described first contrast vector, the system in package chip is determined
Break down.
7. the device according to claim 5 or 6, it is characterised in that
The setting unit is additionally operable to for the port of first nude film to be set to input, second nude film
Port is set to output；
The collecting unit is additionally operable to be input into the second measurement vector by the port of first nude film, collection
Second output vector of the port output of second nude film；
The determining unit is additionally operable to according to second output vector and the default second contrast vector, it is determined that
Whether the system in package chip breaks down.
8. device according to claim 7, it is characterised in that the determining unit specifically for：
If second output vector is identical with the described second contrast vector, the system in package chip is determined
Do not break down；
If second output vector is different from the described second contrast vector, the system in package chip is determined
Break down.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511020240.9A CN106932705A (en) | 2015-12-30 | 2015-12-30 | A kind of system in package multi-chip interconnects method of testing and device |
| PCT/CN2016/098613 WO2017113883A1 (en) | 2015-12-30 | 2016-09-09 | Method and device for testing interconnections of multiple chips in system-in-package chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511020240.9A CN106932705A (en) | 2015-12-30 | 2015-12-30 | A kind of system in package multi-chip interconnects method of testing and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106932705A true CN106932705A (en) | 2017-07-07 |
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| CN (1) | CN106932705A (en) |
| WO (1) | WO2017113883A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109557459A (en) * | 2018-12-20 | 2019-04-02 | 北京时代民芯科技有限公司 | A kind of jtag test method of SiP system and its inside chip based on jtag test |
| CN113051111A (en) * | 2021-03-05 | 2021-06-29 | 海光信息技术股份有限公司 | Multi-chip module fault identification processing method and system |
| CN113779913A (en) * | 2021-11-12 | 2021-12-10 | 浙江大学 | Verification platform structure and test method for AI multi-chip system |
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| CN103412810B (en) * | 2013-07-24 | 2016-05-04 | 中国航天科工集团第三研究院第八三五七研究所 | A kind of system in package chip and method of testing that can testing inner signal |
| CN104795334B (en) * | 2015-03-05 | 2018-01-05 | 浙江中控研究院有限公司 | IC chip of modularized encapsulation and preparation method thereof |
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| CN1108812A (en) * | 1993-11-23 | 1995-09-20 | 摩托罗拉公司 | Package for mating with a semiconductor die and method of manufacture |
| US6380555B1 (en) * | 1999-12-24 | 2002-04-30 | Micron Technology, Inc. | Bumped semiconductor component having test pads, and method and system for testing bumped semiconductor components |
| CN101884031A (en) * | 2007-12-04 | 2010-11-10 | 阿尔卡特朗讯美国公司 | Method and apparatus for testing a system-on-chip involving parallel and serial accesses |
| CN201298046Y (en) * | 2008-11-24 | 2009-08-26 | 信息产业部电子第五研究所 | A temporary encapsulation carrier for a bare chip |
| CN101799517A (en) * | 2010-04-09 | 2010-08-11 | 华为终端有限公司 | Sealing chip and sealing chip testing system |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109557459A (en) * | 2018-12-20 | 2019-04-02 | 北京时代民芯科技有限公司 | A kind of jtag test method of SiP system and its inside chip based on jtag test |
| CN113051111A (en) * | 2021-03-05 | 2021-06-29 | 海光信息技术股份有限公司 | Multi-chip module fault identification processing method and system |
| CN113051111B (en) * | 2021-03-05 | 2022-06-24 | 海光信息技术股份有限公司 | Multi-chip module fault identification processing method and system |
| CN113779913A (en) * | 2021-11-12 | 2021-12-10 | 浙江大学 | Verification platform structure and test method for AI multi-chip system |
| CN113779913B (en) * | 2021-11-12 | 2022-03-22 | 浙江大学 | Verification platform structure and test method for AI multi-chip system |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2017113883A1 (en) | 2017-07-06 |
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