CN108833204A - A kind of network-on-chip test encapsulation based on bidirectional transmission path - Google Patents
A kind of network-on-chip test encapsulation based on bidirectional transmission path Download PDFInfo
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- CN108833204A CN108833204A CN201810516677.9A CN201810516677A CN108833204A CN 108833204 A CN108833204 A CN 108833204A CN 201810516677 A CN201810516677 A CN 201810516677A CN 108833204 A CN108833204 A CN 108833204A
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- bidirectional transmission
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
- H04L43/0817—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking functioning
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/06—Management of faults, events, alarms or notifications
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- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Environmental & Geological Engineering (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
With the progress of semiconductor fabrication process, the more processor cores of multicore system on chip, reliability is with greater need for being taken seriously.The present invention is a kind of network-on-chip test encapsulation based on bidirectional transmission path.The test is encapsulated using bidirectional transmission path as test object, and bidirectional transmission path is used to replace router and link as the basic component units of network-on-chip, wherein bidirectional transmission path is defined as bi-directional data access and its close control logic circuit of Function Coupling between adjacent network-on-chip resource node.It is encapsulated based on the test, on-line testing can be carried out to network-on-chip idle route, fixed present in detection circuit and bridge type failure, Accurate Diagnosis abort situation will not have a negative impact to the application run in system while Test coverage data path and control logic circuit.The test encapsulates the measurability and observability for effectively improving the multicore system on chip based on network-on-chip, and then improves the reliability of digital display circuit.
Description
Technical field
The present invention is a kind of network-on-chip test encapsulation based on bidirectional transmission path, belongs to network-on-chip test encapsulation neck
Domain.
Background technique
With the progress of semiconductor fabrication process, in order to meet the needs of high performance parallel computation, multicore system on chip collection
At resources such as more processor cores.The following a large amount of traffic demand makes network-on-chip become multiple nucleus system one
The important interconnection communication structure of kind.Compared to the communication structure based on bus, network-on-chip possesses bigger address space, allows
Multiple data packet simultaneous transmissions, thus possess bigger bandwidth and flexibility.
The characteristic size constantly reduced makes modern integrated circuits become more quick to variables such as temperature, voltage and techniques
Sense.In the production and use process, the variation of technological parameter, particle shock, aging phenomenon etc. can introduce physics to integrated circuit
Defect.It early detects these failures and takes healing measure, circuit can be made to avoid the occurrence of the mistakes such as short circuit or open circuit,
Finally avoid occurring the failure behaviours such as data-bag lost, data packet damage even deadlock in network-on-chip.
Using before running multiple applications in the multicore system on chip based on network-on-chip, it will usually by these applications point
It is not divided into several tasks, is assigned on a series of nodes of multicore system on chip according to certain mapping ruler, each
Resource node contains a processor and its neighbor router.This process, which is referred to as, to be mapped.Mapping is a kind of multicore on piece
The scheduling means of system resource.After completing mapping, a large amount of idle link and part free time will be present in network-on-chip
Router.The link between resource node that different application occupies is idle, because they do not have traffic load；Secondly, same
It is idle for having inside the resource node that one application occupies there are section communication link；And the road that those are not occupied by application
It is also idle by the peripheral link of device.This provides possibility for the network-on-chip on-line testing of no negative effect.
Currently the test method towards network-on-chip is mainly based upon router and the test based on link.Traditional on piece
Network is made of router, link and network-on-chip interface.Test method based on router is usually required to occupy and is currently running
Resource node tested, or test and fault location are completed by the cooperation of multiple resource nodes.This test
Data path and control logic circuit in energy overlay network, but can have a negative impact to the application of operation.In addition, being based on chain
The test method on road usually only tests the link between Adjacent resource node, can not cover the control in router
Logic circuit processed, so that test is not comprehensive enough.
Summary of the invention
In order to improve the measurability and observability of network-on-chip, while not on the multiple nucleus system based on network-on-chip
The application of operation has a negative impact, and the invention proposes a kind of, and the network-on-chip based on bidirectional transmission path tests encapsulation.It should
Testing encapsulation with bidirectional transmission path replaces router and link as the basic component units of network-on-chip, and by two-way biography
Defeated path is as test object, and wherein transmission path is defined as data path and its function between adjacent network-on-chip resource node
Close control circuit can be coupled.The content of test encapsulation of the invention includes the network-on-chip knot based on bidirectional transmission path
Structure, transmission path structure, wrapper, built-in self-test platform and the test console for being tested circuit.
On-chip network structure based on bidirectional transmission path is as shown in Figure 1.In this configuration, use transmission path as
The basic component units of network-on-chip form tie point in the place that adjacent transmission path crosses.The network-on-chip of the structure with
Traditional network-on-chip function based on router is consistent.The controllers such as processor and memory pass through network-on-chip interface
(Network Interface, NI) is connect with transmission path, and transmission path is interacted in tie point and other transmission paths.
The function of different transmission path is independent from each other.In addition, in test encapsulation of the invention, in order to save the face of test circuit
Long-pending and power consumption, test suite are placed at tie point, and the transmission path by being connected to the tie point is shared.Test suite includes
Built-in self-test platform and test console.
Overall structure of the invention is as shown in Figure 2.Each transmission path contains between independent Adjacent resource node
Data path and its close control logic circuit of Function Coupling.As shown, transmission path structure can be divided into two
Link between port and port.Each port is divided into channel control unit and channel data unit, so divides and conveniently adopts
Different units is tested with different test methods, that is, uses the unit of default test data packet TCH test channel data,
Use Pseudo random test sequences TCH test channel control unit.The hardware configuration that the data path for including in transmission path is related to is logical
Link between track data unit and port, the hardware configuration that control logic circuit is related to are channel control unit.Channel data
Unit has level-one output register grade and input-buffer queue, there is finite state machine (finite state in channel control unit
Machine, FSM), route computing unit (routing calculation unit, RC), virtual channel allocation unit
(virtual-channel allocator, VA), switch divider (switch allocator, SA) and multiplexer.Its
Middle FSM is responsible for the transmission control after present port input data packet, and RC is responsible for calculating the queue of present port input-buffer at first
Into data packet route direction, VA is responsible for handling the virtual channel distribution request of the data packet from other directions of tie point,
The transmission that SA is responsible for the data packet from other directions of tie point makes can control, and multiplexer is responsible for different directions and comes in data
The channel selecting of packet.
Test wrapper in the present invention is as shown in Figure 3.(a) subgraph shows the test of channel data unit in Fig. 3
Wrapper.The wrapper is mainly made of multiplexer, is carried out half to channel data unit and is isolated, i.e., output register grade with
The input-buffer queue reservation of the transmission path other end is directly connected to, and is isolated with the control signal of local port.Work as isolation
When enabled, output register grade receives the test data packet from channel data unit built-in self-test platform, input-buffer team
The data of column will enter channel data unit built-in self-test platform as test response, while it is defeated to use fixed signal to shield
Enter the status information of buffer queue.(b) subgraph shows the test wrapper of channel control unit in Fig. 3.The wrapper is same
Sample is made of multiplexer, and channel control unit is isolated entirely, i.e. all input/output signals of channel control unit
The wrapper will be passed through.When isolation is enabled, channel control unit receives to come from channel control unit built-in self-test platform
Cycle tests and control signal, while same shielding the response requested other controls using fixed signal by the way of.With
The enabled sequence and enable signal of upper wrapper have test console to control, and test console is the pipe of entire test process
Reason person.
Channel control unit built-in self-test platform in the present invention is as shown in Figure 4.The built-in self-test platform is with tradition
STUMP (Self-Testing Using MISR and Parallel SRSG) structure based on.Platform uses linear feedback
Shift register (linear feedback shift register, LFSR) is based on default seed and generates a series of pseudorandoms surveys
Try sequence.In order to save the area of LFSR, phase shifter be used to carry out advanced phase shift to pseudo-random sequence with generate more with
Machine sequence.In the present invention, multi-strip scanning chain is inserted to tested circuit, a large amount of testing time can be saved in this way.?
The response of built-in self-test captures end, uses test response compactors (the X-tolerant test that can accommodate underrange X
Response compactor) test response is compressed, compressed value is input to multi input feature value register later
(multiple input signature register, MISR) is to generate unique characteristic value.Finally in test response analysis
Actual test response characteristic value and ideal response characteristic value are carried out in device (test response analyzer, TRA)
It compares, for judging tested circuit with the presence or absence of failure.Entire built-in self-test platform is controlled by internal built-in self-test
Device controls.
Channel data unit built-in self-test platform use state machine generates preset data packet to data by shifting function
Unit is tested.The data packet that current channel data cell built-in self-test platform generates is deposited by the output of present port
Device grade is input to the other end of input-buffer queue in tested path by data link, and by the built-in self-test of the other end
Examination platform carries out content with ideal data packet and compares, to judge present input data access with the presence or absence of failure.
Detailed description of the invention
Fig. 1 is on-chip network structure example of the invention.
Fig. 2 is overall structure of the invention.
Fig. 3 is test wrapper of the invention.
Fig. 4 is built-in self-test platform of the invention.
Fig. 5 is testing process of the invention.
Specific embodiment
Fig. 5 illustrates testing process of the invention, the process by the finite state machine of test console in the present invention shape
State transfer figure indicates.Before initializing to test suite, state machine is in idle condition.When test console receives
To the enabled triggering of test, the isolation handshake phase of test suite can be entered.Test wrapper can be to tested transmission path first
Output register grade be isolated, while etc. the path other end to be tested same operation.Later to the defeated of present port
Enter buffer to be emptied, while waiting and confirming whether the other end of component in tested path has entered same phase.Quilt
The confirmation of test path both ends finishes expression test and synchronizes success of shaking hands, and then enters the triggering stage of test.Rank is tested in triggering
Section, test console the built-in self-test platform of trigger port control and data cell can test tested path respectively,
Repeatedly test wherein will do it to cover intermittent defect to channel data unit.After all circuit tests finish, enter
In the test result analysis stage, it is eventually returned to idle state, is tested path and restores normal operation mode.
Claims (4)
1. a kind of network-on-chip based on bidirectional transmission path tests encapsulation, it is characterised in that the test of network-on-chip is double with one
It is minimum test object to transmission path, and using bidirectional transmission path as the basic component units of network-on-chip, using being directed to
Property build-in self-test method to transmission path carry out on-line testing.
2. bidirectional transmission path as described in claim 1, it is characterised in that function is mutually indepedent between transmission path, covers
The data path and its close control logic circuit of Function Coupling between network-on-chip Adjacent resource node have been covered, and has shared and puts
Set the test suite in tie point position.
3. targetedly build-in self-test method as described in claim 1, it is characterised in that draw the port of transmission path
It is divided into data cell and control unit, functional test is carried out using the method for default test data packet transmission to data cell,
Structural testing is carried out using Pseudo random test sequences to control unit.
4. test suite as described in claim 2, it is characterised in that test suite includes that data cell built-in self-test is flat
Platform, control unit built-in self-test platform and test console, and the shared use of the transmission path by being connected to identical tie point,
And test process is uniformly controlled by same test console.
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| CN201810516677.9A CN108833204A (en) | 2018-05-25 | 2018-05-25 | A kind of network-on-chip test encapsulation based on bidirectional transmission path |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110365530A (en) * | 2019-07-11 | 2019-10-22 | 电子科技大学 | A kind of test token passing network independently of network-on-chip |
| CN110597722A (en) * | 2019-09-17 | 2019-12-20 | 深圳市及响科技有限公司 | Online debugging method for online development platform |
| CN115934429A (en) * | 2022-12-01 | 2023-04-07 | 电子科技大学 | Cross-chip interconnection-oriented parallel data online calibration system and method |
-
2018
- 2018-05-25 CN CN201810516677.9A patent/CN108833204A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110365530A (en) * | 2019-07-11 | 2019-10-22 | 电子科技大学 | A kind of test token passing network independently of network-on-chip |
| CN110597722A (en) * | 2019-09-17 | 2019-12-20 | 深圳市及响科技有限公司 | Online debugging method for online development platform |
| CN115934429A (en) * | 2022-12-01 | 2023-04-07 | 电子科技大学 | Cross-chip interconnection-oriented parallel data online calibration system and method |
| CN115934429B (en) * | 2022-12-01 | 2024-04-19 | 电子科技大学 | Parallel data online calibration system and calibration method for cross-chip interconnection |
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Application publication date: 20181116 |