CN113779913A - Verification platform structure and test method for AI multi-chip system - Google Patents
Verification platform structure and test method for AI multi-chip system Download PDFInfo
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Abstract
The invention discloses a verification platform structure and a test method for an AI multi-chip system. The verification structure is mainly characterized in that the AI single system chip and the multi-system chip in the chipset are combined to provide a flexible verification structure with good flexibility and strong adaptability under different combination conditions; namely, under a single chip system or a plurality of system chips, the requirements of different test scenes can be met by adopting the same verification structure. The verification structure can be maintained mainly in multiple iterations of a project cycle, main verification structures are reserved, test cases of a single chip system can be utilized to be reused continuously in a verification environment of a multi-chip system, and therefore the expansibility of the verification structure and the reusability of the test cases are met.
Description
Technical Field
The invention belongs to the field of chip verification and test, and particularly relates to a verification platform structure and a test method for an AI multi-chip system adopting a chiplet packaging technology.
Background
The chip is used as a foundation for constructing an information society, and is used in the aspect of society in a terminal form of electronic products, so that the life quality of human beings is improved. In the last five years, artificial intelligence has increasingly appeared in new IT equipment and in many fields such as the Internet, automobiles, security and the like. In order to be able to better implement artificial intelligence techniques and related algorithms, more and more artificial intelligence AI chip developments and products have emerged in recent years.
In the AI chip development process in recent years, efforts are needed to keep up with the product cycle, and overcome the time conflict between the long cycle of chip development and the fast iteration of algorithm updating, so that an AI chip system adopting the chiplet packaging feature becomes a solution to the problem. The Chiplet packaging technology aims at finally packaging a plurality of small chips into a larger system through a new packaging technology, and under the condition of ensuring the core functions of the small chips to be stable, a series of problems of long chip development period, short product marketing time, heavy complex chip development task, high risk and the like can be solved.
The AI chip system adopting the chiplet packaging scheme integrates each AI algorithm model with standard calculation capability and modules with necessary structural characteristics such as a processor, storage, an on-chip network, an external interface and the like into one AI chip system. The standard AI system can be independently taped as bare dies (bare die), and the bare dies can be connected into a multi-AI chip system through the chiplet technology and an inter-chip interconnection interface according to the demand of a client at the later stage, and then the system can be delivered to users with different demands as a chip meeting the demand.
The traditional chip function verification platform is characterized by being built by Verilog and directionally tested, has the characteristics of high speed and high test speed for building a smaller system, but cannot adapt to the challenge under the conditions that the current system is gradually complex and the function test space is larger. Therefore, uvm (universal Verification methodology), which is a universal Verification methodology, has been widely used in the field of chip Verification as an open source standard for Verification framework based on sv (systemveilog) language for the first-turn Verification universal framework at present, and this technology also provides a technical basis for Verification of the multichip AI system based on the chiplet packaging feature of the present invention.
In the past domestic AI chip verification process, the concerned verification structure and test flow mainly aim at how to excite, monitor and compare data of corresponding algorithm in the AI chip system. According to the technical scheme, how to put the AI algorithm model into a verification environment is considered, and the functional verification of the algorithm circuit is completed in an online comparison or offline comparison mode. While the verification framework of the AI chip system with the typical characteristics and the chiplet packaging characteristics capable of repeatedly stacking AI core computing power lacks a verification framework which can simultaneously have flexible expansibility and reusable test cases.
The following problems need to be solved in order to provide a verification framework of an AI multichip system which has flexible expansibility and reusable test cases and is oriented to the chiplet packaging technology.
1. For the structural characteristics of an AI single-chip system, how to realize a verification platform which can support different test languages, different processor types and different starting modes.
2. For an AI multi-chip system which completes interconnection among multiple chips by a standard AI single-chip system, how to multiplex the verification environment, the compiling process and the testing process of the existing AI single-chip system to the AI multi-chip system.
3. How to transplant and multiplex the test cases of the AI single-chip system to the AI multi-chip system and can support the functional test requirements of a plurality of processors running in parallel.
4. How to enable processors in a plurality of AI chips to handle synchronous handshake, message printing and end of test control among the processors when the processors run in parallel.
5. How to manage the storage model in the AI single chip in the AI multi-chip by the centralized external storage model so as to obtain the stored data more quickly and complete the data comparison in the test process.
Disclosure of Invention
In order to solve the problems in the background art, the invention provides a flexible and reusable verification platform structure and a testing method for an AI multi-chip system. The verification structure can be maintained mainly in multiple iterations of a project cycle, main verification structures are reserved, a single-chip system (namely, a single-chip is taken as an independent system) trial example can be utilized, and the verification structure can be continuously multiplexed in the verification environment of a multi-chip system, so that the expansibility of the verification structure is met, and the reusability of a test case is also met. Because a multi-chip system (i.e., a system formed by interconnecting multiple dies) needs to coordinate design units in a single-chip system, parallel processing and data synchronization of each processor in the multiple-chip system are also needed. The verification structure provided by the invention can control the initiating end and the cooperation end of the test and select the type of the processor (a real processor or a virtual processor) for initiating the excitation under the condition of fast adapting to AI chip systems with different numbers, and can quickly introduce the test code into a test scene to save a large amount of simulation time.
The technical scheme adopted by the invention is as follows.
A verification platform structure for an AI multi-chip system.
The multi-chip verification platform of the AI multi-chip mainly comprises a plurality of AI single-chip verification environments and a configuration layer; the configuration layer is a variable set used for controlling the structure and the behavior of the multi-chip verification platform, the variable set comprises the number M of single chips, and the starting number N, the starting mode K, the starting category L and other variables of the processor in each single chip. Each AI single chip in the AI multi-chip system corresponds to one AI single chip verification environment; the AI single-chip verification environment is a verification platform of the AI single-chip, and each AI single-chip verification environment comprises a processor starting control module, a bus verification IP group, a register model, a storage verification IP, an interface verification IP group and a virtual processor sequence.
The processor starts the control module to load and operate the real processor of the AI single chip in a back door access mode; inputting the test file into a processor to start a control module for compiling to generate a binary file; when the test is started and after the AI single chip triggers hardware reset, the binary file is loaded to the on-chip storage of the AI single chip through the processor starting control module.
The bus verification IP group is respectively connected to a real processor, a virtual processor and an on-chip memory of the corresponding AI single chip; the bus verification IP group performs data access on the AI single chip by monitoring the real processor and the virtual processor, and can also access the AI data of the single chip by forcing the bus signal of the real processor to occur.
The register model is connected to the bus verification IP group, and register data of each hardware in the AI single chip are sent and predicted through the bus verification IP group; the register model is generated by a design information file corresponding to the AI single chip through a script (the design information file is a file with the formats of IPXACT, XML, RALF, CSV and the like).
The storage verification IP is connected with an off-chip storage interface of the AI single chip through a standard bus interface; the storage verification IP is used for simulating AI single-chip off-chip storage and supporting the loading and exporting of the storage content in the off-chip storage; the storage verification IP is used for limiting the address range of off-chip storage and giving out validity check and response of AI single-chip writing-out to off-chip storage data.
The interface verification IP group is used for being in butt joint with an external interface of the AI single chip, and a monitor of the interface verification IP group obtains data content received from the external interface of the AI single chip; and selecting a correspondingly adapted interface according to the external interface type of the AI single-chip system to verify the interface of the IP group.
The virtual processor sequence adopts one or more of a UVM test sequence, an SV test sequence formed by standard instructions and a C test sequence formed by standard instructions in the test; the virtual processor sequence verifies that the IP group generates excitation and monitoring on a virtual processor interface signal in the AI single chip through a bus: the virtual processor sequence obtains information in the register model through the register model, the obtained information is consistent with register data information in chip hardware, and then bus access is sent out by the bus verification IP group; the virtual processor sequence obtains the data stored in the storage verification IP by accessing the storage verification IP, and performs data comparison on the obtained data and expected data in the test.
In the configuration layer, the number M of single chips is used for creating a single chip verification environment, the starting number N of processors is used for controlling the number of processors participating in the test, a starting mode K of the processors is used for controlling whether the storage position of a reading instruction in the test is in on-chip storage or off-chip storage, and the starting type L of the processors is used for controlling whether a real processor or a virtual processor is adopted in the test.
The AI single chip verification environment is a verification environment established by adopting a universal UVM methodology, the top layer is a UVM test layer, a UVM test sequence is mounted on a UVM sequencer in an interface verification IP group by the UVM test layer, and the interface verification IP group is designated by the UVM test sequence to send data.
The AI single chip is an AI chip, and the AI multi-chip represents a plurality of AI chips packaged by a chip; the AI single-chip verification environments contained in the AI multi-chip verification system are independent; the real processor is a processor module which is actually present in the AI chip after the AI chip is produced; the virtual processor is a module which does not exist in the AI chip after the AI chip is produced, is only used in the chip verification stage and has the function of the processor.
The bus verification IP group is provided with a bus driver, a bus monitor and a message monitoring and processing unit; the bus monitor is used for monitoring the activity of the bus; the message monitoring and processing unit is used for acquiring the verification information of the bus from the bus monitor and analyzing and processing the verification information; each independent single chip verification environment monitors the alphabetic characters and the end characters written into the chip through a bus verification IP group, and the message monitoring and processing unit prints all the monitored characters to an information window of the simulator after receiving the end characters. The simulator is a tool for loading the AI multichip system and the verification platform thereof.
The method for exciting and monitoring the interface signal of the virtual processor in the chip by the virtual processor sequence in the verification environment comprises the following steps: excitation and monitoring both belong to the functions of a bus validation IP group.
Separately opening up a bus interface initiating terminal connected with a virtual processor in a network on chip of the AI multi-chip system; the bus driver of the bus verification IP group realizes data access to hardware in the chip by using an interface signal connecting a verification environment and the AI single chip; after the interface signal changes, the event of the signal change triggers the verification environment to modify the bus signal in the chip by adopting a signal forced assignment mode; data bus signals connected with the virtual processor inside the AI single chip are immediately transmitted to the interface signals in a signal access mode crossing the design level, so that a bus monitor of the verification environment can timely obtain bus data.
For a real processor or a virtual processor, the printf print function of C needs to be redirected to write the printed characters to a fixed location stored in the slice.
And secondly, a testing method of a verification platform structure for the AI multi-chip system.
The test method specifically comprises the following steps:
1) before the test starts, a single-chip verification environment or a multi-chip verification environment is selected according to the test parameters.
1.1) if a single-chip verification environment is adopted, executing the single-chip test case.
1.2) if a multi-chip verification environment is adopted, selecting to execute a single-chip test case or execute a multi-chip test case.
2) Inputting the test file into a processor starting control module, and configuring the multi-chip verification platform for testing by the processor starting control module according to the environment selection and the processor type selection before the testing in the step 1).
3) After the virtual processor and the real processor in each single chip execute the main program main function, the function for ending the test is called, each processor (the virtual processor or the real processor) writes the function for ending the test into the appointed position stored in the chip, after the message monitoring and processing unit in the bus verification IP group receives the special character which is sent by all the processors and ends the test, the test process is ended, and the report of the test is printed.
The executing single-chip test case specifically comprises the following steps:
1) firstly, a real processor, a virtual processor or a real processor and a virtual processor are designated to be adopted in the current test according to test parameters.
2) When a real processor is adopted to participate in testing, on-chip storage starting or off-chip storage starting is selected through testing parameters.
When the virtual processor is adopted to participate in the test, the test mode adopts one or two of a C test format and a UVM test format.
When the two processors participate in the test together, the synchronization between the real processor and the virtual processor is completed through the on-chip storage in the AI single chip.
The executing multi-chip test case specifically comprises the following steps:
1) selecting a real processor, a virtual processor or selecting a processor to sleep for each different AI single chip in the multi-chip system; i.e., testing of a multichip system may allow different AI-single chip systems to take on different processor types.
2) When a plurality of real processors participate, selecting a starting sequence to be parallel starting or serial starting of the real processors; when a single real processor participates, the real processor is independently started; when the plurality of virtual processors participate, the starting sequence of the plurality of virtual processors is parallel starting; when a single virtual processor participates, the virtual processor starts up independently.
The invention has the beneficial effects that:
the verification structure of the invention adopts the same verification framework and test method for both the single chip system and the multichip system, has stable operation, is easy for the verification structure in the project iteration process to be stable, and is convenient for selecting the test cases between the single chip system and the multichip system. On the premise of multiplexing the single-chip system verification structure and the test cases, the verification structure of the multi-chip system can be clear and easy to understand, so that the same set of verification process is maintained.
Drawings
Fig. 1 is a block diagram of a verification platform structure for an AI-oriented single chip system according to the present invention.
FIG. 2 is a schematic diagram of a verification structure hierarchy extended from a single chip system to a multichip system according to the invention.
FIG. 3 is a flow chart of processor type selection, start and stop testing in a system-on-a-chip test provided by the present invention.
FIG. 4 is a flow chart of verification platform selection and processor boot in multichip system testing provided by the invention.
Fig. 5 is a schematic diagram of data monitoring and analysis processing of message printing and end-of-test control in multichip system testing provided by the invention.
FIG. 6 is a schematic diagram of the excitation and monitoring of internal virtual processor interface signals by the virtual processor sequence provided by the present invention in a validation environment.
Detailed Description
The invention is described in further detail below with reference to the figures and the embodiments.
Fig. 1 is a block diagram of an AI-oriented single chip system verification platform. The AI single chip represents an AI chip; the AI multi-chip means a plurality of AI chips packaged by a chip. The real processor is a processor module which is really inside the AI chip after the AI chip is produced; the virtual processor is a module which does not exist in the AI chip after the AI chip is produced, is only used in the chip verification stage and has the function of the processor.
The verification platform of the AI single-chip system comprises:
1) loading and operating a processor starting control module of a real processor in a back door access mode; inputting the C test file into a processor starting control module for compiling to generate a binary file, and loading the binary file into a chip of the AI single chip through the processor starting control module for storage when the test is started and after the AI single chip system triggers hardware reset.
2) Bus authentication IP groups for stimulating (writing) and monitoring (reading) AI single chip system data activity.
2.1) selecting which specific bus verification IP is adopted according to the interface types of the real processor and the virtual processor and the network on chip.
2.2) the bus verification IP group is respectively connected to the real processor, the virtual processor and the on-chip memory, and the real processor, the virtual processor and the on-chip memory respectively select the corresponding interface types to be connected with the bus verification IP group.
2.3) the bus verification IP can be used for monitoring the data access of the real processor and the virtual processor to the AI single chip, and the bus verification IP can also be used for forcing the bus signal of the real processor to occur so as to achieve the purpose of accessing the AI single chip data.
3) Register models for routing and predicting register data within an AI-chip system.
And 3.1) selecting a design information file (in the formats of IPXACT, XML, RALF, CSV and the like) corresponding to the AI single-chip system, and generating a register model from the design information file through a script.
3.2) monitoring the buses of the real processor and the virtual processor through the bus verification IP, and predicting the data content in the register model.
4) The storage verification IP is used for simulating the storage verification IP stored outside the AI single chip.
4.1) the storage authentication IP has a bus interface adapted to the off-chip storage interface.
4.2) enabling loading and exporting of off-chip stored memory contents.
4.3) the address range of off-chip storage can be limited, and validity check and response of data written out by the AI single chip to the off-chip storage are given.
5) An interface for interfacing with the AI single chip system interface authenticates the IP group.
And 5.1) selecting a corresponding adaptive interface according to the external interface type of the AI single-chip system to verify the IP.
5.2) the verification platform structure adopts a verification environment established by a universal UVM methodology, and the topmost layer is a UVM test layer; at the UVM test layer, the UVM test sequence is mounted to a UVM sequencer within the interface verification IP.
5.3) the data to be transmitted by the IP is verified through the specified interface of the UVM test sequence, and the data content received from the AI single-chip system interface can be obtained through the monitor of the interface verification IP.
6) A virtual processor sequence consisting of a UVM test sequence and a C test sequence, the virtual processor sequence generating virtual processor stimulus through a bus validation IP group.
The test sequence for controlling the behavior of the virtual processor includes a hybrid use of a UVM sequence, a SV test pattern composed of standard instructions, a C test pattern composed of standard instructions, or any combination.
FIG. 2 is a schematic diagram of a hierarchy of authentication structures extending from a single chip system to a multichip system.
Compared with the single-chip system verification structure, the multi-chip verification structure is a verification environment of a multi-chip system verification layer made by utilizing the single-chip system verification structure after the single-chip system verification structure is developed and stabilized. The multi-chip verification platform consists of a plurality of single-chip verification environments and a configuration layer, wherein the single-chip verification environment in the multi-chip verification platform is the single-chip verification platform; the single-chip verification environments contained in the multi-chip verification system are independent from one another and respectively correspond to the AI single chips; the number of the single chip verification environments is consistent with the number of AI chips in the multi-chip system to be tested.
A configuration layer for configuring the structure and the behavior of the multi-chip verification environment is also arranged in the multi-chip verification test layer. The configuration layer is a plurality of variables for configuring the multi-chip verification environment structure, and the variables comprise the number of single chips, the starting number of processors, the mode, the category and the like. The configuration layer is a variable set used for controlling the structure and the behavior of the multi-chip verification platform, and the variable set specifically comprises variables such as the number of single chips and the starting mode (number and category) of the processor. The number M of single chips in the configuration layer is used for dynamically creating a single chip verification environment, the starting number N of the processors is used for controlling the number of the processors needing to participate in the test, the starting mode K of the processors is used for controlling the storage position (on-chip storage or off-chip storage) of a reading instruction in the test, and the starting type L of the processors is used for controlling whether the real processor or the virtual processor is adopted in the test.
FIG. 3 is a flow chart of processor type selection, start and end tests in a system-on-a-chip test. The flow chart is used for illustrating the process from preparation to start to end of the test of the single chip verification system developed for the single chip after the single chip is integrated in the early stage of the project, and the process comprises the following steps:
1) before the test code is compiled, whether a real processor or a virtual processor is adopted by the current test or both processors are adopted by the current test is selected.
2) If the test needs real processor participation, then next step needs to select which starting mode before compiling the test C code through command parameters, and the starting mode comprises on-chip storage starting or off-chip storage starting.
3) If the test requires virtual processor involvement, then the next step is to check whether the test requires C test format or UVM test, or a mixture of both test modes.
4) The two processors participate in the test together, and the synchronization between the real processor and the virtual processor needs to be completed through single-chip on-chip storage, and the end mark is obtained through data monitoring of an on-chip storage bus interface, so that the test is judged to be ended.
FIG. 4 is a flow chart of verification platform selection and processor startup in multichip system testing. The process can explain that a single-chip verification structure or a multi-chip verification structure can be dynamically selected during simulation through the same verification environment structure, and the same verification environment and test method are maintained as much as possible. The method comprises the following steps:
1) before the test is started, a single chip verification environment or a multi-chip verification environment is selected according to the number of test files and the content mark.
2) The test method for single chip verification is explained in detail in fig. 3.
3) For multi-chip verification, when a test case is selected, a single-chip test case can be multiplexed, or a new multi-chip test case can be adopted.
3.1) for the multi-chip test case, a processor needs to be selected for different AI single-chip systems, and a real processor or a virtual processor is adopted, namely, the test of the multi-chip system can allow different AI single-chip systems to adopt different processor types or select the processor of the system to be in a sleep state.
3.2) for a multi-chip test case, if there are multiple real processors, it is necessary to consider their boot order, i.e. whether they are started in parallel or in series. If it is a single real processor, it is started up independently.
3.3) for the multi-chip test case, if a plurality of virtual processors exist, the virtual processors can be started in parallel; if it is a single virtual processor, it starts up independently.
Fig. 5 is a schematic diagram of data monitoring and analysis processing for message printing and end-of-test control during multichip system testing. When the multiple processors work in parallel, the auxiliary functions required to be realized by the multi-chip verification system comprise:
for real or virtual processors, the printf print function of redirect C is required, and the printed characters can be written to fixed locations stored on-chip.
The bus driver, the bus guardian and the message listening and processing unit are all located in a bus validation IP group. The bus monitor is used for monitoring the activity of the bus, and the message monitoring and processing unit is used for acquiring the verification information of the bus from the bus monitor and analyzing and processing the verification information; the letter characters and the end characters written into the chip storage are monitored through the bus verification IP in each independent single chip verification environment, and the message monitoring and processing unit can print all the monitored characters to an information window of the simulator after receiving the end characters.
After the virtual processor and the real processor execute the main program main functions of the virtual processor and the real processor, the function for ending the test is called, the test function is written into an appointed storage position in the chip by each processor, the test process can be ended only after the message monitoring and processing unit receives special characters which are sent by all the processors and finish the test, and a report of the test is printed.
FIG. 6 is a schematic diagram of the excitation and monitoring of internal virtual processor interface signals by a virtual processor sequence in a verification environment. The specific driving and monitoring implementation mode comprises the following steps:
in order to realize data access of the virtual processor, a bus interface initiator needs to be separately opened up in the network on chip of the AI chip, and the initiator needs to be connected with an internal virtual processor, and the virtual processor can initiate port access to the opened bus.
The data access is really realized by depending on a bus driver in the verification environment, the bus driver in the verification environment accesses a design module in a chip system, and the bus driver utilizes an interface signal for connecting the verification environment and a single chip system to trigger the verification environment to modify the bus signal in the AI chip by adopting a signal forced assignment mode after the interface signal is changed.
Bus data signals connected with the virtual processor shell inside the AI chip are transmitted to interface signals in a signal access mode of crossing design levels, namely, the interface signals are transmitted at the same time, and then a monitor for verifying the environment can obtain the bus data in time.
Claims (10)
1. A verification platform structure facing an AI multi-chip system is characterized in that the multi-chip verification platform of the AI multi-chip system mainly comprises a plurality of AI single-chip verification environments and a configuration layer; the configuration layer is a variable set used for controlling the structure and the behavior of the multi-chip verification platform, and the variable set comprises the number M of single chips, the starting number N of processors in each single chip, a starting mode K and a starting type L;
each AI single chip in the AI multi-chip system corresponds to one AI single chip verification environment; the AI single-chip verification environment is a verification platform of the AI single-chip, and each AI single-chip verification environment comprises a processor starting control module, a bus verification IP group, a register model, a storage verification IP, an interface verification IP group and a virtual processor sequence.
2. The AI-oriented multichip system-oriented verification platform structure of claim 1, wherein in the configuration layer, the number of single chips M is used to create a single chip verification environment, the number of processor starts N is used to control the number of processors participating in the test, the processor start mode K is used to control whether the storage location of the read instruction in the test is on-chip storage or off-chip storage, and the processor start class L is used to control whether the test employs a real processor or a virtual processor;
the real processor is a processor module which is actually present in the AI chip after the AI chip is produced; the virtual processor is a module which does not exist in the AI chip after the production of the chip, is only used in the chip verification stage and has the function of the processor.
3. The AI-multichip-system-oriented verification platform structure of claim 1, wherein the AI single chip is an AI chip, and the AI multichip represents a plurality of AI chips packaged by a Chiplet; the AI single-chip verification environments contained in the multi-chip verification platform are independent;
the AI single chip verification environment is a verification environment established by adopting a universal UVM methodology, the top layer is a UVM test layer, a UVM test sequence is mounted on a UVM sequencer in an interface verification IP group by the UVM test layer, and the interface verification IP group is designated by the UVM test sequence to send data.
4. The AI-oriented multichip system verification platform structure of claim 1, wherein in the AI-single-chip verification environment:
the processor starts the control module to load and operate the real processor of the AI single chip in a back door access mode;
the bus verification IP group is respectively connected to a real processor, a virtual processor and an on-chip memory of the AI single chip; the bus verification IP group accesses the AI single chip data by monitoring the real processor and the virtual processor or by forcing the bus signal of the real processor to access the AI single chip data;
the register model is connected to the bus verification IP group, and register data of each hardware in the AI single chip are sent and predicted through the bus verification IP group;
the storage verification IP is connected with an off-chip storage interface of the AI single chip through a standard bus interface; the storage verification IP is used for simulating AI single-chip off-chip storage and supporting the loading and exporting of the storage content in the off-chip storage; the storage verification IP is used for limiting the address range of off-chip storage;
the interface verification IP group is used for being in butt joint with an external interface of the AI single chip, and the monitor of the interface verification IP group obtains data content received from the external interface of the AI single chip;
the virtual processor sequence adopts one or more of a UVM test sequence, an SV test sequence formed by standard instructions and a C test sequence formed by standard instructions in the test; the virtual processor sequence verifies that the IP group generates excitation and monitoring on a virtual processor interface signal in the AI single chip through a bus: the virtual processor sequence obtains the information in the register model through the register model, and then the bus verification IP group sends out bus access; the virtual processor sequence obtains the data stored in the storage verification IP by accessing the storage verification IP, and performs data comparison on the obtained data and expected data in the test.
5. The AI multi-chip system oriented verification platform structure of claim 4, wherein the bus verification IP group is provided with a bus driver, a bus guardian and a message listening and processing unit;
the bus monitor is used for monitoring the activity of the bus;
the message monitoring and processing unit is used for acquiring the verification information of the bus from the bus monitor and analyzing and processing the verification information; each independent single chip verification environment monitors the alphabetic characters and the end characters written into the chip through a bus verification IP group, and the message monitoring and processing unit prints all the monitored characters to an information window of the simulator after receiving the end characters.
6. The AI multi-chip system-oriented verification platform structure of claim 5, wherein the virtual processor sequence's excitation and monitoring of on-chip virtual processor interface signals in the verification environment is implemented by:
separately opening up a bus interface initiating terminal connected with a virtual processor in a network on chip of the AI multi-chip system; the bus driver of the bus verification IP group realizes data access to hardware in the chip by using an interface signal connecting a verification environment and the AI single chip; after the interface signal changes, the event of the signal change triggers the verification environment to modify the bus signal in the chip by adopting a signal forced assignment mode;
data bus signals connected with the virtual processor inside the AI single chip are immediately transmitted to the interface signals in a signal access mode crossing the design level, so that a bus monitor of the verification environment can timely obtain bus data.
7. The AI-oriented multichip system verification platform structure according to claim 6, wherein for a real processor or a virtual processor, the printf print function of redirection C is used to write the printed characters into fixed locations stored on the chip.
8. The AI multi-chip system oriented verification platform structure test method of any one of claims 1 to 7, wherein the test method specifically comprises:
1) before the test starts, selecting a single-chip verification environment or a multi-chip verification environment according to test parameters;
1.1) if a single-chip verification environment is adopted, executing a single-chip test case;
1.2) if a multi-chip verification environment is adopted, selecting to execute a single-chip test case or execute a multi-chip test case;
2) inputting a test file into a processor starting control module, and configuring a multi-chip verification platform for testing according to the environment selection before the test in the step 1) and the processor type selection by the processor starting control module;
3) after the virtual processor and the real processor in each single chip execute the main program main function, the function for ending the test is called, each processor writes the function for ending the test into the appointed position stored in the chip, after the message monitoring and processing unit in the bus verification IP group receives the special character which is sent by all the processors and ends the test, the test process is ended, and the report of the test is printed.
9. The AI-multichip-system-oriented test method for the verification platform structure according to claim 8, wherein the executing single-chip test case specifically comprises:
1) firstly, a real processor, a virtual processor or a real processor and a virtual processor are designated to be adopted in the current test according to test parameters;
2) when a real processor is adopted to participate in testing, on-chip storage starting or off-chip storage starting is selected through testing parameters;
when the virtual processor is adopted to participate in the test, the test mode adopts one or two of a C test format and a UVM test format;
when the two processors participate in the test together, the synchronization between the real processor and the virtual processor is completed through the on-chip storage in the AI single chip.
10. The AI multichip system-oriented test method for the verification platform structure of the claim 8, wherein the executing multichip test case specifically comprises:
1) selecting a real processor, a virtual processor or selecting a processor to sleep for each different AI single chip in the multi-chip system;
2) when a plurality of real processors participate, selecting a starting sequence to be parallel starting or serial starting of the real processors; when a single real processor participates, the real processor is independently started;
when the plurality of virtual processors participate, the starting sequence of the plurality of virtual processors is parallel starting; when a single virtual processor participates, the virtual processor starts up independently.
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