CN106788950A - The B yards of setting means based on VPX frameworks - Google Patents
The B yards of setting means based on VPX frameworks Download PDFInfo
- Publication number
- CN106788950A CN106788950A CN201611059293.6A CN201611059293A CN106788950A CN 106788950 A CN106788950 A CN 106788950A CN 201611059293 A CN201611059293 A CN 201611059293A CN 106788950 A CN106788950 A CN 106788950A
- Authority
- CN
- China
- Prior art keywords
- fpga
- pcie
- yards
- blade
- power board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
-
- G—PHYSICS
- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R40/00—Correcting the clock frequency
Abstract
The present invention relates to a kind of B based on VPX frameworks yards of setting means, technical field when belonging to accurate pair.Exist in VPX frameworks of the invention precise synchronization between power panel, power board and polylith blade mainboard, blade and pair when, be the premise for realizing system load balancing.B yards of reception, punctual circuit are realized on the FPGA of power board, and FPGA can will be input into B yards for coming in and decode date Hour Minute Second information.FPGA provides PCIE interfaces and is connected on the PCIE exchange chips of power board simultaneously, and the port is used as EP.The CPU of power board as PCIE exchange networks RC, and blade is set to NT patterns.Each NT (blade) when need to constantly, the current time being wanted to EP by the NT ports of PCIE buses, the time got be by pair when system time.Simultaneously a serial RapidIO interface, the redundancy backup united when RapidIO interchangers are as B yards have been reserved in FPGA.B yards of setting means, pair when precision can reach Microsecond grade, have good application prospect in VPX systems.
Description
Technical field
The present invention relates to technical field at accurate pair, and in particular to a kind of B based on VPX frameworks yards of setting means.
Background technology
Upgrading and replacement of the VPX frameworks as VME frameworks, once release, just obtained military affairs, Aero-Space etc. it is high-end should
With the favor in field.VPX frameworks, can support the interconnection of high speed and serial switch architecture, such as RapidIO, PCI Express
Deng disclosure satisfy that the requirement of most harsh computer module and digital signal processing module.In the VPX framework high to timing requirements
In, it is necessary to realize multiple mainboards precise synchronization and pair when.Traditional setting means, it is in the majority with device level, specific to plate level
System, method when more using network pair, but be difficult to accomplish synchronism, and pair when precision it is very low, can only achieve Millisecond.
The content of the invention
(1) technical problem to be solved
The technical problem to be solved in the present invention is：It is asynchronous when between polylith blade pair under VPX frameworks, pair when precision it is low
Problem.
(2) technical scheme
In order to solve the above-mentioned technical problem, the invention provides a kind of B based on VPX frameworks yards of setting means, including with
Lower step：
Be sent to B yards of information of generation in the way of 422 level on the power board of VPX frameworks by S1.B code generators, is handed over
Change the B on plate in FPGA yards of decoder and will be input into B yards for coming in and solve the temporal information of date Hour Minute Second, and recover a second arteries and veins
Signal is rushed, the time service register group on power board in FPGA receives the clock count that outside temperature compensating crystal oscillator sends, and by second arteries and veins
Signal is rushed to do clearing treatment；
S2., power board CPU is set to the root node RC of PCIE interchangers, blade is set to nontransparent NT patterns,
The PCIE ports of FPGA are set to end points EP patterns, and the PCIE ports are connected on the PCIE interchangers on power board；
S3. when blade is needed to constantly, the current time being wanted to the PCIE ports of FPGA by the NT ports of PCIE buses,
The time that blade is got be by pair when system time.
Preferably, in step S3, when PCIE interchangers break down, exchanged by the RapidIO of FPGA on power board
Machine realizes peerings with blade, when blade is needed to constantly, actively obtaining the current time from RapidIO interchangers.
Preferably, in step S3, the blade to the current time that the PCIE ports of FPGA are wanted be by FPGA with when unite it is right
When and the punctual time.
(3) beneficial effect
Realized on the FPGA of power board in VPX frameworks of the present invention, FPGA will be input into B yards come in when decoding the date
Every minute and second information.FPGA provides PCIE interfaces and is connected on the PCIE exchange chips of power board simultaneously, and the port is used as EP.Power board
CPU as PCIE exchange networks RC, and blade is set to NT patterns.Each NT (blade) is when needs are to constantly, passing through
The current time is wanted in the NT ports of PCIE buses to EP, the time got be by pair when system time.Simultaneously in FPGA
A serial RapidIO interface, the redundancy backup united when serial RapidIO interchangers (SRIO interchangers) are as B yards are reserved.
B yards of setting means, pair when precision can reach Microsecond grade.
Brief description of the drawings
Fig. 1 is to realize the VPX block architecture diagrams that the method for the embodiment of the present invention is based on；
Fig. 2 is to realize the PCIE exchanger principle block diagrams that the method for the embodiment of the present invention is based on；
Fig. 3 is to realize the SRIO exchanger principle block diagrams that the method for the embodiment of the present invention is based on；
Fig. 4 is B yards of setting means theory diagram of the embodiment of the present invention.
Specific embodiment
With reference to the VPX block architecture diagrams shown in Fig. 1, the PCIE exchange networks theory diagram shown in Fig. 2, shown in Fig. 3
B yards of setting means theory diagram shown in SRIO exchange networks theory diagram and Fig. 4, further retouches to the inventive method
State.
As shown in figure 1, VPX frameworks are made up of N number of blade, 2 power boards, handover module and power panels.Wherein, blade
For system provides computing resource, and load balancing is realized based on virtualization；Power board can realize Ethernet, PCIE and SRIO
Etc. function of exchange；Switch boards can realize that KVM switches；Power panel is that each module configures different power supplys, while power management core
Piece carries out intelligent management to power panel.
As shown in Fig. 2 PCIE interchangers, are realized using a power PC I-E exchanger chips of Integrated Device Technology, Inc..Thereon
Row mouth Lane0 is connected with the PCI-E x1 (Port0) of CPU, and (N+4) individual down going port supports NT moulds to its Lane1-LaneN+4 altogether
Formula enters VPX connectors, and wherein LaneN+1 connects another piece of PCIE interchanger of power board, Lane1-LaneN connection N block masters
Machine plate, LaneN+2-LaneN+3 connects other EP equipment, and LaneN+4 connects this plate FPGA.
As shown in figure 3, SRIO interchangers, are realized using a high-performance SRIO exchanger chips of Integrated Device Technology, Inc..In CPU
A SRIO bus control unit is put, has supported that SRIO interchangers are accessed in 1 x1 Mode S RIO port.Wherein 1 x4 interface
Lane0 is connected with the SRIO x1 of CPU, and the SRIO x1 of 1 Lane0 and FPGA of x4 interfaces are connected, remaining N number of x4 interface
Into VPX connectors.
As shown in figure 4, being based on above-mentioned hardware, B yards of setting means of the embodiment of the present invention are comprised the following steps：
In the way of 422 level be sent on power board B yards of information of generation by step 1.B code generators, on power board
FPGA B yards of decoder will be input into come in B yard solve the temporal information of date Hour Minute Second, and recover pulse per second (PPS) believe
Number.The time service register group of the FPGA on power board receives the clock count that outside high accuracy temperature compensating crystal oscillator sends, and by the second
Pulse signal come do clearing treatment.
Power board CPU is set to step 2. RC (RC, Root-Complex root node) of PCIE interchangers, and blade is set
NT (Non-Transparent, nontransparent) pattern is set to, the PCIE ports of FPGA are set to EP (End-Point, end points) mould
Formula, the PCIE ports are connected on the PCIE interchangers of power board.
Each blade (NT) of step 3. is when needs to PCIE ports (EP) by the NT ports of PCIE buses to that constantly, will be worked as
Preceding time (time by FPGA with when system pair when and keep time), the time that blade is got be by pair when system time.
Wherein, when PCIE interchangers break down, can be by the RapidIO interchangers of FPGA on power board and blade
Peerings are realized, when blade was needed to the time, just actively the current time is taken from RapidIO interchangers.
As can be seen that the present invention realizes B yards of decoding by the FPGA on power board, the decoder will be input into the B of coming in
Code solves date Hour Minute Second information, and recovers pps pulse per second signal.Time service register group receives high accuracy temperature compensating crystal oscillator and comes
Clock count, and clearing treatment is done by pps pulse per second signal, it is possible thereby to obtain the temporal information of 1 microsecond above resolution ratio,
And the temporal information of microsecond resolution can be realized.
FPGA can be configured to PCIE or SRIO with three high speed serdes interfaces, and interior band PCIE stones are connect with EP patterns
Enter PCIE interchangers, each blade main frame and power board CPU are PCIEhost patterns (wherein CPU is RC, and blade is NT patterns),
I.e. each blade main frame and power board CPU can be obtained by PCIE interchangers FPGA decode come temporal information.In order to
Avoiding PCIE link failures, each motherboard can periodically obtain the flag register information that FPGA is specified, to verify that FPGA is visited
Whether normal ask, determine that PCIE links are unobstructed.
For safeguards system reliability, SRIO interfaces all the way are also achieved as system backup, in FPGA (serial
RapidIO interfaces), SRIO interchangers (serial RapidIO interchangers) is accessed, each blade can also be read by SRIO interfaces
B yards of time service information in FPGA.
When precision reaches accurate pair of Microsecond grade when the present invention can realize polylith blade mainboard pair in VPX frameworks.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, on the premise of the technology of the present invention principle is not departed from, some improvement and deformation can also be made, these improve and deform
Also should be regarded as protection scope of the present invention.
Claims (3)
1. a kind of B based on VPX frameworks yards of setting means, it is characterised in that comprise the following steps：
Be sent to B yards of information of generation in the way of 422 level on the power board of VPX frameworks by S1.B code generators, power board
B yards of decoder in upper FPGA will be input into B yards for coming in and solve the temporal information of date Hour Minute Second, and recover pulse per second (PPS) letter
Number, the time service register group on power board in FPGA receives the clock count that outside temperature compensating crystal oscillator sends, and is believed by pulse per second (PPS)
Number come do clearing treatment；
S2., power board CPU is set to the root node RC of PCIE interchangers, blade is set to nontransparent NT patterns, FPGA's
PCIE ports are set to end points EP patterns, and the PCIE ports are connected on the PCIE interchangers on power board；
S3. when blade is needed to constantly, current time, blade being wanted to the PCIE ports of FPGA by the NT ports of PCIE buses
The time got be by pair when system time.
2. the method for claim 1, it is characterised in that in step S3, when PCIE interchangers break down, by handing over
The RapidIO interchangers and blade for changing FPGA on plate realize peerings, when blade is needed to constantly, actively being handed over from RapidIO
Change planes and obtain the current time.
3. method as claimed in claim 1 or 2, it is characterised in that in step S3, the blade will to the PCIE ports of FPGA
Current time be by FPGA with when system pair when and keep time time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611059293.6A CN106788950A (en) | 2016-11-28 | 2016-11-28 | The B yards of setting means based on VPX frameworks |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611059293.6A CN106788950A (en) | 2016-11-28 | 2016-11-28 | The B yards of setting means based on VPX frameworks |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106788950A true CN106788950A (en) | 2017-05-31 |
Family
ID=58911556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611059293.6A Pending CN106788950A (en) | 2016-11-28 | 2016-11-28 | The B yards of setting means based on VPX frameworks |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106788950A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108306722A (en) * | 2017-12-12 | 2018-07-20 | 天津津航计算技术研究所 | A kind of improved B code setting means based on VPX frameworks |
| CN109614357A (en) * | 2018-12-06 | 2019-04-12 | 天津津航计算技术研究所 | It unites when a kind of VPX of high bandwidth multibus module |
| CN109710565A (en) * | 2018-12-03 | 2019-05-03 | 天津津航计算技术研究所 | The logic united when VPX cabinet B code realizes system and method |
| CN110851337A (en) * | 2019-11-18 | 2020-02-28 | 天津津航计算技术研究所 | High-bandwidth multi-channel multi-DSP computing blade device suitable for VPX architecture |
| CN111221771A (en) * | 2019-11-18 | 2020-06-02 | 天津津航计算技术研究所 | GPU (graphics processing Unit) blade device suitable for VPX (virtual private network X) architecture |
| CN112231267A (en) * | 2020-10-16 | 2021-01-15 | 天津津航计算技术研究所 | B code timing device of homemade VPX framework |
| CN113805643A (en) * | 2021-10-18 | 2021-12-17 | 天津津航计算技术研究所 | Nationwide multi-bus multi-redundancy B code time synchronization device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101751230A (en) * | 2009-12-29 | 2010-06-23 | 成都市华为赛门铁克科技有限公司 | Equipment and method for calibrating time stamp of I/O (input/output) data |
| CN102323744A (en) * | 2011-08-12 | 2012-01-18 | 北京电子工程总体研究所 | High-precision and independent time-keeping type ground time service instrument used on ground in complex environment |
| CN204303042U (en) * | 2014-12-30 | 2015-04-29 | 西安奇维科技股份有限公司 | A kind of high-speed data recording instrument based on PowerPC and FPGA framework |
| CN104865824A (en) * | 2015-04-30 | 2015-08-26 | 苏州科技学院 | Beidou B-code timing synchronization device based on PCI-E bus |
| CN205050133U (en) * | 2015-07-27 | 2016-02-24 | 北京国基科技股份有限公司 | Embedded time system that unites in system |
| US9318212B2 (en) * | 2013-02-13 | 2016-04-19 | Kabushiki Kaisha Toshiba | Nonvolatile memory device changing a period of an internal clock |
-
2016
- 2016-11-28 CN CN201611059293.6A patent/CN106788950A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101751230A (en) * | 2009-12-29 | 2010-06-23 | 成都市华为赛门铁克科技有限公司 | Equipment and method for calibrating time stamp of I/O (input/output) data |
| CN102323744A (en) * | 2011-08-12 | 2012-01-18 | 北京电子工程总体研究所 | High-precision and independent time-keeping type ground time service instrument used on ground in complex environment |
| US9318212B2 (en) * | 2013-02-13 | 2016-04-19 | Kabushiki Kaisha Toshiba | Nonvolatile memory device changing a period of an internal clock |
| CN204303042U (en) * | 2014-12-30 | 2015-04-29 | 西安奇维科技股份有限公司 | A kind of high-speed data recording instrument based on PowerPC and FPGA framework |
| CN104865824A (en) * | 2015-04-30 | 2015-08-26 | 苏州科技学院 | Beidou B-code timing synchronization device based on PCI-E bus |
| CN205050133U (en) * | 2015-07-27 | 2016-02-24 | 北京国基科技股份有限公司 | Embedded time system that unites in system |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108306722A (en) * | 2017-12-12 | 2018-07-20 | 天津津航计算技术研究所 | A kind of improved B code setting means based on VPX frameworks |
| CN109710565A (en) * | 2018-12-03 | 2019-05-03 | 天津津航计算技术研究所 | The logic united when VPX cabinet B code realizes system and method |
| CN109710565B (en) * | 2018-12-03 | 2023-07-14 | 天津津航计算技术研究所 | Logic realization system and method for VPX chassis B code time system |
| CN109614357A (en) * | 2018-12-06 | 2019-04-12 | 天津津航计算技术研究所 | It unites when a kind of VPX of high bandwidth multibus module |
| CN110851337A (en) * | 2019-11-18 | 2020-02-28 | 天津津航计算技术研究所 | High-bandwidth multi-channel multi-DSP computing blade device suitable for VPX architecture |
| CN111221771A (en) * | 2019-11-18 | 2020-06-02 | 天津津航计算技术研究所 | GPU (graphics processing Unit) blade device suitable for VPX (virtual private network X) architecture |
| CN111221771B (en) * | 2019-11-18 | 2023-04-28 | 天津津航计算技术研究所 | GPU blade device suitable for VPX framework |
| CN110851337B (en) * | 2019-11-18 | 2023-08-08 | 天津津航计算技术研究所 | High-bandwidth multichannel multi-DSP (digital Signal processor) computing blade device suitable for VPX (virtual private X) architecture |
| CN112231267A (en) * | 2020-10-16 | 2021-01-15 | 天津津航计算技术研究所 | B code timing device of homemade VPX framework |
| CN113805643A (en) * | 2021-10-18 | 2021-12-17 | 天津津航计算技术研究所 | Nationwide multi-bus multi-redundancy B code time synchronization device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106788950A (en) | The B yards of setting means based on VPX frameworks | |
| CN106708169A (en) | Multicomputer system time synchronization method based on VPX framework and device | |
| CN108306722A (en) | A kind of improved B code setting means based on VPX frameworks | |
| CN109614357A (en) | It unites when a kind of VPX of high bandwidth multibus module | |
| KR101109030B1 (en) | Clock supply method and information processing apparatus | |
| CN106713184A (en) | Dual-redundancy data exchange device | |
| US20240045821A1 (en) | Multi-path server and multi-path server signal interconnection system | |
| CN104079460B (en) | Communication between plates component based on POWERLINK technologies | |
| CN105119703B (en) | Multi-standard clock MicroTCA system and clock management method | |
| CN101123491A (en) | An implementation device and method for time synchronization of advanced telecom computer architecture | |
| CN109976489A (en) | Automatically reset realization method and system under a kind of iic bus abnormal conditions | |
| CN113885394A (en) | Airborne data comprehensive acquisition and recording system and method | |
| CN103235769A (en) | High speed 1553 bus protocol processor | |
| US7952992B1 (en) | Procedure and mechanisms for control and bearer redundancy of TDM-based service provider connections | |
| CN101296063B (en) | Main/standby switching device, method and single plate | |
| CN111145529B (en) | Communication method of cascade power unit of high-voltage frequency converter | |
| CN104360639A (en) | VME user-defined bus-based real-time synchronous grating ruler data reading method for multiple motion control cards | |
| CN202617157U (en) | PCI express (PCIE) switched circuit | |
| CN104598420A (en) | SoC chip architecture of 1394 bus | |
| CN211015495U (en) | Bus architecture and case type acquisition instrument with same | |
| CN106814596A (en) | A kind of Hardware-in-the-Loop Simulation in Launch Vehicle tests ground installation method for synchronizing time | |
| CN207232857U (en) | A kind of transformer substation communication server system of double net dual-cpu communication functions | |
| CN111145530B (en) | Communication method of high-voltage frequency converter power unit | |
| CN111212000A (en) | Exchange backplate based on PXIe bus | |
| CN108664433A (en) | A kind of low time delay shake high speed signal switching technology and the backboard using the Technology design |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20170531 |
|
| WD01 | Invention patent application deemed withdrawn after publication |