CN113885394A - Airborne data comprehensive acquisition and recording system and method - Google Patents

Abstract

The invention relates to an airborne data comprehensive acquisition and recording system and a method thereof, which comprises a comprehensive data acquisition device, a quick access recording card and a protection recorder which are positioned on an airborne part; the comprehensive data acquisition unit is electrically connected with the protection recorder through the Ethernet; the comprehensive data acquisition unit is electrically connected with the onboard power supply; the input end of the on-board monitoring device is used for collecting on-board signals on an airborne part, and the on-board signals comprise switching signals, frequency signals, voltage signals, vibration signals, an ARINC429 bus, an RS422 bus, an MIL-STD-155B bus, an AFDX bus, audio signals and video signals; the data of the acquired onboard signals are packed according to the IRIG-106 standard and then sent to a quick access recording card and a protection recorder for recording; the invention has reasonable design, compact structure and convenient use.

Description

Airborne data comprehensive acquisition and recording system and method

Technical Field

The invention relates to an airborne data comprehensive acquisition and recording system and method.

Background

The traditional airplane mostly takes a mechanical airplane control and simulation operation system as a main part, and is gradually replaced by full-electronic transmission and control equipment along with the rapid development of the technology, and in the past, when a pilot, particularly a pilot test plane, operates the airplane, the pilot is often required to have abundant personal experience to collect and record various complex data, and the workload is large, so that the accurate collection and analysis of the data are not facilitated.

The integrated data acquisition and recording system mainly acquires signals such as a switching signal, a frequency signal, a voltage signal, a vibration signal, an ARINC429 bus, an RS422 bus, an MIL-STD-155B bus, an AFDX bus, an audio signal, a video signal and the like on the machine and records data according to the standard of IRIG-106.

Cn201120265010.x an onboard computer data acquisition and recording system provides a set of system, which comprises a computer acquisition and recording device, a track guidance display and an onboard power supply module, wherein the computer acquisition and recording device, the track guidance display and the onboard power supply module are connected to a bus; the computer acquisition recorder comprises a first embedded processor module, an analog parameter acquisition module and a serial data acquisition module which are respectively connected with the bus, and the first embedded processor module is also connected with a detachable reinforced electronic disk; the track guiding display comprises a digital I/O parameter acquisition module and a second embedded processor module which are connected with a bus respectively, the digital I/O parameter acquisition module is connected with a keyboard control interface, and the second embedded processor module is connected with an EL display screen. However, the structure is complex, the test precision is low, and effective recording cannot be realized.

Disclosure of Invention

The invention aims to solve the technical problem of providing an airborne data comprehensive acquisition and recording system and method.

In order to solve the problems, the technical scheme adopted by the invention is as follows:

an airborne data comprehensive acquisition and recording system comprises a comprehensive data acquisition unit, a quick access recording card and a protection recorder which are positioned on an airborne part; the comprehensive data acquisition unit is electrically connected with the protection recorder through the Ethernet;

the comprehensive data acquisition unit is electrically connected with the onboard power supply; the input end of the on-board monitoring device is used for collecting on-board signals on an airborne part, and the on-board signals comprise switching signals, frequency signals, voltage signals, vibration signals, an ARINC429 bus, an RS422 bus, an MIL-STD-155B bus, an AFDX bus, audio signals and video signals; the data of the acquired onboard signals are packed according to the IRIG-106 standard and then sent to a quick access recording card and a protection recorder for recording;

the quick access recording card adopts the SATA bus to be cross-linked with the comprehensive data acquisition unit to complete the recording of all the acquired data;

the protection recorder adopts a gigabit Ethernet bus to be crosslinked with the comprehensive data acquisition unit to complete the recording of important data; the vital data includes data used for incident analysis;

an unloading calibrator and a flight parameter data ground comprehensive analysis processing system are arranged on the ground;

the unloading checker is respectively linked with the protection recorder and the comprehensive data collector through Ethernet; the output end of the unloading checker is electrically connected with the input end of the ground comprehensive analysis and processing system of the flight parameter data so as to import the data.

As a further improvement of the above technical solution:

the chassis structure of the integrated data acquisition unit adopts a non-backplane form, and the communication and power supply among the modules are interconnected through an inter-board connector;

the comprehensive data acquisition device comprises a power supply module, a main control module adopting an integrated cache recording card, a voltage signal acquisition module I, a voltage signal acquisition module II, a switch signal acquisition module, a vibration signal acquisition module, a bus acquisition module and an audio and video acquisition module;

the master control module, the voltage signal acquisition module I, the voltage signal acquisition module II, the switch signal acquisition module, the vibration signal acquisition module, the bus acquisition module and the audio and video acquisition module are respectively provided with

A BIT test capability module; the BIT test capability module has three self-checking modes, including PBIT power-on self-checking, CBIT periodic self-checking and IBIT maintenance self-checking;

the fault logging module is used for providing a fault logging means through a LAN bus, fault information is stored in the nonvolatile memory, and each piece of fault recording information must contain timestamp information;

and each module of the time synchronization module realizes time synchronization by using IRIG-B codes, time marks are marked by using hardware, and the time synchronization precision is 100 ns.

In the comprehensive data acquisition unit, a power supply module comprises a Power Control Unit (PCU) power supply conversion unit, combines and inputs a normal power supply and an emergency power supply, and converts a direct current 28V input voltage into a direct current 24Vd bottom plate voltage;

the voltage range of the normal power supply is 22V-30V; the voltage range of the emergency power supply is 18V-30V;

a PSA power supply having an output voltage monitoring and switch control module cross-linked with the NIU module; the output voltage monitoring and switch control module is responsible for switching on, switching off and monitoring different power supply outputs of other modules in the rack;

the NIU module is used for managing a power supply in the rack and detecting power supply distribution faults through the CPU module and the PHY module which are crosslinked through an internal MII signal; the CPU module controls the PSA based on information received from the system to provide power to the desired module; the PHY module communicates with the system over a LAN channel.

The PCU power conversion unit comprises an energy storage capacitor, a holding module, a filtering module and a DC-DC module I; the input end of the filtering module is connected with an external power supply, and the input end of the holding module is respectively connected with the energy storage capacitor and the output end of the filtering module; the output end of the holding module is connected with the input end of the DC-DC module I; the DC-DC module I outputs +24V voltage;

the system comprises a voltage signal acquisition module I for inputting 32-path voltage signals, a voltage signal acquisition module II for inputting 32-path voltage signals, a switch signal acquisition module for inputting switch signals and frequency signals, a vibration signal acquisition module for inputting vibration signals, a bus acquisition module for inputting ARINC429, RS422, MIL-STD-1553B and/or AFDX signals, and an audio and video acquisition module for inputting audio signals and video signals, wherein the audio and video acquisition module completes the exchange of acquired data through a PCIe bus and a main control module and completes the exchange of maintenance information through a LAN bus and the main control module, and the maintenance information comprises self-checking information, software upgrading, log information and parameter monitoring;

the main control module is internally integrated with an FPGA integrated circuit, an LAN switch chip, a PCIe switch chip, a CPU, a synchronous signal module and an RTC chip; the PCIe switch chip is respectively exchanged with the voltage signal acquisition module I, the voltage signal acquisition module II, the switch signal acquisition module, the vibration signal acquisition module, the bus acquisition module and the audio and video acquisition module through a PCIe bus and an input end of the synchronous signal module through an IRIG-B channel;

the LAN switch chip cross-links the maintenance information with the unloading checker through LAN; maintaining log information and storing the log information in an SATA hard disk integrated on a main control module; the LAN switch chip is crosslinked with the CPU through LAN;

the PCIe switch chip and the CPU are switched through a PCIe bus; the CPU is electrically connected with the quick access recording card through the SATA channel;

the synchronous signal module receives an RTC time service signal of the RTC chip;

in a physical link of a PCIe bus, the PCIe link uses an end-to-end data transmission mode, and a sending end and a receiving end both contain TX sending logic and RX receiving logic; the PCIe link comprises a plurality of data paths Lane; in the data path Lane, a transmitting link of a transmitting end and a transmitting link of a receiving end are included;

a TX component of the transmitting end is connected with an RX component of the receiving end using a set of differential signals;

the RX component of the transmitting end and the TX component of the receiving end are connected by another set of differential signals, and this link is also called a receiving link of the transmitting end, i.e. a transmitting link of the receiving end;

the PCIe link carries out data transmission through a differential signal, the differential signal comprises a D + signal and a D-signal, and the signal receiving end judges whether the signal sent by the sending end is a logic 1 or a logic 0 by comparing the difference value of the D + signal and the D-signal;

the voltage signal acquisition module is provided with a voltage signal conditioning module, an AD sampling module, a self-checking circuit, an FPGA integrated circuit I, CPU1 and a port PHYI;

the input end of the voltage signal conditioning module inputs 32 paths of voltage signals; the input end of the AD sampling module is electrically connected with the output end of the voltage signal conditioning module, the output end of the AD sampling module is electrically connected with the input end of an FPGA integrated circuit I, and the FPGA integrated circuit I is electrically connected with the CPU 1; the self-checking circuit is respectively and electrically connected with the voltage signal conditioning module, the AD sampling module, the FPGA integrated circuit I and the CPU 1;

the FPGA integrated circuit I receives the IRIG-B synchronous signal and is in cross-linking with a PCIe bus;

CPU1 cross-links the LAN signal through port PHYI;

the switching signal acquisition module comprises a switching signal conditioning module, a frequency signal conditioning module, a switching signal self-checking circuit, a switching signal CPU, a switching signal port and a switching signal integrated circuit;

the input end of the switching signal conditioning module receives 96 switching signal inputs, and the output end of the switching signal conditioning module is electrically connected with the switching signal integrated circuit;

and the frequency signal conditioning module receives 6 paths of frequency signal input, is crosslinked with the switching signal conditioning module, and has an output end electrically connected with the switching signal integrated circuit.

The switching signal integrated circuit receives an IRIG-B synchronous signal and is in cross-linking with the PCle bus;

the switching signal CPU is crosslinked with the switching signal integrated circuit and is connected with the LAN port through a switching signal port;

the switching signal self-checking circuit comprises a switching signal self-checking circuit, a self-checking switching signal conditioning module, a frequency signal conditioning module and a switching signal CPU;

the system comprises a vibration data acquisition module, a vibration signal conditioning module for receiving vibration signals, an azimuth signal conditioning module for receiving azimuth signals, a vibration data AD sampling module, a vibration data self-checking circuit, a vibration circuit FPGA module, an oscillation data CPU and a vibration data PHY port;

the vibration signal conditioning module is connected with the input end of the vibration circuit FPGA module through a vibration data AD sampling module, and the output end of the azimuth angle signal conditioning module is connected with the input end of the vibration circuit FPGA module;

the oscillation data CPU is crosslinked with the oscillation circuit FPGA module and is connected with the LAN channel through an oscillation data PHY port; the FPGA module of the vibration circuit receives and receives IRIG-B synchronous signals and cross-links a PCle bus; the vibration data self-checking circuit is used for self-checking the vibration signal conditioning module, the azimuth angle signal conditioning module, the vibration data AD sampling module and the vibration data CPU.

The bus acquisition module comprises an RS422 interface conditioning module, an ARINC429 interface conditioning module, an MIL-STD-1553B interface conditioning module, an AFDX bus interface conditioning module, a bus FPGA module, a bus self-checking circuit, a bus CPU and a bus PHY;

the input end of the RS422 interface conditioning module is connected with an RS422 bus, the ARINC429 interface conditioning module is connected with an ARINC429 bus, the MIL-STD-1553B interface conditioning module is connected with an MIL-STD-1553B bus, and the AFDX bus interface conditioning module is connected with an AFDX bus;

the output ends of the RS422 interface conditioning module, the ARINC429 interface conditioning module, the MIL-STD-1553B interface conditioning module and the AFDX bus interface conditioning module are connected with the input end of the bus FPGA module;

the bus FPGA module is connected with an IRIG-B synchronous signal, a PCIe bus and a bus CPU; the bus CPU is connected with the LAN channel through a bus PHY;

the bus self-checking circuit comprises a RS422 interface conditioning module, an ARINC429 interface conditioning module, an MIL-STD-1553B interface conditioning module, an AFDX bus interface conditioning module and a bus CPU;

the audio and video data acquisition module comprises a video signal conditioning module for receiving a video signal, an audio signal conditioning module for receiving an audio signal, a video acquisition module, an audio and video AD sampling module, an audio and video self-checking circuit, an audio and video FPGA module, an audio and video self-checking circuit, an audio and video CPU and an audio and video PHY;

the audio and video FPGA module receives the output signal of the video signal conditioning module through the video acquisition module; receiving an audio signal conditioning module through an audio and video AD sampling module; the audio and video FPGA module is connected with an IRIG-B synchronous signal, a PCIe bus and a bus CPU; the audio/video CPU is connected with the LAN channel through the audio/video PHY;

the audio and video self-detection circuit comprises a video signal conditioning module, an audio signal conditioning module and an audio and video CPU.

The quick access recording card is integrated on the main control module and adopts the SATA bus to communicate with the main control module; the quick access recording card uses a reinforced FLASH hard disk and is connected with the outside through a switching board with a DMU connector;

the protection recorder adopts a fixed memory, adopts a cyclic recording mode and is provided with a gigabit Ethernet interface;

the quick access recording card is integrated on the main control module and adopts the SATA bus to communicate with the main control module; the quick access recording card uses a reinforced FLASH hard disk and is connected with the outside through a switching board with a DMU connector;

the protection recorder adopts a fixed memory, adopts a cyclic recording mode and is provided with a gigabit Ethernet interface.

The collector comprises a plurality of box bodies; the box body is provided with a through hole and is detachably connected; the method comprises one of the following schemes;

according to the first scheme, a connecting rod penetrates through a through hole, a gasket is sleeved on the connecting rod, and the gasket is arranged between box bodies; a nut and a washer are arranged at the end part of the connecting rod;

according to the second scheme, transverse clamping grooves are respectively and transversely formed in the upper portion and the lower portion of the outer side walls of the two sides of the box body, a transverse connecting block is arranged between the side walls of the adjacent box bodies, the two sides of each transverse connecting block are respectively inserted into the corresponding transverse clamping grooves, and clamping groove holes are formed in the transverse clamping grooves and are connected with positioning bolts through threads; the lower end of the positioning bolt is connected to the transverse connecting block;

according to the third scheme, a connecting rod penetrates through the through hole, a gasket is sleeved on the connecting rod, and the gasket is arranged between the box bodies; a nut and a washer are arranged at the end part of the connecting rod; the upper part and the lower part of the outer side walls of two sides of the box body are respectively transversely provided with a transverse clamping groove, a transverse connecting block is arranged between the side walls of the adjacent box bodies, two sides of the transverse connecting block are respectively inserted into the corresponding transverse clamping grooves, and the transverse clamping grooves are provided with clamping groove holes which are connected with positioning bolts through threads; the lower end of the positioning bolt is connected to the transverse connecting block;

according to the fourth scheme, transverse clamping grooves are respectively and transversely formed in the upper portion and the lower portion of the outer side walls of the two sides of the box body, a transverse connecting block is arranged between the side walls of the adjacent box bodies, the two sides of each transverse connecting block are respectively inserted into the corresponding transverse clamping grooves, and clamping groove holes are formed in the transverse clamping grooves and are connected with positioning bolts through threads; the positioning bolt lower extreme is connected on transverse connection piece, still reserve a plurality of two-sided horizontal draw-in grooves of substitution, and it is as wide as the box body, after certain collector is taken off, installs this position through two-sided horizontal draw-in groove to guarantee that whole module's position is unchangeable.

An airborne data comprehensive acquisition and recording method, which is characterized in that by means of an airborne data comprehensive acquisition and recording system,

firstly, sending an onboard signal to a comprehensive data acquisition unit; then, the collector stores the signal in the quick-access recording card and cross-links with the unloading checker; and thirdly, importing the data into a ground comprehensive analysis processing system of the flight parameter data by the unloading calibrator.

As a further improvement of the above technical solution:

during the work of the comprehensive data collector, the main control module executes the PCIe switch function to exchange data, performs the LAN switch function, performs the maintenance function, realizes the time synchronization function module, generates IRIG-B code output through RTC or GPS time service, realizes the hardware time marking function through FPGA, exchanges data with the main control module through a PCIe bus, and realizes module self-checking and software upgrading through LAN;

the voltage signal acquisition module executes voltage signal acquisition, the input range of the voltage signal is set through software, the hardware time marking function is realized through an FPGA (field programmable gate array), data exchange with the main control module is realized through a PCIe (peripheral component interconnect express) bus, and module self-checking and software upgrading are realized through an LAN (local area network);

the switching signal acquisition module executes the following steps; collecting a switch signal, collecting a frequency signal, performing a hardware time marking function through an FPGA, realizing data exchange with a main control module through a PCIe bus, and realizing module self-checking and software upgrading through an LAN;

the vibration data acquisition module executes the following steps; acquiring an azimuth angle signal, acquiring a vibration signal, realizing a hardware time marking function through an FPGA, realizing data exchange with a main control module through a PCIe bus, and realizing module self-checking and software online upgrading through an LAN;

the bus acquisition module executes the following steps of acquiring an RS422 bus, acquiring 8 paths of ARINC429 buses, acquiring a dual-redundancy MIL-STD-1553B bus, acquiring a dual-redundancy AFDX bus, realizing a hardware time marking function through an FPGA (field programmable gate array), realizing data exchange with a main control module through a PCIe bus, and realizing module self-checking and software online upgrading through an LAN (local area network);

the audio and video data acquisition module executes the following steps of acquiring video signals, acquiring 4 paths of audio signals, realizing a hardware time marking function through an FPGA (field programmable gate array), realizing data exchange with the main control module through a PCIe (peripheral component interconnect express) bus, and realizing module self-checking and software online upgrading through an LAN (local area network).

The invention has the advantages of reasonable design, low cost, firmness, durability, safety, reliability, simple operation, time and labor saving, capital saving, compact structure and convenient use.

Drawings

FIG. 1 is a block diagram of the system components of the present invention.

Fig. 2 is a cross-linking block diagram of the internal modules of the collector of the present invention.

FIG. 3 is a physical link diagram of the PCIe bus of the present invention.

FIG. 4 is a diagram of the PCIe bus specification of the present invention in relation to bus frequency and encoding.

FIG. 5 is a graph of the peak bandwidth of the PCIe bus of the present invention.

FIG. 6 is an IRIG B code diagram of the present invention.

FIG. 7 is a diagram of the internal maintenance bus cross-linking of the collector of the present invention.

FIG. 8 is a functional block diagram of the voltage signal acquisition module of the present invention.

Fig. 9 is a functional block diagram of the power conversion module of the present invention.

Fig. 10 is a functional block diagram of a master control module of the present invention.

Fig. 11 is a schematic diagram of a switching signal acquisition module of the present invention.

FIG. 12 is a functional block diagram of the vibration data acquisition module of the present invention.

FIG. 13 is a functional block diagram of a bus acquisition module of the present invention.

Fig. 14 is a functional block diagram of an audio-video data acquisition module of the present invention.

FIG. 15 is a schematic block diagram of a cache card according to the present invention.

FIG. 16 is a table diagram of the flight parameter recording system of the present invention.

FIG. 17 is a table of an integrated research data acquisition system and vibration monitoring system of the present invention.

Fig. 18 is a schematic structural view of the collector of the present invention.

Fig. 19 is a schematic view of the collector connection structure of the present invention.

Wherein: 1. a box body; 2. perforating; 3. a connecting rod; 4. a transverse clamping groove; 5. a transverse connecting block; 6. positioning the bolt; 7. a slot clamping hole.

Detailed Description

Referring to fig. 1-19, the integrated data collection and recording system of the present embodiment includes an integrated data collector, a cache card and a protection recorder on the onboard portion; the comprehensive data acquisition unit is electrically connected with the protection recorder through the Ethernet;

the comprehensive data acquisition unit is electrically connected with the onboard power supply; the input end of the on-board monitoring device is used for collecting on-board signals on an airborne part, and the on-board signals comprise switching signals, frequency signals, voltage signals, vibration signals, an ARINC429 bus, an RS422 bus, an MIL-STD-155B bus, an AFDX bus, audio signals and video signals; the data of the acquired onboard signals are packed according to the IRIG-106 standard and then sent to a quick access recording card and a protection recorder for recording;

the quick access recording card adopts the SATA bus to be cross-linked with the comprehensive data acquisition unit to complete the recording of all the acquired data;

the protection recorder adopts a gigabit Ethernet bus to be crosslinked with the comprehensive data acquisition unit to complete the recording of important data; the vital data includes data used for incident analysis;

an unloading calibrator and a flight parameter data ground comprehensive analysis processing system are arranged on the ground;

the unloading checker is respectively linked with the protection recorder and the comprehensive data collector through Ethernet; the output end of the unloading calibrator is electrically connected with the input end of the ground comprehensive analysis and processing system of the flight parameter data so as to import the data;

the case structure of the integrated data acquisition unit adopts a backboard-free form, and the modules are interconnected through connectors between the boards for communication and power supply. The method brings challenges to a high-speed bus, the high-speed bus needs to pass through a plurality of connectors from a main control board to a farthest acquisition board card, and signal integrity has certain difficulty.

One embodiment of the invention uses long screws for mutual fixation, which is a mode that is relatively well maintained. Each module adopts a structure sealing design, and the EMC performance is relatively good.

The integrated data acquisition device is based on a modularized case and comprises a power supply module, a main control module adopting an integrated quick access recording card, a voltage signal acquisition module I, a voltage signal acquisition module II, a switch signal acquisition module, a vibration signal acquisition module, a bus acquisition module and an audio and video acquisition module;

the master control module, the voltage signal acquisition module I, the voltage signal acquisition module II, the switch signal acquisition module, the vibration signal acquisition module, the bus acquisition module and the audio and video acquisition module are respectively provided with

A BIT test capability module; the BIT test capability module has three self-checking modes, including PBIT power-on self-checking, CBIT periodic self-checking and IBIT maintenance self-checking;

the fault logging module is used for providing a fault logging means through a LAN bus, fault information is stored in the nonvolatile memory, and each piece of fault recording information must contain timestamp information;

each module realizes time synchronization by using IRIG-B codes, and uses hardware to mark time marks with the time synchronization precision of 100 ns;

the power supply module comprises a PCU power supply conversion unit, combines and inputs a normal power supply and an emergency power supply, and converts a direct current 28V input voltage into a direct current 24Vd bottom plate voltage;

the voltage range of the normal power supply is 22V-30V; the voltage range of the emergency power supply is 18V-30V;

a PSA power supply having an output voltage monitoring and switch control module cross-linked with the NIU module; the output voltage monitoring and switch control module is responsible for switching on, switching off and monitoring different power supply outputs of other modules in the rack;

the NIU module is used for managing a power supply in the rack and detecting power supply distribution faults through the CPU module and the PHY module which are crosslinked through an internal MII signal; the CPU module controls the PSA based on information received from the system to provide power to the desired module; the PHY module communicates with the system through the LAN channel;

the PCU power conversion unit comprises an energy storage capacitor, a holding module, a filtering module and a DC-DC module I; the input end of the filtering module is connected with an external power supply, and the input end of the holding module is respectively connected with the energy storage capacitor and the output end of the filtering module; the output end of the holding module is connected with the input end of the DC-DC module I; the DC-DC module I outputs +24V voltage;

the system comprises a voltage signal acquisition module I for inputting 32-path voltage signals, a voltage signal acquisition module II for inputting 32-path voltage signals, a switch signal acquisition module for inputting switch signals and frequency signals, a vibration signal acquisition module for inputting vibration signals, a bus acquisition module for inputting ARINC429, RS422, MIL-STD-1553B and/or AFDX signals, and an audio and video acquisition module for inputting audio signals and video signals, wherein the audio and video acquisition module completes the exchange of acquired data through a PCIe bus and a main control module and completes the exchange of maintenance information through a LAN bus and the main control module, and the maintenance information comprises self-checking information, software upgrading, log information and parameter monitoring;

the main control module is internally integrated with an FPGA integrated circuit, an LAN switch chip, a PCIe switch chip, a CPU, a synchronous signal module and an RTC chip; the PCIe switch chip is respectively exchanged with the voltage signal acquisition module I, the voltage signal acquisition module II, the switch signal acquisition module, the vibration signal acquisition module, the bus acquisition module and the audio and video acquisition module through a PCIe bus and an input end of the synchronous signal module through an IRIG-B channel;

the LAN switch chip cross-links the maintenance information with the unloading checker through LAN; maintaining log information and storing the log information in an SATA hard disk integrated on a main control module; the LAN switch chip is crosslinked with the CPU through LAN;

the PCIe switch chip and the CPU are switched through a PCIe bus; the CPU is electrically connected with the quick access recording card through the SATA channel;

the synchronous signal module receives an RTC time service signal of the RTC chip;

in a physical link of a PCIe bus, the PCIe link uses an end-to-end data transmission mode, and a sending end and a receiving end both contain TX sending logic and RX receiving logic; the PCIe link comprises a plurality of data paths Lane; in the data path Lane, a transmitting link of a transmitting end and a transmitting link of a receiving end are included;

a TX component of the transmitting end is connected with an RX component of the receiving end using a set of differential signals;

the RX component of the transmitting end and the TX component of the receiving end are connected by another set of differential signals, and this link is also called a receiving link of the transmitting end, i.e. a transmitting link of the receiving end;

the PCIe link carries out data transmission through differential signals, the differential signals comprise D + and D-, and the signal receiving end judges whether the transmitting end sends logic '1' or logic '0' by comparing the difference value of the D + and D-signals.

The master control module realizes the PCIe switch function: the system is used for exchanging data with other functional modules, and the number of the ports is not less than 7; implementing LAN switch functions: the number of the ports is not less than 8; 3) CPU adopts PowerPC series processor, the operating system adopts VxWorks of wind river; one-way gigabit Ethernet is realized and is used for interfacing with a protection recorder; two SATA paths are realized: one path is used for interfacing with the quick access recording card, and the other path is used for carrying an SATA hard disk and storing log information and the like; the time synchronization function module is realized: generating 8 paths of IRIG-B codes to be sent to other functional modules through RTC or GPS time service; the hardware timing mark function is realized through the FPGA, and the time synchronization precision can reach 100 ns; data exchange with the main control module is realized through a PCIe bus; and the functions of module self-checking, software upgrading and the like are realized through the LAN.

The electrical specification of high-speed differential signals requires that the transmitter side be connected in series with a capacitor for AC coupling. This capacitance is also referred to as an AC coupling capacitance. Compared with single-ended signals, the differential signals have stronger interference resistance because the differential signals are required to be equal in length, equal in width and close to each other during wiring and are on the same layer. Thus, the external interference noise will be "in-phase" and "simultaneously" applied to both the D + and D-signals, the difference between which is ideally 0, with less effect on the logic values of the signals. Thus, differential signaling may use a higher bus frequency.

In addition, the use of differential signals can effectively suppress electromagnetic interference (EMI). Because the differential signals D + and D-are close to each other and the signals are equal in amplitude and opposite in polarity. The amplitude of the coupling electromagnetic field between the two wires and the ground wire is equal, and the two wires and the ground wire are mutually offset, so that the differential signal has small electromagnetic interference to the outside. The disadvantages of differential signals are also obvious, and firstly, the differential signals use two signals to transmit one bit of data; secondly, the wiring of the differential signals is relatively strict.

Different PCIe bus specifications use different bus frequencies and use different data encoding methods. The PCIe bus V1.x and V2.0 specifications use 8/10b encoding in the physical layer, that is, 10 bits on the PCIe link contain 8 bits of valid data; the V3.0 specification uses 128/130b encoding, i.e., 130 bits on the PCIe link contain 128 bits of valid data. As shown in the graph, the V3.0 specification uses a bus frequency of only 4GHz, but has an effective bandwidth twice that of V2. x. The v2.x specification is taken as an example to illustrate the peak bandwidth that can be provided by PCIe links of different widths.

The effective bandwidth provided by the PCIe bus is still much higher than the PCI bus. PCIe buses also have their weaknesses, the most prominent of which is transfer latency. The PCIe link uses serial mode for data transmission, however, the data bus is still parallel inside the chip, so the PCIe link interface needs serial-parallel conversion, which will generate large delay. In addition, data messages of the PCIe bus need to pass through the transaction layer, the data link layer, and the physical layer, and these data messages will also cause delay when passing through these layers.

Data transmission between physical links of the PCIe bus uses a synchronous transmission mechanism based on a clock, but a clock line does not exist on the physical links, and a receiving end of the PCIe bus comprises a clock recovery module (CDR) which extracts a receiving clock from a received message so as to perform synchronous Data transmission.

The main control module receives GPS signals or adopts a built-in RTC clock to form uniform synchronous signals which are sent to other modules for use, and the synchronous signals adopt IRIG-B codes.

As the Global Positioning System (GPS) has become a global shared time distribution system with extremely high accuracy, GPS-based time tick signals have been widely used in many fields. Currently, many manufacturers have introduced GPS-based synchronous time synchronization devices. The devices adopt various modes to provide accurate time signals, such as a pulse synchronization mode, a serial port information synchronization mode, an IRIG-B code information synchronization mode and the like, and the modes have advantages and disadvantages. The IRIG-B code is used as an international universal time code, is accurate in time synchronization, simplifies a time synchronization loop, and contains complete absolute time scale information, so that the IRIG-B code is widely applied. The code has been widely applied to time-domain equipment such as missiles, spaceflight, remote measurement and the like, and has high implementation precision and strong stability.

IRIG codes have 4 parallel binary time code formats and 6 serial binary time code formats, among which the most common is IRIG-B time code format, which transmits time information at a frequency of once per second, including not only pulse-per-second information, but also absolute time information including year, day, hour, minute, second, binary second, day, and the like.

As shown, which is a serial time code of one frame per second, each symbol has a total width of 10ms, and one time frame period includes 100 symbols, which is pulse width encoded. Each symbol has 3 patterns: binary 0, 1 and a location identifier. Encoding is divided into 3 fields: the 1 st field is the time of year (year, day, hour, minute, second), the 2 nd field is the control function field, the 3 rd field is the time of day information directly represented by a binary second symbol, and the cycle is 1 time every 24 hours. The 'on-time' reference point of the code element is the leading edge of the pulse, the reference mark of the time frame consists of a position identification mark and adjacent reference code elements, and the pulse width of the reference mark is 8 ms; there is one position identifier per 10 symbols, so there are 10 position identifiers in 1 second, namely: p1, P2, P3, …, P9, P0, all of which have a pulse width of 8 ms; PR is a frame reference point; the pulse widths of binary "1" and "0" are 5ms and 2ms, respectively.

The voltage signal acquisition module is provided with a voltage signal conditioning module, an AD sampling module, a self-checking circuit, an FPGA integrated circuit I, CPU1 and a port PHYI;

the input end of the voltage signal conditioning module inputs 32 paths of voltage signals; the input end of the AD sampling module is electrically connected with the output end of the voltage signal conditioning module, the output end of the AD sampling module is electrically connected with the input end of an FPGA integrated circuit I, and the FPGA integrated circuit I is electrically connected with the CPU 1; the self-checking circuit is respectively and electrically connected with the voltage signal conditioning module, the AD sampling module, the FPGA integrated circuit I and the CPU 1;

the FPGA integrated circuit I receives the IRIG-B synchronous signal and is in cross-linking with a PCIe bus;

CPU1 cross-links the LAN signal through port PHYI;

the voltage signal acquisition module realizes the following functions: 1) collecting 32 voltage signals; 2) the voltage signal input range can be set by software; 3) the hardware timing mark function is realized through the FPGA, and the time synchronization precision can reach 100 ns; 4) data exchange with the main control module is realized through a PCIe bus; 5) and the functions of module self-checking, software upgrading and the like are realized through the LAN.

The switching signal acquisition module comprises a switching signal conditioning module, a frequency signal conditioning module, a switching signal self-checking circuit, a switching signal CPU, a switching signal port and a switching signal integrated circuit;

the input end of the switching signal conditioning module receives 96 switching signal inputs, and the output end of the switching signal conditioning module is electrically connected with the switching signal integrated circuit;

the frequency signal conditioning module receives 6 paths of frequency signal input, is crosslinked with the switching signal conditioning module, and has an output end electrically connected with the switching signal integrated circuit;

the switching signal integrated circuit receives an IRIG-B synchronous signal and is in cross-linking with the PCle bus;

the switching signal CPU is crosslinked with the switching signal integrated circuit and is connected with the LAN port through a switching signal port;

the switching signal self-checking circuit comprises a switching signal self-checking circuit, a self-checking switching signal conditioning module, a frequency signal conditioning module and a switching signal CPU;

the switch signal acquisition module realizes the following functions: 1) collecting 96 switching signals; 2) collecting 6 paths of frequency signals; 3) the hardware timing mark function is realized through the FPGA, and the time synchronization precision can reach 100 ns; 4) data exchange with the main control module is realized through a PCIe bus; 5) and the functions of module self-checking, software upgrading and the like are realized through the LAN.

The system comprises a vibration data acquisition module, a vibration signal conditioning module for receiving vibration signals, an azimuth signal conditioning module for receiving azimuth signals, a vibration data AD sampling module, a vibration data self-checking circuit, a vibration circuit FPGA module, an oscillation data CPU and a vibration data PHY port;

the vibration signal conditioning module is connected with the input end of the vibration circuit FPGA module through a vibration data AD sampling module, and the output end of the azimuth angle signal conditioning module is connected with the input end of the vibration circuit FPGA module;

the oscillation data CPU is crosslinked with the oscillation circuit FPGA module and is connected with the LAN channel through an oscillation data PHY port; the FPGA module of the vibration circuit receives and receives IRIG-B synchronous signals and cross-links a PCle bus; the vibration data self-checking circuit is used for self-checking the vibration signal conditioning module, the azimuth angle signal conditioning module, the vibration data AD sampling module and the vibration data CPU;

the vibration data acquisition module realizes the following functions: 1) collecting 4 paths of azimuth angle signals; 2) collecting 16 paths of vibration signals; 3) the hardware timing mark function is realized through the FPGA, and the time synchronization precision can reach 100 ns; 4) data exchange with the main control module is realized through a PCIe bus; 5) and the functions of module self-checking, software online upgrading and the like are realized through the LAN.

The bus acquisition module comprises an RS422 interface conditioning module, an ARINC429 interface conditioning module, an MIL-STD-1553B interface conditioning module, an AFDX bus interface conditioning module, a bus FPGA module, a bus self-checking circuit, a bus CPU and a bus PHY;

the input end of the RS422 interface conditioning module is connected with an RS422 bus, the ARINC429 interface conditioning module is connected with an ARINC429 bus, the MIL-STD-1553B interface conditioning module is connected with an MIL-STD-1553B bus, and the AFDX bus interface conditioning module is connected with an AFDX bus;

the output ends of the RS422 interface conditioning module, the ARINC429 interface conditioning module, the MIL-STD-1553B interface conditioning module and the AFDX bus interface conditioning module are connected with the input end of the bus FPGA module;

the bus FPGA module is connected with an IRIG-B synchronous signal, a PCIe bus and a bus CPU; the bus CPU is connected with the LAN channel through a bus PHY;

the bus self-checking circuit comprises a RS422 interface conditioning module, an ARINC429 interface conditioning module, an MIL-STD-1553B interface conditioning module, an AFDX bus interface conditioning module and a bus CPU;

the realization function is as follows, 1) 8 paths of RS422 buses are collected; 2) collecting 8 paths of ARINC429 buses; 3) collecting 1 path of dual-redundancy MIL-STD-1553B bus; 4) collecting a 1-path dual-redundancy AFDX bus; 5) the hardware timing mark function is realized through the FPGA, and the time synchronization precision can reach 100 ns; 6) data exchange with the main control module is realized through a PCIe bus; 7) and the functions of module self-checking, software online upgrading and the like are realized through the LAN.

The audio and video data acquisition module comprises a video signal conditioning module for receiving a video signal, an audio signal conditioning module for receiving an audio signal, a video acquisition module, an audio and video AD sampling module, an audio and video self-checking circuit, an audio and video FPGA module, an audio and video self-checking circuit, an audio and video CPU and an audio and video PHY;

the audio and video FPGA module receives the output signal of the video signal conditioning module through the video acquisition module; receiving an audio signal conditioning module through an audio and video AD sampling module; the audio and video FPGA module is connected with an IRIG-B synchronous signal, a PCIe bus and a bus CPU; the audio/video CPU is connected with the LAN channel through the audio/video PHY;

the audio and video self-detection circuit comprises a video signal conditioning module, an audio signal conditioning module and an audio and video CPU;

the audio and video data acquisition module realizes the following functions: 1) 2 paths of video signals are collected; 2) collecting 4 paths of audio signals; 3) the hardware timing mark function is realized through the FPGA, and the time synchronization precision can reach 100 ns; 4) data exchange with the main control module is realized through a PCIe bus; 5) and the functions of module self-checking, software online upgrading and the like are realized through the LAN.

The quick access recording card is integrated on the main control module and adopts the SATA bus to communicate with the main control module; the quick access recording card uses a reinforced FLASH hard disk and is connected with the outside through a switching board with a DMU connector;

the memory capacity is not less than 256G. Because the cache recording card is frequently required to unload recorded data and frequently plug and unplug the cache recording card, and the common SATA connector does not have the durability, the SATA connector is converted into an HJ30J-18 high-reliability rectangular connector through a switching board, the transmission speed of the HJ30J-18 can reach 3Gbps, and the SATA signal transmission requirement is met. The FLASH hard disk is reinforced by selecting aluminum alloy to reinforce the shell, so that the reliability of the product is improved.

The protection recorder adopts a fixed memory, the recording mode adopts cycle recording, the protection recorder is provided with a gigabit Ethernet interface, and the crash-resistant capability meets the standards of TSO-C123b and TSO-C124b or other related standards.

In the system software architecture, an operating system adopts VxWorks6.6 or more, and a data recording format adopts an IRIG-106 standard; PCIe communication protocol realizes data exchange between the acquisition module and the main control module in the collector, and the aim of plug and play is realized.

The collector comprises a plurality of box bodies 1; the box body 1 is detachably connected with a through hole 2 on the box body 1;

according to the first scheme, a connecting rod 3 penetrates through a through hole 2, a gasket is sleeved on the connecting rod 3 and is arranged between box bodies 1; a nut and a washer are arranged at the end part of the connecting rod 3; thereby realizing the modular design and convenient disassembly, assembly and maintenance.

According to the second scheme, transverse clamping grooves 4 are respectively and transversely arranged at the upper part and the lower part of the outer side walls of the two sides of the box body 1, a transverse connecting block 5 is arranged between the side walls of the adjacent box bodies 1, the two sides of each transverse connecting block 5 are respectively inserted into the corresponding transverse clamping grooves 4, and clamping groove holes 7 are formed in the transverse clamping grooves 4 and are connected with positioning bolts 6 through threads; the lower end of the positioning bolt 6 is connected on the transverse connecting block 5. Scheme one, exist and damage when a certain collector module, need take off whole, need reserve lateral part connecting rod removal space moreover, use inconvenient.

According to the third scheme, a connecting rod 3 penetrates through the through hole 2, a gasket is sleeved on the connecting rod 3 and is arranged between the box bodies 1; a nut and a washer are arranged at the end part of the connecting rod 3; the upper part and the lower part of the outer side walls of the two sides of the box body 1 are respectively and transversely provided with a transverse clamping groove 4, a transverse connecting block 5 is arranged between the side walls of the adjacent box bodies 1, the two sides of the transverse connecting block 5 are respectively inserted into the corresponding transverse clamping grooves 4, and the transverse clamping grooves 4 are provided with clamping groove holes 7 which are connected with positioning bolts 6 through threads; the lower end of the positioning bolt 6 is connected on the transverse connecting block 5. The space is enough, and when the requirement for stability is higher, the first scheme and the second scheme are combined for use, so that the overall stability of the box body is enhanced, and convenience in disassembly is kept.

According to the fourth scheme, transverse clamping grooves 4 are respectively and transversely arranged at the upper part and the lower part of the outer side walls of the two sides of the box body 1, a transverse connecting block 5 is arranged between the side walls of the adjacent box bodies 1, the two sides of each transverse connecting block 5 are respectively inserted into the corresponding transverse clamping grooves 4, and clamping groove holes 7 are formed in the transverse clamping grooves 4 and are connected with positioning bolts 6 through threads; 6 lower extremes of positioning bolt are connected on transverse connection piece 5, still reserve a plurality of two-sided horizontal draw-in grooves of substitution, and it is aequilate with box body 1, after certain collector is taken off, installs this position through two-sided horizontal draw-in groove to guarantee that whole module's position is unchangeable.

Claims (10)

1. The utility model provides an airborne data synthesizes collection record system which characterized in that: the system comprises a comprehensive data acquisition unit, a quick access recording card and a protection recorder which are positioned on an airborne part; the comprehensive data acquisition unit is electrically connected with the protection recorder through the Ethernet;

the comprehensive data acquisition unit is electrically connected with the onboard power supply; the input end of the on-board monitoring device is used for collecting on-board signals on an airborne part, and the on-board signals comprise switching signals, frequency signals, voltage signals, vibration signals, an ARINC429 bus, an RS422 bus, an MIL-STD-155B bus, an AFDX bus, audio signals and video signals; the data of the acquired onboard signals are packed according to the IRIG-106 standard and then sent to a quick access recording card and a protection recorder for recording;

the quick access recording card adopts the SATA bus to be cross-linked with the comprehensive data acquisition unit to complete the recording of all the acquired data;

the protection recorder adopts a gigabit Ethernet bus to be crosslinked with the comprehensive data acquisition unit to complete the recording of important data; the vital data includes data used for incident analysis;

an unloading calibrator and a flight parameter data ground comprehensive analysis processing system are arranged on the ground;

the unloading checker is respectively linked with the protection recorder and the comprehensive data collector through Ethernet; the output end of the unloading checker is electrically connected with the input end of the ground comprehensive analysis and processing system of the flight parameter data so as to import the data.

2. The system according to claim 1, wherein:

the chassis structure of the integrated data acquisition unit adopts a non-backplane form, and the communication and power supply among the modules are interconnected through an inter-board connector;

the comprehensive data acquisition device comprises a power supply module, a main control module adopting an integrated cache recording card, a voltage signal acquisition module I, a voltage signal acquisition module II, a switch signal acquisition module, a vibration signal acquisition module, a bus acquisition module and an audio and video acquisition module;

the master control module, the voltage signal acquisition module I, the voltage signal acquisition module II, the switch signal acquisition module, the vibration signal acquisition module, the bus acquisition module and the audio and video acquisition module are respectively provided with

A BIT test capability module; the BIT test capability module has three self-checking modes, including PBIT power-on self-checking, CBIT periodic self-checking and IBIT maintenance self-checking;

the fault logging module is used for providing a fault logging means through a LAN bus, fault information is stored in the nonvolatile memory, and each piece of fault recording information must contain timestamp information;

and each module of the time synchronization module realizes time synchronization by using IRIG-B codes, time marks are marked by using hardware, and the time synchronization precision is 100 ns.

3. The system according to claim 2, wherein: in the comprehensive data acquisition unit, a power supply module comprises a Power Control Unit (PCU) power supply conversion unit, combines and inputs a normal power supply and an emergency power supply, and converts a direct current 28V input voltage into a direct current 24Vd bottom plate voltage;

the voltage range of the normal power supply is 22V-30V; the voltage range of the emergency power supply is 18V-30V;

a PSA power supply having an output voltage monitoring and switch control module cross-linked with the NIU module; the output voltage monitoring and switch control module is responsible for switching on, switching off and monitoring different power supply outputs of other modules in the rack;

the NIU module is used for managing a power supply in the rack and detecting power supply distribution faults through the CPU module and the PHY module which are crosslinked through an internal MII signal; the CPU module controls the PSA based on information received from the system to provide power to the desired module; the PHY module communicates with the system over a LAN channel.

4. The system according to claim 3, wherein: the PCU power conversion unit comprises an energy storage capacitor, a holding module, a filtering module and a DC-DC module I; the input end of the filtering module is connected with an external power supply, and the input end of the holding module is respectively connected with the energy storage capacitor and the output end of the filtering module; the output end of the holding module is connected with the input end of the DC-DC module I; the DC-DC module I outputs +24V voltage;

the system comprises a voltage signal acquisition module I for inputting 32-path voltage signals, a voltage signal acquisition module II for inputting 32-path voltage signals, a switch signal acquisition module for inputting switch signals and frequency signals, a vibration signal acquisition module for inputting vibration signals, a bus acquisition module for inputting ARINC429, RS422, MIL-STD-1553B and/or AFDX signals, and an audio and video acquisition module for inputting audio signals and video signals, wherein the audio and video acquisition module completes the exchange of acquired data through a PCIe bus and a main control module and completes the exchange of maintenance information through a LAN bus and the main control module, and the maintenance information comprises self-checking information, software upgrading, log information and parameter monitoring;

the main control module is internally integrated with an FPGA integrated circuit, an LAN switch chip, a PCIe switch chip, a CPU, a synchronous signal module and an RTC chip; the PCIe switch chip is respectively exchanged with the voltage signal acquisition module I, the voltage signal acquisition module II, the switch signal acquisition module, the vibration signal acquisition module, the bus acquisition module and the audio and video acquisition module through a PCIe bus and an input end of the synchronous signal module through an IRIG-B channel;

the LAN switch chip cross-links the maintenance information with the unloading checker through LAN; maintaining log information and storing the log information in an SATA hard disk integrated on a main control module; the LAN switch chip is crosslinked with the CPU through LAN;

the PCIe switch chip and the CPU are switched through a PCIe bus; the CPU is electrically connected with the quick access recording card through the SATA channel;

the synchronous signal module receives an RTC time service signal of the RTC chip;

in a physical link of a PCIe bus, the PCIe link uses an end-to-end data transmission mode, and a sending end and a receiving end both contain TX sending logic and RX receiving logic; the PCIe link comprises a plurality of data paths Lane; in the data path Lane, a transmitting link of a transmitting end and a transmitting link of a receiving end are included;

a TX component of the transmitting end is connected with an RX component of the receiving end using a set of differential signals;

the RX component of the transmitting end and the TX component of the receiving end are connected by another set of differential signals, and this link is also called a receiving link of the transmitting end, i.e. a transmitting link of the receiving end;

the PCIe link carries out data transmission through a differential signal, the differential signal comprises a D + signal and a D-signal, and the signal receiving end judges whether the signal sent by the sending end is a logic 1 or a logic 0 by comparing the difference value of the D + signal and the D-signal;

the voltage signal acquisition module is provided with a voltage signal conditioning module, an AD sampling module, a self-checking circuit, an FPGA integrated circuit I, CPU1 and a port PHYI;

the input end of the voltage signal conditioning module inputs 32 paths of voltage signals; the input end of the AD sampling module is electrically connected with the output end of the voltage signal conditioning module, the output end of the AD sampling module is electrically connected with the input end of an FPGA integrated circuit I, and the FPGA integrated circuit I is electrically connected with the CPU 1; the self-checking circuit is respectively and electrically connected with the voltage signal conditioning module, the AD sampling module, the FPGA integrated circuit I and the CPU 1;

the FPGA integrated circuit I receives the IRIG-B synchronous signal and is in cross-linking with a PCIe bus;

CPU1 cross-links the LAN signal through port PHYI;

the switching signal acquisition module comprises a switching signal conditioning module, a frequency signal conditioning module, a switching signal self-checking circuit, a switching signal CPU, a switching signal port and a switching signal integrated circuit;

the input end of the switching signal conditioning module receives 96 switching signal inputs, and the output end of the switching signal conditioning module is electrically connected with the switching signal integrated circuit;

and the frequency signal conditioning module receives 6 paths of frequency signal input, is crosslinked with the switching signal conditioning module, and has an output end electrically connected with the switching signal integrated circuit.

5. The system according to claim 4, wherein: the switching signal integrated circuit receives an IRIG-B synchronous signal and is in cross-linking with the PCle bus;

the switching signal CPU is crosslinked with the switching signal integrated circuit and is connected with the LAN port through a switching signal port;

the switching signal self-checking circuit comprises a switching signal self-checking circuit, a self-checking switching signal conditioning module, a frequency signal conditioning module and a switching signal CPU;

the system comprises a vibration data acquisition module, a vibration signal conditioning module for receiving vibration signals, an azimuth signal conditioning module for receiving azimuth signals, a vibration data AD sampling module, a vibration data self-checking circuit, a vibration circuit FPGA module, an oscillation data CPU and a vibration data PHY port;

the vibration signal conditioning module is connected with the input end of the vibration circuit FPGA module through a vibration data AD sampling module, and the output end of the azimuth angle signal conditioning module is connected with the input end of the vibration circuit FPGA module;

the oscillation data CPU is crosslinked with the oscillation circuit FPGA module and is connected with the LAN channel through an oscillation data PHY port; the FPGA module of the vibration circuit receives and receives IRIG-B synchronous signals and cross-links a PCle bus; the vibration data self-checking circuit is used for self-checking the vibration signal conditioning module, the azimuth angle signal conditioning module, the vibration data AD sampling module and the vibration data CPU.

6. The system according to claim 5, wherein: the bus acquisition module comprises an RS422 interface conditioning module, an ARINC429 interface conditioning module, an MIL-STD-1553B interface conditioning module, an AFDX bus interface conditioning module, a bus FPGA module, a bus self-checking circuit, a bus CPU and a bus PHY;

the input end of the RS422 interface conditioning module is connected with an RS422 bus, the ARINC429 interface conditioning module is connected with an ARINC429 bus, the MIL-STD-1553B interface conditioning module is connected with an MIL-STD-1553B bus, and the AFDX bus interface conditioning module is connected with an AFDX bus;

the output ends of the RS422 interface conditioning module, the ARINC429 interface conditioning module, the MIL-STD-1553B interface conditioning module and the AFDX bus interface conditioning module are connected with the input end of the bus FPGA module;

the bus FPGA module is connected with an IRIG-B synchronous signal, a PCIe bus and a bus CPU; the bus CPU is connected with the LAN channel through a bus PHY;

the bus self-checking circuit comprises a RS422 interface conditioning module, an ARINC429 interface conditioning module, an MIL-STD-1553B interface conditioning module, an AFDX bus interface conditioning module and a bus CPU;

the audio and video data acquisition module comprises a video signal conditioning module for receiving a video signal, an audio signal conditioning module for receiving an audio signal, a video acquisition module, an audio and video AD sampling module, an audio and video self-checking circuit, an audio and video FPGA module, an audio and video self-checking circuit, an audio and video CPU and an audio and video PHY;

the audio and video FPGA module receives the output signal of the video signal conditioning module through the video acquisition module; receiving an audio signal conditioning module through an audio and video AD sampling module; the audio and video FPGA module is connected with an IRIG-B synchronous signal, a PCIe bus and a bus CPU; the audio/video CPU is connected with the LAN channel through the audio/video PHY;

the audio and video self-detection circuit comprises a video signal conditioning module, an audio signal conditioning module and an audio and video CPU.

7. The system according to claim 1, wherein: the quick access recording card is integrated on the main control module and adopts the SATA bus to communicate with the main control module; the quick access recording card uses a reinforced FLASH hard disk and is connected with the outside through a switching board with a DMU connector;

the protection recorder adopts a fixed memory, adopts a cyclic recording mode and is provided with a gigabit Ethernet interface;

the quick access recording card is integrated on the main control module and adopts the SATA bus to communicate with the main control module; the quick access recording card uses a reinforced FLASH hard disk and is connected with the outside through a switching board with a DMU connector;

the protection recorder adopts a fixed memory, adopts a cyclic recording mode and is provided with a gigabit Ethernet interface.

8. The system according to claim 1, wherein: the collector comprises a plurality of box bodies; the box body is provided with a through hole and is detachably connected; the method comprises one of the following schemes;

according to the first scheme, a connecting rod penetrates through a through hole, a gasket is sleeved on the connecting rod, and the gasket is arranged between box bodies; a nut and a washer are arranged at the end part of the connecting rod;

according to the second scheme, transverse clamping grooves are respectively and transversely formed in the upper portion and the lower portion of the outer side walls of the two sides of the box body, a transverse connecting block is arranged between the side walls of the adjacent box bodies, the two sides of each transverse connecting block are respectively inserted into the corresponding transverse clamping grooves, and clamping groove holes are formed in the transverse clamping grooves and are connected with positioning bolts through threads; the lower end of the positioning bolt is connected to the transverse connecting block;

according to the third scheme, a connecting rod penetrates through the through hole, a gasket is sleeved on the connecting rod, and the gasket is arranged between the box bodies; a nut and a washer are arranged at the end part of the connecting rod; the upper part and the lower part of the outer side walls of two sides of the box body are respectively transversely provided with a transverse clamping groove, a transverse connecting block is arranged between the side walls of the adjacent box bodies, two sides of the transverse connecting block are respectively inserted into the corresponding transverse clamping grooves, and the transverse clamping grooves are provided with clamping groove holes which are connected with positioning bolts through threads; the lower end of the positioning bolt is connected to the transverse connecting block;

according to the fourth scheme, transverse clamping grooves are respectively and transversely formed in the upper portion and the lower portion of the outer side walls of the two sides of the box body, a transverse connecting block is arranged between the side walls of the adjacent box bodies, the two sides of each transverse connecting block are respectively inserted into the corresponding transverse clamping grooves, and clamping groove holes are formed in the transverse clamping grooves and are connected with positioning bolts through threads; the positioning bolt lower extreme is connected on transverse connection piece, still reserve a plurality of two-sided horizontal draw-in grooves of substitution, and it is as wide as the box body, after certain collector is taken off, installs this position through two-sided horizontal draw-in groove to guarantee that whole module's position is unchangeable.

9. An airborne data comprehensive acquisition and recording method is characterized in that: by means of the onboard data comprehensive acquisition and recording system of claim 1,

firstly, sending an onboard signal to a comprehensive data acquisition unit; then, the collector stores the signal in the quick-access recording card and cross-links with the unloading checker; and thirdly, importing the data into a ground comprehensive analysis processing system of the flight parameter data by the unloading calibrator.

10. The method for comprehensively acquiring and recording the airborne data according to claim 9, wherein the method comprises the following steps: during the work of the comprehensive data collector, the main control module executes the PCIe switch function to exchange data, performs the LAN switch function, performs the maintenance function, realizes the time synchronization function module, generates IRIG-B code output through RTC or GPS time service, realizes the hardware time marking function through FPGA, exchanges data with the main control module through a PCIe bus, and realizes module self-checking and software upgrading through LAN;

the voltage signal acquisition module executes voltage signal acquisition, the input range of the voltage signal is set through software, the hardware time marking function is realized through an FPGA (field programmable gate array), data exchange with the main control module is realized through a PCIe (peripheral component interconnect express) bus, and module self-checking and software upgrading are realized through an LAN (local area network);

the switching signal acquisition module executes the following steps; collecting a switch signal, collecting a frequency signal, performing a hardware time marking function through an FPGA, realizing data exchange with a main control module through a PCIe bus, and realizing module self-checking and software upgrading through an LAN;

the vibration data acquisition module executes the following steps; acquiring an azimuth angle signal, acquiring a vibration signal, realizing a hardware time marking function through an FPGA, realizing data exchange with a main control module through a PCIe bus, and realizing module self-checking and software online upgrading through an LAN;

the bus acquisition module executes the following steps of acquiring an RS422 bus, acquiring 8 paths of ARINC429 buses, acquiring a dual-redundancy MIL-STD-1553B bus, acquiring a dual-redundancy AFDX bus, realizing a hardware time marking function through an FPGA (field programmable gate array), realizing data exchange with a main control module through a PCIe bus, and realizing module self-checking and software online upgrading through an LAN (local area network);

the audio and video data acquisition module executes the following steps of acquiring video signals, acquiring 4 paths of audio signals, realizing a hardware time marking function through an FPGA (field programmable gate array), realizing data exchange with the main control module through a PCIe (peripheral component interconnect express) bus, and realizing module self-checking and software online upgrading through an LAN (local area network).

Images