CN208705384U - Electric power system fault distributed synchronization recording system - Google Patents
Electric power system fault distributed synchronization recording system Download PDFInfo
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- CN208705384U CN208705384U CN201821334777.1U CN201821334777U CN208705384U CN 208705384 U CN208705384 U CN 208705384U CN 201821334777 U CN201821334777 U CN 201821334777U CN 208705384 U CN208705384 U CN 208705384U
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Abstract
The utility model discloses a kind of electric power system fault distributed synchronization recording systems, including a Main Control Tank and an at least analog acquisition case, Main Control Tank sends Synchronous Sampling Pulse signal to each vasculum, it is synchronous independent of clock synchronizations such as GPS, vasculum is only completed data acquisition and sends, it is not done directly recording function, recording function is realized by Main Control Tank.Analog quantity acquires in analog acquisition case, and switching value acquires in Main Control Tank, effectively avoids interfering with each other for analog quantity and switching value.This recording system be it is a kind of reliable, with the system of new way synchronous acquisition analog quantity and switching value.In case of a fault, this system can continuously record fault data；Under non-failure conditions, this system continuously can measure and record sampled data.This system can be widely applied to various power system monitoring occasions, be reliably completed the functions such as transient state recording and stable state recording.
Description
Technical field
The utility model relates to power system monitoring technology more particularly to a kind of electric power system fault distributed synchronization recordings
System.
Background technique
Currently, Power System Fault Record generally all includes that analog quantity and on-off value data acquisition, data transmission, failure are sentenced
The links such as disconnected and data storage.What wherein analog quantity and on-off value data acquisition, data transmission directly influenced recorder data can
By property and stability.A kind of integral type recording system that acquisition data are transmitted by backboard, the system are disclosed in the prior art
Using backboard transmission mode, it cannot achieve the discrete of acquisition unit and main control unit, be unfavorable for some engineering constructions.It is another existing
Have and disclose a kind of recording system that acquisition unit dependence GPS clock synchronization is synchronous in technology, each interval is there is still a need for acquisition unit and divides
Analyse unit, although the recording system will acquire it is discrete with recording, its acquisition unit it is synchronous dependent on GPS and be respectively spaced there is still a need for
Acquisition unit and analytical unit, do not realize distributed wave recording really.
Utility model content
In view of the drawbacks described above of the prior art, the utility model provides a kind of electric power system fault distributed synchronization recording system
System, to realize the distributed synchronization recording of electric power system fault.The utility model is achieved by the following technical solution:
A kind of electric power system fault distributed synchronization recording system, including an at least analog acquisition case and a master control
Case；DPU board and time management board are installed in the Main Control Tank；
The DPU board includes the first fpga chip and PPC chip, and first fpga chip and the PPC chip connect
Connect letter；
The time management board includes the second fpga chip and ARM chip, the ARM chip and the 2nd FPGA core
Piece connection communication；
Third fpga chip and analog-to-digital conversion module be installed in the analog acquisition case, the third fpga chip with
The analog-to-digital conversion module connection communication；
Second fpga chip is connect with first fpga chip and the third fpga chip, for reception pair
When source signal, and according to the clock synchronization source signal generate Synchronous Sampling Pulse signal, and by the Synchronous Sampling Pulse signal send out
Give first fpga chip and the third fpga chip；
The third fpga chip is connect with first fpga chip, for receiving the Synchronous Sampling Pulse
When signal, the analog-to-digital conversion module acquisition analog signals are controlled, and by the analog signals through the analog-to-digital conversion mould
The first digital quantity signal obtained after block conversion is sent to first fpga chip；
First fpga chip is connect with the ARM chip, for receiving the Synchronous Sampling Pulse signal
When, the second digital quantity signal is acquired by the ARM chip, and to first digital quantity signal and the second digital quantity signal into
Row processing.
Further, the first optical fiber interface is connected on first fpga chip, first fpga chip passes through institute
It states the first optical fiber interface to connect with the third fpga chip, the second optical fiber interface, institute is connected on second fpga chip
It states the second fpga chip and is connect by second optical fiber interface with the third fpga chip.
Further, 4 first optical fiber interfaces, second fpga chip are connected on first fpga chip
On be connected with 4 second optical fiber interfaces, the recording system includes 4 analog acquisition casees, the first FPGA
Chip is connected by the first different optical fiber interfaces from the third fpga chip in different analog acquisition casees, and described second
Fpga chip is connected by the second different optical fiber interfaces from the third fpga chip in different analog acquisition casees.
Further, GPS clock synchronization source signal interface and IRIG-B clock synchronization source signal are connected on second fpga chip
Interface.
Further, RS485 interface and the first CAN interface are connected on the ARM chip.
Further, installation is connected with 2 on the third fpga chip there are two the DPU board in the Main Control Tank
A third optical fiber interface, the third fpga chip pass through one of third optical fiber interface and one of DPU board the
The connection of one fpga chip, is connect by another third optical fiber interface with the first fpga chip of another DPU board.
Further, 2 Ethernet interfaces are connected on the PPC chip.
Further, 2 the second CAN interfaces are connected on the PPC chip.
Compared with prior art, electric power system fault distributed synchronization recording system provided by the utility model, including one
Platform Main Control Tank and at least an analog acquisition case, Main Control Tank send Synchronous Sampling Pulse signal to each vasculum, do not depend on
Synchronous in clock synchronizations such as GPS, vasculum is only completed data acquisition and sends, and is not done directly recording function, recording function is by master control
Case is realized.Analog quantity acquires in analog acquisition case, and switching value acquires in Main Control Tank, effectively avoids analog quantity and opens
Pass amount interferes with each other.This recording system be it is a kind of reliable, with the system of new way synchronous acquisition analog quantity and switching value.
In case of a fault, this system can continuously record fault data；Under non-failure conditions, this system continuously can measure and remember
Record sampled data.This system can be widely applied to various power system monitoring occasions, be reliably completed transient state recording and stable state record
The functions such as wave.
Detailed description of the invention
Fig. 1 is that the composed structure of electric power system fault distributed synchronization recording system provided by the embodiment of the utility model is shown
It is intended to.
Specific embodiment
For the purpose of this utility model, technical solution and advantage is more clearly understood, below with reference to embodiment and attached drawing,
The utility model is described in further detail.
Term is explained:
DPU:Distributed Processing Unit, decentralized processing unit；
PPC:Performance Optimization With Enhanced RISC-Performance
Computing, a kind of central processing unit of reduced instruction set computer framework；
FPGA:Field-Programmable Gate Array, field programmable gate array；
ARM:Advanced RISC Machines, a kind of reduced instruction set computer microprocessor；
As shown in Figure 1, electric power system fault distributed synchronization recording system provided by the utility model, including at least one
Analog acquisition case 2 and a Main Control Tank 1.DPU board 11 and time management board 12 are installed in Main Control Tank 1.
DPU board 11 includes the first fpga chip 111 and PPC chip 112, the first fpga chip 111 and PPC chip 112
Connection communication.The main sampled data decoding completed from analog acquisition case 2 of DPU board 11, outputs control at switch acquisition
System, data summarization, breakdown judge and record, system configuration, host computer communication etc..
Time management board 12 includes the second fpga chip 121 and ARM chip 122, ARM chip 122 and the 2nd FPGA core
121 connection communication of piece.ARM chip 122 completes initial configuration: initialization system time, configuration analog quantity sample rate, sample rate
Maximum can be configured to 12.8K sampling rate (50H, a cycle sample at 256 points).Second fpga chip 121 completion GPS signal,
The processing of IRIG-B code and sectors punching, exports synchronous sampling signal to analog acquisition case 2, and output system synchronization time is to ARM
Chip 122, ARM chip 122 complete the time communication of whole system.
Third fpga chip 22 and analog-to-digital conversion module 21 be installed in analog acquisition case 2, third fpga chip 22 with
21 connection communication of analog-to-digital conversion module.
Second fpga chip 121 is connect, for receiving clock synchronization source with the first fpga chip 111 and third fpga chip 22
Signal, and Synchronous Sampling Pulse signal is generated according to clock synchronization source signal, and Synchronous Sampling Pulse signal is sent to the first FPGA
Chip 111 and third fpga chip 22.
Third fpga chip 22 is connect with the first fpga chip 111, for when receiving Synchronous Sampling Pulse signal,
It controls analog-to-digital conversion module 21 and acquires analog signals, and that analog signals are obtained after the conversion of analog-to-digital conversion module 21
One digital quantity signal is sent to the first fpga chip 111.Analog-to-digital conversion module 21 is 16 analog-digital converters, and each analog quantity is adopted
Mountable three such analog-to-digital conversion modules 21 in header 2, third fpga chip 22 control three analog-to-digital conversion modules 21 into
Row synchronized sampling, an analog acquisition case 2 can acquire 16,24 tunnel analog data.
Support 128 tunnels are opened to output signal into 8 road of signal in Main Control Tank 1, by ARM chip 122 complete intake acquisition and
Output control.Switch acquisition and analog acquisition use consistent Synchronous Sampling Pulse signal, so switch acquisition
It is synchronous that data are automatically performed with analog acquisition, are handled without subsequent synchronisation, are guaranteed the primitiveness and synchronism of sampled data.The
One fpga chip 111, connect with ARM chip 122, for passing through ARM chip 122 when receiving Synchronous Sampling Pulse signal
The second digital quantity signal is acquired, and the first digital quantity signal and the second digital quantity signal are handled.
In the system, Main Control Tank 1 sends Synchronous Sampling Pulse signal to each vasculum, same independent of clock synchronizations such as GPS
Step, vasculum are only completed data acquisition and send, and are not done directly recording function, recording function is realized by Main Control Tank 1.Analog quantity
It being acquired in different cabinets with switching value, Main Control Tank 1 acquires on-off model, and analog acquisition case 2 acquires analog signals,
Effectively prevent interfering with each other for analog quantity and switching value.Simultaneously as analog quantity and switching value are according to same synchronized sampling arteries and veins
Signal acquisition is rushed, is synchronous acquisition, therefore the data that Main Control Tank 1DPU board 11 is got have been synchronous crude sampling numbers
According to it is synchronous not need to carry out data by modes such as interpolation, is based on this, the data of breakdown judge and record are all crude samplings
Value, will not introduce corresponding error, to truly record analog quantity and switching value information.
In the present embodiment, sampled data is encoded to Manchester's code.Digital quantity and switching value data pass through Man Chesi
Spy's coding, a high position first transmit, and encoded byte length is identical, and extra byte is spare, and the rate of data frame is all 20Mbit/s, that is, adjusts
Transmission rate after system is 40Mbit/s.Manchester's code is to be mainly used in a kind of coding mode of data synchronous transfer.
In Manchester's code, there is a jump in the centre of each, and the jump among position is not only used as clock signal, but also believes as data
Number；Jump indicates " 0 " from high to low, and jump indicates " 1 " from low to high.DC component is not present in coding, there is motor synchronizing energy
Power and good interference free performance.It is as shown in the table that sampled data encodes content frame:
Be connected with the first optical fiber interface on first fpga chip 111, the first fpga chip 111 by the first optical fiber interface with
Third fpga chip 22 connects, and is connected with the second optical fiber interface on the second fpga chip 121, and the second fpga chip 121 passes through the
Two optical fiber interfaces are connect with third fpga chip 22.
4 the first optical fiber interfaces, the corresponding analog quantity of each first optical fiber interface are connected on first fpga chip 111
Vasculum 2.4 the second optical fiber interfaces are connected on second fpga chip 121, each second optical fiber interface also corresponds to a simulation
Measure vasculum 2.Recording system includes 4 analog acquisition casees 2, and the first fpga chip 111 passes through the first different optical fiber interfaces
It is connected from the third fpga chip 22 in different analog acquisition casees 2, the second fpga chip 121 passes through the second different optical fiber
Interface is connected from the third fpga chip 22 in different analog acquisition casees 2.In this way, a Main Control Tank 1 can pass through 4 second
Optical fiber interface exports totally 4 tunnel Synchronous Sampling Pulse signal, controls 42 synchronized samplings of analog acquisition case, and pass through 4 first
Optical fiber interface receives the sampled data of 4 analog acquisition casees 2, can 96 road analog data of synchronous acquisition.First fpga chip
Two the first optical fiber interfaces as spare interface can be also in addition reconnected on 111.
GPS clock synchronization source signal interface and IRIG-B clock synchronization source signal interface are connected on second fpga chip 121, so that when
Between management board 12 support GPS clock synchronization and optical electrical IRIG-B code clock synchronization.
RS485 interface and the first CAN interface are connected on ARM chip 122.
Installation is connected with 2 third optical fiber interfaces on third fpga chip 22 there are two DPU board 11 in Main Control Tank 1, the
Three fpga chips 22 are connect by one of third optical fiber interface with the first fpga chip 111 of one of DPU board 11,
It is connect by another third optical fiber interface with the first fpga chip 111 of another DPU board 11.Two third optical fiber interfaces
The data of output are identical, in this way, the data that a DPU board 11 exports thereto of third fpga chip 22 can be used as transient state record
Wave, the data exported to another DPU board 11 can be used for stable state recording.
2 Ethernet interfaces are connected on PPC chip 112, one of them with host computer for communicating, another is as dimension
Protect debugging interface.Ethernet interface bandwidth is 100Mbps.In addition, being also connected with 2 the second CAN interfaces on PPC chip 112, use
In transmission CAN bus data.
Above-described embodiment is only preferred embodiment, the protection scope being not intended to limit the utility model, practical new at this
Made any modifications, equivalent replacements, and improvements etc., should be included in the protection of the utility model within the spirit and principle of type
Within the scope of.
Claims (8)
1. a kind of electric power system fault distributed synchronization recording system, which is characterized in that including an at least analog acquisition case
With a Main Control Tank；DPU board and time management board are installed in the Main Control Tank；
The DPU board includes the first fpga chip and PPC chip, and first fpga chip connect logical with the PPC chip
Letter；
The time management board includes the second fpga chip and ARM chip, and the ARM chip and second fpga chip connect
Connect letter；
Third fpga chip and analog-to-digital conversion module be installed in the analog acquisition case, the third fpga chip with it is described
Analog-to-digital conversion module connection communication；
Second fpga chip is connect, for receiving clock synchronization source with first fpga chip and the third fpga chip
Signal, and Synchronous Sampling Pulse signal is generated according to the clock synchronization source signal, and the Synchronous Sampling Pulse signal is sent to
First fpga chip and the third fpga chip；
The third fpga chip is connect with first fpga chip, for receiving the Synchronous Sampling Pulse signal
When, the analog-to-digital conversion module acquisition analog signals are controlled, and the analog signals are turned through the analog-to-digital conversion module
The first digital quantity signal obtained after changing is sent to first fpga chip；
First fpga chip is connect with the ARM chip, for leading to when receiving the Synchronous Sampling Pulse signal
Cross the ARM chip and acquire the second digital quantity signal, and to first digital quantity signal and the second digital quantity signal at
Reason.
2. electric power system fault distributed synchronization recording system as described in claim 1, which is characterized in that the first FPGA
The first optical fiber interface is connected on chip, first fpga chip passes through first optical fiber interface and the 3rd FPGA core
Piece connects, and the second optical fiber interface is connected on second fpga chip, and second fpga chip passes through second optical fiber
Interface is connect with the third fpga chip.
3. electric power system fault distributed synchronization recording system as claimed in claim 2, which is characterized in that the first FPGA
It is connected with 4 first optical fiber interfaces on chip, 4 second optical fiber interfaces are connected on second fpga chip,
The recording system includes 4 analog acquisition casees, first fpga chip by different the first optical fiber interface with
Third fpga chip connection in different analog acquisition casees, second fpga chip pass through the second different optical fiber interfaces
It is connected from the third fpga chip in different analog acquisition casees.
4. electric power system fault distributed synchronization recording system as described in claim 1, which is characterized in that the 2nd FPGA
GPS clock synchronization source signal interface and IRIG-B clock synchronization source signal interface are connected on chip.
5. electric power system fault distributed synchronization recording system as described in claim 1, which is characterized in that the ARM chip
On be connected with RS485 interface and the first CAN interface.
6. electric power system fault distributed synchronization recording system as described in claim 1, which is characterized in that in the Main Control Tank
Installation is connected with 2 third optical fiber interfaces, the 3rd FPGA core on the third fpga chip there are two the DPU board
Piece is connect by one of third optical fiber interface with the first fpga chip of one of DPU board, another third is passed through
Optical fiber interface is connect with the first fpga chip of another DPU board.
7. electric power system fault distributed synchronization recording system as described in claim 1, which is characterized in that the PPC chip
On be connected with 2 Ethernet interfaces.
8. electric power system fault distributed synchronization recording system as described in claim 1, which is characterized in that the PPC chip
On be connected with 2 the second CAN interfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821334777.1U CN208705384U (en) | 2018-08-17 | 2018-08-17 | Electric power system fault distributed synchronization recording system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821334777.1U CN208705384U (en) | 2018-08-17 | 2018-08-17 | Electric power system fault distributed synchronization recording system |
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| CN208705384U true CN208705384U (en) | 2019-04-05 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114280974A (en) * | 2021-11-17 | 2022-04-05 | 南京国电南自维美德自动化有限公司 | Centralized alternating current data sampling synchronization method and device based on FPGA |
-
2018
- 2018-08-17 CN CN201821334777.1U patent/CN208705384U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114280974A (en) * | 2021-11-17 | 2022-04-05 | 南京国电南自维美德自动化有限公司 | Centralized alternating current data sampling synchronization method and device based on FPGA |
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Granted publication date: 20190405 |