CN207021774U - A kind of Ship Electrical Power System failure wave-recording main frame - Google Patents

Abstract

A kind of Ship Electrical Power System failure wave-recording main frame, including communication processor, complicated programmable logic device, storage control, FLASH flash memories, solid state hard disc, programmable gate array chip, ethernet transceiver, photoelectrical coupler, UART Universal Asynchronous Receiver Transmitter FT232, DEBUG test chart, No.1 GBIC transceiver and No. two GBIC transceivers；The synchronization of recorder data is realized by the way of a Lagrangian interpolation resampling, has broken away from the dependence to external clock reference；Contour structures are simple, size is small, in light weight, are especially suitable for the narrow and small cabin spaces of ship and carry out installing multidiameter delay directly to adopt pattern at a high speed, improve the real-time Transmission ability of network, recording precision is high.

Description

A kind of Ship Electrical Power System failure wave-recording main frame

Technical field

A kind of recording main frame is the utility model is related to, specifically a kind of Ship Electrical Power System failure wave-recording main frame.

Background technology

Failure wave-recording main frame is a kind of smart machine generally used in national grid, when power system normal operation When, device only carries out the collection and monitoring in real time of data, and recording will be triggered when the disturbance such as short circuit or vibration occurs in system Process, the situation of change of the analog quantity such as the voltage of overall process, electric current and relay protection, breaker etc. before and after failure under complete documentation The action situation of switching value, technical staff can obtain desired fault message from the recorded wave file of preservation, not only can be real The defects of showing the fast positioning and accurate judgement of electric fault, and being advantageous to find relay protection and automatics, it is easy to day Further improve and perfect afterwards.If being included marine vessel power monitoring system, administrative staff can be undoubtedly greatly improved Operating efficiency, escort for the safe and stable operation of Ship Electrical Power System.

At present, failure wave-recording main frame both domestic and external mainly has following feature：

(1) at present, domestic and international land is generally synchronous using the networking based on external clock with failure wave-recording main frame, and which is led to The often time source on the basis of the satellite time transfer signal such as GPS, BDS, issued by clock server to the synchronous smart machine of needs Pulse per second (PPS), when receiving pair after signal, that calibrates inside realizes synchronized sampling from clock for collecting unit and recording main frame.

Although external clock Synchronos method is widely applied in national grid, ship failure wave-recording master is not particularly suited for Machine.First, it is navigator fix service that the satellite system installed on ship, which is typically, not yet plays the function of time synchronized, simultaneously Because Ship Structure is complicated, the recording main frame positioned at the bilge be difficult obtain deck upper strata pair when signal.Secondly, by marine severe The influence of weather conditions and ship Complex Power environment, satellite time transfer signal is heavily disturbed sometimes or even interrupts, once Problem occurs for clock source, and the temporal information for causing whole system is got muddled.Again, the introducing of clock server, which adds, is The complexity of system, once it breaks down whole synchronizing network will be caused to paralyse, and pair when equipment need to configure it is extra Clock input interface, add the design difficulty and hardware cost of device.Finally, satellite time service system be related to one it is national Strategic security, the gps signal in the U.S. and inadvisable is relied on simply, and domestic BDS still can not be covering the whole world, can not be that ocean is navigated During row offer pair.

(2) land would generally add one to multiple interchanger with failure wave-recording main frame between collecting unit and recording main frame, So doing mainly has three reasons：First, interchanger possesses the back bus and internal switch fabric of a very high bandwidth, each Port all can be considered the independent network segment, each enjoy overall network bandwidth, be advantageous to the raising of message capacity；Second, land power network It is in large scale, sampled point can reach hundreds of, it is necessary to collecting unit quantity it is relatively more, by interchanger to recording main frame pass Defeated bottom data can reduce the collection port number of recording main frame, simplify structure design；Three be due to land failure wave-recording main frame Using the external clock method of synchronization, collecting unit inside recording main frame from the master clock of clock and time service network with keeping Stringent synchronization, therefore need not consider to store Forwarding Latency as caused by interchanger, i.e. comprising standard in the message that collecting unit uploads The true synchronized sampling moment.

Although aforesaid way has many benefits, but be applied among ship failure wave-recording and the problem of certain be present.First, After a Lagrangian interpolation algorithm is incorporated into ship failure wave-recording main frame, interface when collecting unit just eliminates pair, Therefore sampling instant is not included in the message that it is uploaded.Obtained in the NTP messages that the temporal information of recording main frame is sent from central control desk Take, can stamp absolute timestamp after it receives the message of each interval upload, subtract collecting unit on this basis to recording The specified time delay of main frame is reducible real sampling instant.If still using switch mode transmission sampled data, by The limitation of recording main frame side bandwidth bearing capacity, the data that all collecting units are sent are deposited by having one during interchanger The process of forwarding is stored up, delay is larger and does not fix so that accurate sampling instant can not be extrapolated during interpolation synchronization. Secondly, once interchanger breaks down, then more collecting units being attached thereto will be unable to normal transmission data to recording main frame, Cause some power monitoring points even if occur it is abnormal also can not startup separator recording the problems such as.

Utility model content

The purpose of this utility model is to lack adaptation marine environment to solve current marine vessel power monitoring system The problem of failure wave-recording main frame.

The technical solution adopted in the utility model is：A kind of Ship Electrical Power System failure wave-recording main frame, including communication process Device, complicated programmable logic device, storage control, FLASH flash memories, the solid state hard disc for storing recorder data, programmable gate Array chip, ethernet transceiver, photoelectrical coupler, the UART Universal Asynchronous Receiver Transmitter of debugging function for realizing USB port FT232, DEBUG test chart, for the No.1 GBIC transceiver of data transfer and the transmitting-receiving of No. two GBICs Device；It is characterized in that：

The communication processor is connected by SATA buses with solid state hard disc, by No.1 spi bus and FLASH flash memories It is connected, is connected by No. two spi bus with storage control, by No.1 local bus LBC and complicated programmable logic device phase Even, it is connected by UART interface with photoelectrical coupler, by No.1 Serial Gigabit Media stand-alone interface SGMII and No.1 gigabit Position ethernet transceiver, by No. two Serial Gigabit Media stand-alone interface SGMII and No. two GBIC transceivers, lead to Management data input/output interface MDIO is crossed to receive and dispatch with No.1 GBIC transceiver and No. two GBICs simultaneously Device is connected, is connected by PCIe interface and No. two local bus LBC with programmable gate array chip；

The programmable gate array chip is connected by RMII interfaces with ethernet transceiver, on the ethernet transceiver Receive the sampled data SFP from different acquisition units provided with quantity being used for no less than two and gather port, each SFP collections Outside collecting unit is connected with port；UART Universal Asynchronous Receiver Transmitter FT232 is also connected with the photoelectrical coupler, it is described general different DEBUG test charts are also connected with step transceiver FT232；The No.1 GBIC transceiver passes through No.1 netting twine and one Number M12 COM1s are connected, and No. two GBIC transceivers pass through No. two netting twines and No. two M12 COM1 phases Even.

Further, the SFP collections port has two, respectively No.1 SFP collections port, No. two SFP collection terminals Mouthful；

Further, the communication processor uses the P1010 communication processors of Freescale companies.

Further, the Ship Electrical Power System failure wave-recording main frame also includes temperature sensor, and the communication processor leads to Iic bus is crossed with temperature sensor to be connected.

The beneficial effects of the utility model and feature are：1. realize record by the way of a Lagrangian interpolation resampling The synchronization of wave number evidence, the dependence to external clock reference is broken away from；2. contour structures are simple, size is small, in light weight, ship is especially suitable for The narrow and small cabin spaces of oceangoing ship are installed；3. multidiameter delay directly adopts pattern at a high speed, the real-time Transmission ability of network, recording are improved Precision is high.

Brief description of the drawings

Fig. 1 is the cut-away drawing of the utility model preferred embodiment；

Fig. 2 is the veneer distributed frame figure of Fig. 1 embodiments；

Fig. 3 is recording main frame SFP collection port circuit diagrams.

Fig. 4 is recording main frame M12 communication port circuit figures.

Fig. 5 is recording host-physical layer RMII interface circuit figures.

Fig. 6 is recording main frame and the direct-connected schematic diagram of collecting unit.

Fig. 7 is the synchronous resampling process of interpolation of Lagrange.

Fig. 8 is directly to adopt the time delay under pattern.

Fig. 9 is external clock Synchronos method.

Figure 10 is conventional switching Ethernet recorder data collection schematic diagram.

Label represents respectively in figure：1- communication processors, 2- complicated programmable logic devices, 3- storage controls, 4-FLASH Flash memory, 5- solid state hard discs, 6- programmable gate array chips, 7- ethernet transceivers, 8- No.1s SFP collections port, 9- bis- SFP collections port, 10- photoelectrical couplers, 11- UART Universal Asynchronous Receiver Transmitter FT232,12-DEBUG test chart, 13- TEMPs Device, 14- No.1 GBICs transceiver, 15- No.1 M12 COM1s, 16- No. bis- GBIC transceivers, 17- Collecting unit, the extra portion collecting units of 19- bis- outside No. two M12 COM1s, 18- No.1s.

Embodiment

The utility model is further described below in conjunction with the accompanying drawings：

As shown in figure 1, a kind of Ship Electrical Power System failure wave-recording main frame, including communication processor 1, complex programmable logic Device 2, storage control 3, FLASH flash memories 4, the solid state hard disc 5 for storing recorder data, programmable gate array chip 6, ether Net transceiver 7, photoelectrical coupler 10, UART Universal Asynchronous Receiver Transmitter FT23211, DEBUG of debugging function for realizing USB port Test chart 12, No.1 GBIC transceiver 14 and No. two GBIC transceivers 16 for data transfer；Its In：

The communication processor 1 is connected by SATA buses with solid state hard disc 5, by No.1 spi bus and FLASH flash memories 4 are connected, are connected by No. two spi bus with storage control 3, by No.1 local bus LBC and complicated programmable logic device 2 It is connected, is connected by UART interface with photoelectrical coupler 10, by No.1 Serial Gigabit Media stand-alone interface SGMII and one Number GBIC transceiver 14, pass through No. two Serial Gigabit Media stand-alone interface SGMII and No. two GBICs Transceiver 16, by manage data input/output interface MDIO simultaneously with No.1 GBIC transceiver 14 and No. two thousand Megabit ethernet transceiver 16 is connected, is connected by PCIe interface and No. two local bus LBC with programmable gate array chip 6；

The programmable gate array chip 6 is connected by RMII interfaces with ethernet transceiver 7, the ethernet transceiver 7 are provided with the sampled data SFP collection port that is used to receive from different acquisition units of the quantity no less than two, each SFP Collection is connected with outside collecting unit on port；UART Universal Asynchronous Receiver Transmitter FT23211, institute are also connected with the photoelectrical coupler 10 State and DEBUG test charts 12 are also connected with UART Universal Asynchronous Receiver Transmitter FT23211；The No.1 GBIC transceiver 14 is logical No.1 netting twine is crossed with No.1 M12 COM1s 15 to be connected, No. two GBIC transceivers 16 by No. two netting twines with No. two M12 COM1s 17 are connected.

In practice, the SFP collections port can set two, the SFP collections port of respectively No.1 SFP collections port 8, two 9；

The communication processor 1 is using the P1010 communication processors of Freescale companies, and the processor is in the low of 45nm On power consumption platform, 1.2GHz double-core frequency can be achieved, there is high power dissipation ratio of performance.

Recording main frame also includes temperature sensor 13, and the communication processor 1 passes through iic bus and the phase of temperature sensor 13 Even, the detection to environment temperature can be achieved.

Own characteristic and current demand of the utility model according to Ship Electrical Power System, are set to recording main frame Meter, below, mainly from hardware design, circuit design and performance indications it is several in terms of be introduced.

One, hardware designs

(1) outward appearance

Size：The long wide * of * high are about 223mm*300mm*177mm

Weight：Less than 6kg

Shell uses metal shell, is designed using closed dust, fan-free, natural heat dissipation, IP23 degree of protection.

Each interface board is identified according to industry standard, including interface board name, wire size etc..

Mounting means uses guide rail, and using guide rail truss, front panel is fixed.

(2) structure

As shown in Fig. 2 recording main frame uses veneer Distributed Design, including by master control borad, solid state hard disc plate and power supply Plate.It is independently installed between each daughter board, for overhaul, change and upgrading provide conveniently.

Recording main frame master control borad mainly forms hardware platform by CPU, FPGA etc..CPU is from Freescale companies P1010 communication processors, on 45nm low-power consumption platform, 1.2GHz double-core frequency can be achieved, there is high performance work( Loss-rate.32 DDR3 storage controls support self-correcting code, ensure that the high reliability of system.Spi bus, SATA buses, Iic bus etc. additionally provides the branch to peripheral hardwares such as FLASH flash memories, SSD solid state hard discs, eeprom memory, temperature sensors Hold, UART interface then coordinates the debugging function for realizing USB port with UART Universal Asynchronous Receiver Transmitter FT232.In addition, P1010 mailing addresses A whole set of interface being integrated with reason device including 16 local bus LBC, PCIe buses etc., realize management control plane Big data exchanges.What FPGA was used is equally the EP4CGX50 devices of altera corp, be will not be repeated here.When recording main frame is sent out When raw abnormal, system reducing can be carried out by 5M570 CPLDs.

As shown in figure 3, separate unit recording main frame is configured with SFP collections port, traffic rate can reach 100,000,000, main to be responsible for Receive the sampled data from different acquisition units, it is internal then by physical chip 88E3082 and FPGA interaction datas, adopt After the lightwave signal that collection unit is sent is sent to SFP Optical Receivers, differential logic level PHY0_SIP/N is converted to, through reduction 88E3082 P0_RXP/N pins are accessed after the appropriate correction of circuit.PHY0_SCL and PHY0_SDA is respectively what FPGA was sent Clock signal and command signal, be mainly used to control read SFP chips in relevant information.

As shown in figure 4, in order to realize the data transfer with central control desk, every recording main frame is furnished with two M12 communication ends Mouthful, one is online, and one is standby.Physical layer selects GBIC transceiver 88E1512, support 1000BASE-T, The ethernet type such as 100BASE-TX, 100BASE-FX and 10base-T, and it is more kinds high to provide RGMII, SGMII, SERDES Fast transceiver interface.In order to meet the communication bandwidth requirement between recording main frame and central control desk, the utility model is using serial lucky ratio Special GMII SGMII realizes the data interaction between transceiver 88E1512 and processor P1010, and transmission rate can To reach 1.25G.88E1512 chips are connected with M12 ports by network isolation transformer 11FB-05NL, are utilizing electromagnetism coupling , can effectively clutter reduction signal, and the difference isolated between recording main frame and interchanger while differential signal transmission is realized in conjunction Level, prevent device damage caused by high voltage.

Because the memory capacity that recorder data needs is big, so recording main frame is configured with two blocks of hard disk plates, every block of hard disk plate Two 512G solid state hard disc is installed, maximum storage capacity can reach 2T.In addition, multiple LED instructions are also equipped with panel Lamp, it is respectively " power supply ", " RUN ", " failure ", " storage ", " pair when " and " standby ".

100~250V of input AC or DC voltage conversion is the 5V DC quantities for being available for daughter board to use by power panel Output, line regulation are no more than 0.5%.Inside uses overvoltage, overcurrent and short-circuit protection mechanism, when there is load abnormal Or can be cut off the electricity supply in time during electric voltage exception, pending fault can voluntarily recover after removing.

2nd, circuit design

The analysis circuit for being installed on central control desk is divided into on-line monitoring analysis and off-line analysis two parts.On-line monitoring point Analysing module can be shown the real time data that recording main frame uploads by patterned mode, amplitude, the phase of power system The information such as position, frequency, power, harmonic wave can accomplish tracking and monitoring, and alarm signal is sent immediately once noting abnormalities.Meanwhile The relevant parameter of recording main frame can also be configured, including increase and decrease recording unit, modification distribution parameter, extraction sampling channel, Adjust the recording period, start-up criterion is adjusted, digital ＆ analog signal controls, changes user right etc..Off-line analysis module will can store File in recording main frame is extracted, and is converted into the COMTRADE forms of standard, and phasor point is carried out to power system Analysis, sequence component analysis, frequency analysis etc., and print fault waveform can be required according to sampling channel or period etc..

3rd, performance indications

(1) electricity species is recorded

The situation of change of the analog quantity such as the voltage of overall process, electric current and relay protection, breaker etc. before and after recordable failure The action situation of switching value.

(2) Starting mode

Alternating voltage：Phase voltage mutation startup, the out-of-limit startup of phase voltage, the out-of-limit startup of positive sequence voltage, negative sequence voltage are out-of-limit

Start, the out-of-limit startup of harmonic voltage.

Alternating current：Phase current mutation startup, the out-of-limit startup of phase current, the out-of-limit startup of negative-sequence current.

Frequency：The high out-of-limit startup of frequency, the low out-of-limit startup of frequency.

Direct current：Sudden Changing Rate startup, high out-of-limit startup and low out-of-limit startup.

Switching value：ON → OFF starts, OFF → ON starts.

(3) message accounting

Recorded using original message plus real-time evaluation of markers mode, real-time evaluation of markers receives the micro- of message including device Second level markers and the result to the real-time analysis of message.The message generated in recording main frame can by analysis circuit conversion into Csv forms or GB/T 22386-2008 countries newest standards COMTRADE forms readable Excel.

(4) transient state recorder data recording mode

The failure wave-recording of early stage at times, does not keep constant, shortcoming is if sampling from recording termination sample rate is started to Rate is relatively low, is not enough to the transient process at accurate reproduction disturbance moment, if sample rate is too high and can increase before failure occurs and steady The data volume recorded after fixed.Therefore,《220~500kV electric power system fault dynamically recording technical criterias》By recording it is each when Section is divided into five periods of A, B, C, D, E.

During A segment record be system jam before data, length can (>=0.04s) more than 2 cycles.B Period is then transitioned into abnormality, record be failure early period of origination Temporal Data, it is desirable to length more than 10 cycles (>= 0.1s).From Nyquist theorems, sample frequency cannot be below 2 times of primary signal highest frequency component, and otherwise modulus turns The phenomenon of frequency alias can be produced after changing.But this is minimum requirements, want to analyze harmonic components, sample frequency is general Reach 5~10 times of signal highest frequency.Therefore the sampling rate of AB periods is higher, and export for original record ripple Shape.The C periods are that mid-term occurs for failure, and the recording time in more than 1.0s, is changed to virtual value storage.The D periods are that the later stage occurs for failure Dynamic process, the duration is slightly long (>=20s), and an effective value is exported per 0.1s.Segment record is system length during E Process dynamics data, the time is most long (>=10min), and an effective value is exported every 1s.C, D, E are that system is gradually recovered The process of stable state, sample rate from high to low, duration extension.

Table 1 adjusts the recording period

On the basis of above-mentioned standard, with reference to actual use demand, the utility model is done to the control parameter of recording period Certain adjustment, is shown in Table 1.A, segment record is abnormal process occurs for power system during B, and the sampling time is short, sample frequency Height, segment record is process that system recovers stable state during C, sampling time length, and sample frequency is low.It is arranged such and both can guarantee that in detail Record failure and front and rear transient process occurs, the memory space of recorded wave file occupancy can be saved again, and improve real time data Uploading speed.Meanwhile A, B, C section are recorded using virtual value, the analyticity of later data is improved.

(5) way of self-regulation

Online modification：During device on-line operation, operation definite value and parameter can be directly changed.

Teletransmission is changed：Upper management department can be changed by teletransmission.

(6) interface

Acquisition interface：RG45 interface phases used by using SFP fiber optic Ethernet interfaces, with conventional fault recording main frame Than the connection of SFP modules and medium is relatively reliable, the generation of port obscission caused by can effectively avoiding ship hull vibration.This Outside, SFP also has the advantages that compact-sized, power consumption is relatively low, supports hot plug, can be effectively saved cabinet space, reduction dissipates Heat, convenient replacement.Communication media selects flexible metal armouring multimode fibre line, and a helical layer shape stainless steel is wrapped in optical fiber periphery Material, on the premise of optical property is not influenceed, the protection for solving conventional fiber lateral pressure resistant, shock resistance and mouse bite preventing is asked Topic, to ensure the unimpeded of communication network.

Upload interface：RJ45 connectors are turned as the communication interface between recording main frame and Upper Switch using M12, its The locking mechanism of screw means formula can ensure to be reliably connected between plug and socket, patch place classification of waterproof IP ＞ 67, normally The temperature range of work can effectively reduce electromagnetic radiation and interference, transmission rate between -25 DEG C to 85 DEG C, from shielded cable 100Mbit/s can be reached.

Power interface：Input wires terminal uses aviation plug.

(7) communication protocol supported

PTP protocol, Network Time Protocol.

IEC 61850-9-2 standards.

IEEE802.1p agreements, ICP/IP protocol.

Proprietary protocol.

(8) operating ambient temperature

Operating ambient temperature：- 20 DEG C~+70 DEG C.

Accumulating environment temperature：- 20 DEG C~+70 DEG C, energizing quantity is not added with limiting value, device occurs without irreversible change, Device should be able to normal work after temperature is recovered.

Relative humidity：5%~95% (no condensation).

Atmospheric pressure：80kPa~110kPa.

As shown in figure 5, the utility model is from RMII RMII transmission Ethernet bags.Pass through MII interfaces Achievable multidiameter delay rapidly inputs output, and the data that each collecting unit uploads need not be waited in line, and be directly transferred to FPGA, And reception and the transmission timing of MII interfaces are controlled by FPGA, the transmission rate of data is substantially increased, so as to ensure that interpolation is same The accuracy for the temporal information that recorded wave file records under the conditions of step.

As shown in figs. 6-9, the synchronous core concept of interpolation is to be sampled using original function f (t) in some time interval Several obtained adjacent functional values, estimate adopting for other any times in the section by selecting appropriate fitting function Sample value.For separate unit collecting unit, electric current, the voltage signal of each passage are to carry out A/D according to identical sampling instant to turn Change, it is achieved thereby that the data syn-chronization in interval.But for different collecting units, although sample frequency can protect Hold unanimously, but corresponding time reference, there may be dislocation, this just needs recording main frame to carry out weight to the sampled data across interval Sampling, wherein relating to the synchronous processing of interpolation.Recording main frame therefrom parses after the message of collecting unit upload is received The information such as sampling sequence number, sampled value, time delay, using the time of reception subtract specified delay i.e. reducible actual sampling when Carve.Then, the internal clocking frequency dividing of recording main frame produces resampling pulse signal, according to resampling moment and front and rear several references Functional relation between moment, carry out interpolation arithmetic and can be obtained by one " synchronized sampling value ".According to fixed time interval Resampling point is not had no progeny shifting, finally gives a new sample sequence.

Without Ethernet switch between collecting unit and recording main frame, but data are carried out in a manner of fiber direct connection The transmission of report, each pair optical fiber are only responsible for the running state monitoring in the sampling interval, reduce the dependence to intermediate link, conflict The increase being effectively isolated with network bandwidth in domain also improves the real-time Transmission ability and signal synchronization accuracy of network.

Because interpolation algorithm needs to use the sampled value of several adjacent time points, it requires collecting unit according to identical Time interval uploads data, and the error of interpolation result and actual value otherwise can be caused excessive.In order to reduce transmission delay to data Synchronous influence, the transmission plan that the utility model is directly adopted at a high speed using multidiameter delay：1. collecting unit and recording main frame are not Need to access external clock synchronizing network；2. different collecting units is according to respective internal clocking, with fixed sample frequency (settable) transmission sample values；3. collecting unit is joined directly together by optical fiber and recording main frame, sampled value is no longer pass through handing over Exchange device transmits.

In this scenario, in order to ensure that the sampled data of the different interval before interpolation synchronization has reached recording main frame, Synchronization point needs to lag the regular hour, and the time delay includes the later LPF of analog signal access collecting unit and prolonged Late, transmission delay and recording main frame extraction message of the sampling delay, sampled data in A/D transfer processes in optical-fibre channel Decoding delay.Because optical signal has high transmission rate, and the transmission range between collecting unit and recording main frame Limited (most long 100 meters or so), therefore transmission delay of the sampled data in optical-fibre channel is almost nil, can be neglected.Always The size of time delay can be obtained by measurement, and be added in sampling value message and be transferred to recording main frame, and recording main frame is according to report The reception time and delayed data of text can extrapolate the actual sampling time.

Assuming that recording main frame receives the message data at two neighbouring sample intervals that same outside collecting unit is sent, And obtain two discrete points [tk, i (tk)] and [tk+1, i (tk of some current channel by decoding extraction and time complexity curve +1)].The current value that can be obtained corresponding to synchronization point t using a Lagrangian interpolation algorithm is calculated as follows：

As actual value i (t) approximation, the error of a Lagrangian interpolation is

In formula, i " (ξ) is i (t) second dervative, and ξ is section [t_k,t_k+1] in sometime.

Because the current value of Ship Electrical Power System can be expressed as the superposition of DC component, fundamental wave and each harmonic, such as formula 3 It is shown

Wherein, I₀For DC component, n is overtone order (fundamental wave is represented during n=1), I_n、Fundamental wave and each time are represented respectively The amplitude and initial phase angle of harmonic wave, ω are fundamental frequency angular frequency.I (t) expression formula, which is brought into formula 2, to be obtained

Assuming that the working frequency of power system is 50Hz, then the π f=100 π of fundamental frequency angular frequency=2, and sampling interval t_k+1- t_k=0.02/N, N are the sampling number per cycle.Because the absolute value in formula 4 is in t=(t_k+1+t_kMaximum is obtained at)/2, So the worst error of a Lagrangian interpolation is

By observing R_maxExpression formula can be derived that as drawn a conclusion：

①R_maxDC component of the size not in by ource electric current influenceed, that is to say, that Lagrange is done to constant-direct current One time interpolation will not bring measurement error.

2. although recording main frame can carry out the process of a resampling to the message data from different interval, adopt again Sample frequency f_sR will not be caused_maxChange.

③R_maxThe linear superposition of fundamental wave and each harmonic can be expressed as, in the case where N values are constant, overtone order is got over Height is bigger to the contribution rate of error.

4. sampling number of the collecting unit per cycle is more, i.e. N values are bigger, R_maxIt is smaller, therefore can be sampled by increasing The mode of frequency reduces the error of a Lagrangian interpolation.

Recording main frame decides whether startup recording behavior according to corresponding criterion, and the starting algorithm being related to mainly includes Sudden Changing Rate starting algorithm, harmonic wave starting algorithm, sequence amount starting algorithm, frequency starting algorithm etc..Once more than the limit value adjusted, record Ripple main frame just carries out the storage of fault message according to the recording sequential being mentioned above.

Because the utility model is synchronized using interpolation algorithm, sampling instant is calculated to obtain by recording main frame, therefore should Cut down the number of intermediate links as far as possible the uncertain delay brought.Except eliminated between collecting unit and recording main frame interchanger it Outside, the utility model is also improved the bottom data incoming end of recording main frame.Land failure wave-recording main frame generally use The sampled data that conventional exchange chip processing uploads from different acquisition units, i.e., multiple corresponding outputs of input channel are logical Road, thus communication delay be present.For the above situation, the physical layer (PHY) of the utility model device has selected Marvell companies 8 port Fast Ethernet transceiver 88E3082 chips of the third generation of production based on DSP, the chip are supported under IEEE802 standards 10base-T, 100BASE-T Double-strand transmissions pattern and 100BASE-FX optical fiber transmission modes, full duplex and half pair can be achieved Work communicates.Meanwhile a variety of Media Independent Interfaces of 88E3082 integrated chips, in order to reduce 88E3082 and EP4CGX50 I/O Pin number,

(multiple white box of bottom are outside collecting unit in Figure 10, and black box is recording main frame) as shown in Figure 10, land One to multiple interchanger would generally be added between collecting unit and recording main frame with failure wave-recording main frame, so doing mainly has three Individual reason：First, interchanger possesses the back bus and internal switch fabric of a very high bandwidth, each port can be considered only The vertical network segment, overall network bandwidth is each enjoyed, be advantageous to the raising of message capacity；Second, land electricity consumption net is in large scale, sampling Point can reach hundreds of, it is necessary to collecting unit quantity it is relatively more, by interchanger to recording main frame transmission bottom data can The collection port number of recording main frame is reduced, simplifies structure design；Three be due to land failure wave-recording main frame using outside Clock synchronization mode, collecting unit keep stringent synchronization with the master clock from clock and time service network inside recording main frame, because This need not consider to store Forwarding Latency as caused by interchanger, and accurate synchronized sampling is included in the message that collecting unit uploads Moment.

Its technical advantage is：

(1) a Lagrangian interpolation synchronization.External clock Synchronos method is that current land is generally used with failure wave-recording main frame Method for synchronizing time, due to when which exists pair under marine condition signal be difficult to obtain, pair when signal be easily disturbed, together The step complicated network structure, there is the problems such as potential potential safety hazard, therefore the utility model is adopted again using a Lagrangian interpolation The mode of sample realizes the synchronization of recorder data.Recorder data synchronization can be achieved by circuit for which, when having broken away to outside Zhong Yuan dependence, and do not need clock server, pair when the interface and punctual crystal oscillator of high accuracy, simplify network structure, save Cost, has adapted to marine severe working environment.

(2) multidiameter delay directly adopts pattern (such as Fig. 6) at a high speed, without interchanger between collecting unit and recording main frame, and It is the transmission that datagram is carried out in a manner of fiber direct connection, each pair optical fiber is only responsible for the running state monitoring in the sampling interval, from And storage Forwarding Latency problem caused by the possibility and interchanger that the message data for avoiding different interval collides, improve The real-time Transmission ability of network.Meanwhile every optical fiber only carries out one-way data transfer, in the absence of sender and recipient simultaneously The problem of fighting for same channel.Recording host-physical layer uses RMII Interface designs, is opened from inside by each SFP port isolations Come so that the data that different acquisition units are sent to recording main frame are not interfere with each other, and achievable multidiameter delay rapidly inputs output, is The application of interpolation algorithm creates condition.

The advantages of general principle and principal character of the present utility model and the utility model has been shown and described above.One's own profession The technical staff of industry is it should be appreciated that the utility model is not restricted to the described embodiments, described in above-described embodiment and specification Simply illustrate structural relation and principle of the present utility model, on the premise of the spirit and scope of the utility model is not departed from, this Utility model also has various changes and modifications, and these changes and improvements are both fallen within claimed the scope of the utility model. The utility model requires protection scope is by appended claims and its equivalent thereof.

Claims (4)

1. a kind of Ship Electrical Power System failure wave-recording main frame, including communication processor (1), complicated programmable logic device (2), storage Controller (3), FLASH flash memories (4), the solid state hard disc (5) for storing recorder data, programmable gate array chip (6), ether Net transceiver (7), photoelectrical coupler (10), the UART Universal Asynchronous Receiver Transmitter FT232 of debugging function for realizing USB port (11), DEBUG test charts (12), No.1 GBIC transceiver (14) and No. two kilomegabit ether for data transfer Net transceiver (16)；It is characterized in that：

The communication processor (1) is connected by SATA buses with solid state hard disc (5), by No.1 spi bus and FLASH flash memories (4) it is connected, is connected by No. two spi bus with storage control (3), is patrolled by No.1 local bus LBC and complex programmable Device (2) is collected to be connected, by UART interface with photoelectrical coupler (10) be connected, by No.1 Serial Gigabit Media stand-alone interface SGMII and No.1 GBIC transceiver (14), pass through No. two Serial Gigabit Media stand-alone interface SGMII and No. two thousand Megabit ethernet transceiver (16), by manage data input/output interface MDIO simultaneously with No.1 GBIC transceiver (14) it is connected with No. two GBIC transceivers (16), passes through PCIe interface and No. two local bus LBC and programmable gate Array chip (6) is connected；

The programmable gate array chip (6) is connected by RMII interfaces with ethernet transceiver (7), the ethernet transceiver (7) the sampled data SFP collection port that is used to receive from different acquisition units of the quantity no less than two is provided with, each SFP collections are connected with outside collecting unit on port；UART Universal Asynchronous Receiver Transmitter FT232 is also connected with the photoelectrical coupler (10) (11) DEBUG test charts (12) also, are connected with the UART Universal Asynchronous Receiver Transmitter FT232 (11)；The No.1 GBIC Transceiver (14) is connected by No.1 netting twine with No.1 M12 COM1s (15), No. two GBIC transceivers (16) it is connected by No. two netting twines with No. two M12 COM1s (17).

2. Ship Electrical Power System failure wave-recording main frame according to claim 1, it is characterised in that：The SFP gathers port There are two, respectively No.1 SFP collections port (8), No. two SFP collections port (9).

3. Ship Electrical Power System failure wave-recording main frame according to claim 1, it is characterised in that：The communication processor (1) the P1010 communication processors of Freescale companies are used.

4. the Ship Electrical Power System failure wave-recording main frame according to claims 1 to 3 any claim, it is characterised in that： Also include temperature sensor (13), the communication processor (1) is connected by iic bus with temperature sensor (13).