CN104865824A

CN104865824A - Beidou B-code timing synchronization device based on PCI-E bus

Info

Publication number: CN104865824A
Application number: CN201510212153.7A
Authority: CN
Inventors: 王军; 张福第; 孙兆友; 杜博军; 唐彬; 王磊
Original assignee: Suzhou University of Science and Technology
Current assignee: Suzhou University of Science and Technology
Priority date: 2015-04-30
Filing date: 2015-04-30
Publication date: 2015-08-26

Abstract

The invention provides a Beidou B-code timing synchronization device based on PCI-E bus, which comprises the components of a Beidou receiving module, an FPGA programmable logic device, a PCI-E interface and a computer. The Beidou receiving module is connected with the FPGA programmable logic device and transmits GPRMC positioning information to the FPGA programmable logic device. The FPGA programmable logic device is connected with the computer through the PCI-E interface. An RAM memory is simulated in the FPGA programmable logic device. Corresponding time zone time which is demodulated by the FPGA programmable logic device is stored in the simulated RAM memory. Furthermore the PCI-E interface is triggered through a corresponding triggering time for halting reading to the time zone time in the RAM memory to the computer. The Beidou B-code timing synchronization device is provided with the Beidou receiving module and has high safety. The number of PCI-E buses is smaller than that of the PCI pins. The Beidou B-code timing synchronization device further has advantages of simple wiring on a board, effective bandwidth increase, effective transmission efficiency improvement, and flexible expandability.

Description

A kind of Big Dipper B code time service synchronous device of Based PC I-E bus

Technical field

The invention belongs to Service of Timing field, be specifically related to a kind ofly utilize Beidou navigation satellite reception standard satellite temporal information and the time synchronism apparatus of B code time service is provided to computing machine by PCI-E bus interface.

Background technology

Time, have a wide range of applications in social every field, wherein satellite navigation, electric power synchronous sampling system often had very high requirement to the precision of time as a basic physical reference amount of the motion of matter.Traditional time service mode adopts gps satellite navigation to provide standard time code information, solves temporal information and be sent to computer host computer by Asynchronous Serial Interface by embedded scm.Although the weak point of this time service mode is that GPS navigation satellite precision is high, but its system is single, reliability is not high, also there is licensing issue, if can not get authorizing the situation that there will be part system paralysis, and adopt Asynchronous Serial Interface to be connected with computer, interface is loaded down with trivial details, cannot with computer integrated.

The prior art the most close with patent of the present invention is that the Liu Junliang of National Time Service Center, Chinese Academy of Sciences equals 2009 the whole nation observing and controlling of the 19 boundary, metering, " the GPS time service card based on pci bus designs " that instrument and meter Annual Conference proposes, its technical scheme as shown in Figure 1: comprise MPU microprocessing unit 1, dual-ported memory 2, pci interface 3, computing machine 4, GPS receiver module 5, frequency multiplication of phase locked loop module 6, CPLD programming device 7.GPS receiver module 5 output time signal is delivered to MPU microprocessing unit 1 by serial ports and is carried out temporal information process, the 10KPPS signal simultaneously produced enters frequency multiplication of phase locked loop module 6, module 6 is responsible for the rising edge of 10KPPS signal with GPS pps pulse per second signal constantly to align, and exports the clock source of 20MPPS signal as CPLD programming device 7.The signal receiving that GPS receiver module 5 receives is become the UTC time and the Beijing time of being converted into by MPU microprocessing unit 1, by Beijing time information transmission to dual-ported memory 2, computing machine 4 can read the Beijing Today time by pci interface 3 at any time.

This technology Problems existing is: the authorizing secure problem not solving GPS; And pci bus needs to draw a large amount of pin from chipset, cause mainboard wiring difficulty to increase, its narrow bandwidth and transmission speed are slowly compared with PCI-E, make computing machine eliminate pci bus slot gradually.

Summary of the invention

The object of the invention is to overcome prior art Problems existing, a kind of Big Dipper B code time service synchronous device of Based PC I-E bus is provided.

For realizing above-mentioned technical purpose, reach above-mentioned technique effect, the present invention is achieved through the following technical solutions:

A kind of Big Dipper B code time service synchronous device of Based PC I-E bus, this device comprises Big Dipper receiver module, FPGA programmable logic device, PCI-E interface and computing machine, described Big Dipper receiver module connects and transmits GPRMC locating information to FPGA programmable logic device, described FPGA programmable logic device connects computing machine by PCI-E interface, a RAM storer is fictionalized in described FPGA programmable logic device, the corresponding time zone time that FPGA programmable logic device demodulates is stored in this virtual RAM storer, and by the time zone time in corresponding this RAM storer of trigger pip triggering PCI-E interface interruption reading to computing machine.

Further, described FPGA programmable logic device comprises interconnective satellite time decoder module and main control module, described main control module fictionalizes a RAM module, described satellite time decoder module reception GPRMC locating information, solves the UTC time and the Beijing time of being converted into writes in RAM module; Described PCI-E interface comprises PCI-E interface chip, PCI-E bus and config memory, described PCI-E bus connects PCI-E interface chip, described PCI-E interface chip connects config memory, described main control module connects PCI-E interface chip, the PPS trigger pip that sends main control module triggers PCI-E interface chip and enters interrupt routine, and described PCI-E interface chip reads the Beijing time information pass to computing machine by PCI-E bus inside RAM module by address data signal path.

Further, described Big Dipper receiver module adopts N303 Big Dipper module.

Further, described FPGA programmable logic device adopts EP2C5T144C8N chip.

Further, described PCI-E interface chip adopts CH368 chip.

The invention has the beneficial effects as follows:

The present invention adopts big-dipper satellite receiver module, and security is high, and PCI-E bus is fewer than PCI pin, and plank wiring is simple and easy, and bandwidth increases, and transfer rate improves, and has extendability flexibly.

Accompanying drawing explanation

Fig. 1 is the structural schematic block diagram of prior art;

Fig. 2 is structural schematic block diagram of the present invention;

Fig. 3 is FPGA programmable logic device inner structure schematic block diagram in Fig. 2;

Fig. 4 is the structural schematic block diagram of PCI-E interface 10 in Fig. 2;

Fig. 5 is FPGA programmable logic device and PCI-E interface inner connecting structure block diagram.

Number in the figure illustrates: 1, MPU microprocessing unit, 2, dual-ported memory, 3, pci interface, 4, computing machine, 5, GPS receiver module, 6, frequency multiplication of phase locked loop module, 7, CPLD programming device, 8, Big Dipper receiver module, 9, FPGA programmable logic device, 10, PCI-E interface, 11, computing machine, 12, GPRMC locating information, 13, satellite time decoder module, 14, RAM module, 15, main control module, 16, address data signal path, 17, PPS trigger pip, 18, PCI-E interface chip, 19, PCI-E bus, 20, config memory.

Embodiment

Below with reference to the accompanying drawings and in conjunction with the embodiments, describe the present invention in detail.

With reference to shown in Fig. 2, a kind of Big Dipper B code time service synchronous device of Based PC I-E bus, this device comprises Big Dipper receiver module 8, FPGA programmable logic device 9, PCI-E interface 10 and computing machine 11, described Big Dipper receiver module 8 connects and transmits GPRMC locating information 12 to FPGA programmable logic device 9, described FPGA programmable logic device 9 connects computing machine 11 by PCI-E interface 10, a RAM storer is fictionalized in described FPGA programmable logic device 9, the corresponding time zone time that FPGA programmable logic device 9 demodulates is stored in this virtual RAM storer, and by the time zone time in corresponding this RAM storer of trigger pip triggering PCI-E interface 10 interruption reading to computing machine 11.

With reference to shown in Fig. 3, described FPGA programmable logic device 9 comprises interconnective satellite time decoder module 13 and main control module 15, described main control module 15 fictionalizes a RAM module 14, described satellite time decoder module 13 receives GPRMC locating information 12, solves the UTC time and in the Beijing time of being converted into write RAM module 14;

With reference to shown in Fig. 4, described PCI-E interface 10 comprises PCI-E interface chip 18, PCI-E bus 19 and config memory 20, described PCI-E bus 19 connects PCI-E interface chip 18, described PCI-E interface chip 18 connects config memory 20, when just powering on, PCI-E interface chip 18 reads the configuration information inside config memory 20, main control module 15 connects PCI-E interface chip 18, the PPS trigger pip 17 that sends main control module 15 triggers PCI-E interface chip 18 and enters interrupt routine, PCI-E interface chip 18 reads the Beijing time information pass to computing machine 11 by PCI-E bus 19 inside RAM module 14 by address data signal path 16.

Described Big Dipper receiver module 8 adopts N303 Big Dipper module.

Described FPGA programmable logic device 9 adopts EP2C5T144C8N chip.

Described PCI-E interface chip 18 adopts CH368 chip.

The principle of the invention: Big Dipper receiver module 8 receives satellite-signal and GPRMC locating information 12 is sent to FPGA programmable logic device 9, FPGA programmable logic device 9 inside solves the UTC time and becomes and be converted to Beijing time and trigger PCI-E interface chip 18 stored in the PPS trigger pip 17 that RAM module 14, FPGA programmable logic device 9 produces and interrupt reading Beijing time in RAM module 14 to computing machine 11.

The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. the Big Dipper B code time service synchronous device of a Based PC I-E bus, it is characterized in that, this device comprises Big Dipper receiver module (8), FPGA programmable logic device (9), PCI-E interface (10) and computing machine (11), described Big Dipper receiver module (8) connects and transmits GPRMC locating information (12) to FPGA programmable logic device (9), described FPGA programmable logic device (9) connects computing machine (11) by PCI-E interface (10), a RAM storer is fictionalized in described FPGA programmable logic device (9), the corresponding time zone time that FPGA programmable logic device (9) demodulates is stored in this virtual RAM storer, and by the time zone time in corresponding this RAM storer of trigger pip triggering PCI-E interface (10) interruption reading to computing machine (11).

2. the Big Dipper B code time service synchronous device of Based PC I-E bus according to claim 1, it is characterized in that, described FPGA programmable logic device (9) comprises interconnective satellite time decoder module (13) and main control module (15), described main control module (15) fictionalizes a RAM module (14), described satellite time decoder module (13) reception GPRMC locating information (12), solves the UTC time and the Beijing time of being converted into writes in RAM module (14);

Described PCI-E interface (10) comprises PCI-E interface chip (18), PCI-E bus (19) and config memory (20), described PCI-E bus (19) connects PCI-E interface chip (18), described PCI-E interface chip (18) connects config memory (20), described main control module (15) connects PCI-E interface chip (18), main control module (15) sends PPS trigger pip (17) triggering PCI-E interface chip (18) and enters interrupt routine, the Beijing time information that described PCI-E interface chip (18) reads RAM module (14) the inside by address data signal path (16) also passes to computing machine (11) by PCI-E bus (19).

3. the Big Dipper B code time service synchronous device of Based PC I-E bus according to claim 1, is characterized in that, described Big Dipper receiver module (8) adopts N303 Big Dipper module.

4. the Big Dipper B code time service synchronous device of Based PC I-E bus according to claim 2, is characterized in that, described FPGA programmable logic device (9) adopts EP2C5T144C8N chip.

5. the Big Dipper B code time service synchronous device of Based PC I-E bus according to claim 2, is characterized in that, described PCI-E interface chip (18) adopts CH368 chip.