CN104865824A - Beidou B-code timing synchronization device based on PCI-E bus - Google Patents

Abstract

The invention provides a Beidou B-code timing synchronization device based on PCI-E bus, which comprises the components of a Beidou receiving module, an FPGA programmable logic device, a PCI-E interface and a computer. The Beidou receiving module is connected with the FPGA programmable logic device and transmits GPRMC positioning information to the FPGA programmable logic device. The FPGA programmable logic device is connected with the computer through the PCI-E interface. An RAM memory is simulated in the FPGA programmable logic device. Corresponding time zone time which is demodulated by the FPGA programmable logic device is stored in the simulated RAM memory. Furthermore the PCI-E interface is triggered through a corresponding triggering time for halting reading to the time zone time in the RAM memory to the computer. The Beidou B-code timing synchronization device is provided with the Beidou receiving module and has high safety. The number of PCI-E buses is smaller than that of the PCI pins. The Beidou B-code timing synchronization device further has advantages of simple wiring on a board, effective bandwidth increase, effective transmission efficiency improvement, and flexible expandability.

Description

A Beidou B code timing synchronization device based on PCI-E bus

technical field

The invention belongs to the technical field of time service, and in particular relates to a time synchronization device which utilizes Beidou navigation satellites to receive standard satellite time information and provides B code time service to a computer through a PCI-E bus interface.

Background technique

As a basic physical reference quantity for material movement, time is widely used in various fields of society. Among them, satellite navigation and power synchronous sampling systems often have high requirements for time accuracy. The traditional time service method is to use GPS satellite navigation to provide standard time code information, decode the time information through the embedded single-chip microcomputer and send it to the computer host computer through the asynchronous serial interface. The disadvantage of this timing method is that although the GPS navigation satellite has high precision, its system is single, the reliability is not high, and there are authorization problems. If the authorization is not obtained, some systems will be paralyzed, and the asynchronous serial interface and The computer is connected, the interface is cumbersome, and it cannot be integrated with the computer.

The existing technology closest to the patent of the present invention is the "GPS timing card design based on PCI bus" proposed by Liu Junliang of the National Time Service Center of the Chinese Academy of Sciences in 2009 at the 19th National Annual Conference on Measurement, Control, Measurement, and Instrumentation. Its technical scheme is shown in Figure 1: including MPU microprocessing unit 1, dual-port memory 2, PCI interface 3, computer 4, GPS receiving module 5, phase-locked loop frequency multiplier module 6, CPLD programmable device 7. The GPS receiving module 5 outputs the time signal to the MPU micro-processing unit 1 through the serial port for time information processing, and the 10KPPS signal generated at the same time enters the phase-locked loop frequency multiplication module 6, and the module 6 is responsible for continuously combining the 10KPPS signal with the rising edge of the GPS second pulse signal. The alignment, and output 20MPPS signal as the clock source of CPLD programmable device 7. The MPU micro-processing unit 1 demodulates the signal received by the GPS receiving module 5 into UTC time and converts it into Beijing time, and transmits the Beijing time information to the dual-port memory 2, and the computer 4 can read the current Beijing time through the PCI interface 3 at any time.

The problems of this technology are: it does not solve the security problem of GPS authorization; and the PCI bus needs to lead out a large number of pins from the chipset, which makes the wiring of the motherboard more difficult. Compared with PCI-E, its bandwidth is narrow and the transmission speed is slow. The computer gradually eliminates the PCI bus slot.

Contents of the invention

The purpose of the present invention is to overcome the problems existing in the prior art, and to provide a Beidou B-code timing synchronization device based on the PCI-E bus.

In order to achieve the above-mentioned technical purpose and achieve the above-mentioned technical effect, the present invention is realized through the following technical solutions:

A kind of Beidou B code time service synchronization device based on PCI-E bus, this device comprises Beidou receiving module, FPGA programmable logic device, PCI-E interface and computer, described Beidou receiving module is connected and transmits GPRMC to FPGA programmable logic device Positioning information, the FPGA programmable logic device is connected to the computer through the PCI-E interface, a RAM memory is virtualized in the FPGA programmable logic device, and the corresponding time zone time demodulated by the FPGA programmable logic device is stored in this virtual RAM In the memory, and trigger the PCI-E interface interrupt through the corresponding trigger signal to read the time zone time in the RAM memory to the computer.

Further, the FPGA programmable logic device includes a satellite time decoding module and a main control module connected to each other, and a dual-port RAM memory module is virtualized by the main control module, and the satellite time decoding module receives GPRMC positioning information, and solves UTC time is also converted into Beijing time and written in the dual-port RAM memory module; the PCI-E interface includes a PCI-E interface chip, a PCI-E bus and a configuration memory, and the PCI-E bus is connected to the PCI-E interface chip, The PCI-E interface chip is connected to the configuration memory, the main control module is connected to the PCI-E interface chip, the main control module sends a PPS trigger signal to trigger the PCI-E interface chip to enter the interrupt program, and the PCI-E interface chip passes the address data The signal path reads the Beijing time information in the dual-port RAM memory module and transmits it to the computer through the PCI-E bus.

Further, the Beidou receiving module adopts the N303 Beidou module.

Further, the FPGA programmable logic device adopts EP2C5T144C8N chip.

Further, the PCI-E interface chip adopts CH368 chip.

The beneficial effects of the present invention are:

The invention adopts the Beidou satellite receiving module, which has high safety, the PCI-E bus has fewer pins than the PCI, the board wiring is simple, the bandwidth is increased, the transmission rate is improved, and it has flexible scalability.

Description of drawings

Fig. 1 is a structural schematic block diagram of the prior art;

Fig. 2 is a structural schematic block diagram of the present invention;

Fig. 3 is a schematic block diagram of the internal structure of the FPGA programmable logic device in Fig. 2;

Fig. 4 is the structural schematic block diagram of PCI-E interface 10 among Fig. 2;

Fig. 5 is a block diagram of the internal connection structure between the FPGA programmable logic device and the PCI-E interface.

Explanation of symbols in the figure: 1. MPU micro-processing unit, 2. Dual-port memory, 3. PCI interface, 4. Computer, 5. GPS receiving module, 6. Phase-locked loop frequency multiplier module, 7. CPLD programmable device, 8 , Beidou receiving module, 9, FPGA programmable logic device, 10, PCI-E interface, 11, computer, 12, GPRMC positioning information, 13, satellite time decoding module, 14, dual-port RAM memory module, 15, main control module , 16. Address data signal path, 17. PPS trigger signal, 18. PCI-E interface chip, 19. PCI-E bus, 20. Configuration memory.

Detailed ways

The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

With reference to shown in Fig. 2, a kind of Beidou B code time service synchronization device based on PCI-E bus, this device comprises Beidou receiving module 8, FPGA programmable logic device 9, PCI-E interface 10 and computer 11, described Beidou receiving module 8 is connected and transmits GPRMC location information 12 to FPGA programmable logic device 9, and described FPGA programmable logic device 9 is connected computer 11 by PCI-E interface 10, virtual out a RAM memory in described FPGA programmable logic device 9, FPGA The corresponding time zone time demodulated by the programmable logic device 9 is stored in the virtual RAM memory, and the corresponding trigger signal triggers the PCI-E interface 10 to interrupt and read the time zone time in the RAM memory to the computer 11 .

With reference to shown in Figure 3, described FPGA programmable logic device 9 comprises interconnected satellite time decoding module 13 and main control module 15, and described main control module 15 virtual goes out a dual-port RAM memory module 14, and described satellite time decoding Module 13 receives GPRMC positioning information 12, solves UTC time and converts into Beijing time and writes in the dual-port RAM memory module 14;

With reference to shown in Figure 4, described PCI-E interface 10 comprises PCI-E interface chip 18, PCI-E bus 19 and configuration memory 20, and described PCI-E bus 19 connects PCI-E interface chip 18, and described PCI-E The E interface chip 18 is connected to the configuration memory 20. When the power is just turned on, the PCI-E interface chip 18 reads the configuration information in the configuration memory 20. The main control module 15 is connected to the PCI-E interface chip 18, and the main control module 15 sends a PPS trigger signal 17 Trigger the PCI-E interface chip 18 to enter the interrupt program, and the PCI-E interface chip 18 reads the Beijing time information in the dual-port RAM memory module 14 through the address data signal path 16 and transmits it to the computer 11 through the PCI-E bus 19.

The Beidou receiving module 8 adopts the N303 Beidou module.

The FPGA programmable logic device 9 adopts an EP2C5T144C8N chip.

Described PCI-E interface chip 18 adopts CH368 chip.

The principle of the present invention: the Beidou receiving module 8 receives satellite signals and sends the GPRMC positioning information 12 to the FPGA programmable logic device 9, and the FPGA programmable logic device 9 internally solves the UTC time change and converts it into Beijing time and stores it in the dual-port RAM memory module 14. The PPS trigger signal 17 generated by the FPGA programmable logic device 9 triggers the PCI-E interface chip 18 to interrupt and read the Beijing time in the dual-port RAM memory module 14 to the computer 11 .

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (5)

1. the Big Dipper B code time service synchronous device of a Based PC I-E bus, it is characterized in that, this device comprises Big Dipper receiver module (8), FPGA programmable logic device (9), PCI-E interface (10) and computing machine (11), described Big Dipper receiver module (8) connects and transmits GPRMC locating information (12) to FPGA programmable logic device (9), described FPGA programmable logic device (9) connects computing machine (11) by PCI-E interface (10), a RAM storer is fictionalized in described FPGA programmable logic device (9), the corresponding time zone time that FPGA programmable logic device (9) demodulates is stored in this virtual RAM storer, and by the time zone time in corresponding this RAM storer of trigger pip triggering PCI-E interface (10) interruption reading to computing machine (11).

2. the Big Dipper B code time service synchronous device of Based PC I-E bus according to claim 1, it is characterized in that, described FPGA programmable logic device (9) comprises interconnective satellite time decoder module (13) and main control module (15), described main control module (15) fictionalizes a RAM module (14), described satellite time decoder module (13) reception GPRMC locating information (12), solves the UTC time and the Beijing time of being converted into writes in RAM module (14);

Described PCI-E interface (10) comprises PCI-E interface chip (18), PCI-E bus (19) and config memory (20), described PCI-E bus (19) connects PCI-E interface chip (18), described PCI-E interface chip (18) connects config memory (20), described main control module (15) connects PCI-E interface chip (18), main control module (15) sends PPS trigger pip (17) triggering PCI-E interface chip (18) and enters interrupt routine, the Beijing time information that described PCI-E interface chip (18) reads RAM module (14) the inside by address data signal path (16) also passes to computing machine (11) by PCI-E bus (19).

3. the Big Dipper B code time service synchronous device of Based PC I-E bus according to claim 1, is characterized in that, described Big Dipper receiver module (8) adopts N303 Big Dipper module.

4. the Big Dipper B code time service synchronous device of Based PC I-E bus according to claim 2, is characterized in that, described FPGA programmable logic device (9) adopts EP2C5T144C8N chip.

5. the Big Dipper B code time service synchronous device of Based PC I-E bus according to claim 2, is characterized in that, described PCI-E interface chip (18) adopts CH368 chip.