CN102571503B - SDLC (System Development Life Cycle) protocol bus communication testing device based on FPGA (Field-Programmable Gate Array) - Google Patents

SDLC (System Development Life Cycle) protocol bus communication testing device based on FPGA (Field-Programmable Gate Array) Download PDF

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CN102571503B
CN102571503B CN201210072878.7A CN201210072878A CN102571503B CN 102571503 B CN102571503 B CN 102571503B CN 201210072878 A CN201210072878 A CN 201210072878A CN 102571503 B CN102571503 B CN 102571503B
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test
fpga
module
differential
signal
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CN102571503A (en
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郝斌魁
孔令涛
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SHANGHAI WORKPOWER TELECOM TECHNOLOGY CO., LTD.
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Shanghai Aerospace Science and Industry Appliance Co Ltd
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Abstract

The invention discloses an SDLC (System Development Life Cycle) protocol bus communication testing device based on FPGA (Field-Programmable Gate Array). The testing device is characterized by being composed of an FPGA test module, a differential driver, a differential receiver, a connector, a computer, a crystal oscillator and a memory, wherein the computer inputs test data to the FPGA test module to form an SDLC sequence, the SDLC sequence is input to the differential driver, the differential driver converts the SDLC sequence into differential signals, the differential signals are input to the connector, the connector inputs test signals of self-tested and tested products to the differential receiver, the differential receiver converts the test signals into logic signals, the logic signals are input to the FPGA test module for performing SDLC protocol decoding, and the computer calculates the error rate and delay time of the tested product. As compared with the prior art, the testing device has the advantages of high testing efficiency, convenience for operation and convenience for system integration, and can automatically change the design content as required so as to meet the testing of special occasions.

Description

A kind of SDLC protocol bus communication test device based on FPGA
Technical field
The present invention relates to communication check technical field, specifically a kind of SDLC protocol bus communication test device based on FPGA.
Background technology
At present, in multipoint communication system, as in the networking of armament systems, industrial collecting and distributing compartment system and business POS cash register, all adopt serial communication, RS-485 is a kind of serial interface standard of balance transmission mode, be characterized in that antijamming capability is strong, transmission rate is high, and transmitting range is far away.While adopting twisted-pair feeder, the peak transfer rate that it allows is 10Mbit/s, and its transmitting range is 15m, and RS-485 allows to connect at most 32 transmitter/receivers pair on balanced cable, is widely applied in many aspects.
The normal a kind of agreement adopting of serial communication is synchronous data link control SDLC, the feature of this agreement is that transmitted frame data can be any positions, and it is the bit combination pattern by agreement, rather than come beginning and the end of marker frames by specific character, owing to not being with character but take binary digit as smallest transmission unit in this transformat, therefore be called the agreement of " Bit Oriented ".SDLC agreement regulation, all communications must start with a kind of identifier, and finish with same identifier, this identifier is " 01111110 ", be called mark domain (Flag), between from opening flag to end mark, form a complete information unit, be called a frame (Frame), all information is all to transmit with the form of frame, and tab character provides the border of each frame, receiving terminal can be determined by search " 01111110 " beginning and the end of frame, sets up frame synchronization with this.RS-485 serial bus communication based on SDLC agreement is a kind of more common communication form that realizes main system and each subsystem information exchange, generally, be mainly high transmission rates, low error rate, low time of delay and high reliability to the requirement of this communication interface.
At present, error code testing has been developed some code error detecting instruments, signal delay can be monitored by oscilloscope, but because its cost is high, volume is large, complicated operation, be unfavorable for system integration application, especially to-be-measured cell is carried out to the processs of the test such as functional test, seasoned, temperature cycles, high low temperature, random vibration, noise and transportation must be by a large amount of testing equipments with product transfer, fitting operation is very inconvenient.
Summary of the invention
The object of the invention is a kind of SDLC protocol bus communication test device based on FPGA designing for the deficiencies in the prior art, adopt the error rate and the time of delay of the SDLC protocol communication of FPGA test of heuristics changeable frequency, testing efficiency is high, easy to operate, be convenient to system integration, there is very strong versatility, flexibility and practicality, and can change voluntarily as requested design content, meet the test of specific applications.
The object of the present invention is achieved like this: a kind of SDLC protocol bus communication test device based on FPGA, be characterized in that this testing apparatus is by FPGA test module, differential driver, differential receiver, connector, computer, crystal oscillator and memory composition, computer, crystal oscillator and memory access respectively FPGA test module, the output of FPGA test module is connected with differential driver input, differential driver output is connected with connector one input, connector one output is connected with differential receiver input, differential receiver output is connected with the input of FPGA test module, another output of connector is provided with self check branch road with another input of connector and is connected, computer sends test data and test instruction to FPGA test module, and crystal oscillator provides clock source for FPGA test module, and memory provides loading procedure for FPGA test module, by computer, the test data generating is at random inputted to FPGA test module, FPGA test module will be inputted input difference driver after data compositions synchronous data-link control sequence, differential driver accesses connector after transferring sequence signal to differential signal, the self-test signal that connector forms by self check branch road when differential signal is exported accesses connector together with the test signal of test product, by connector by the test signal access differential receiver of self-test signal and test product, differential receiver transfers differential signal to input FPGA test module after logical signal and carry out protocol-decoding to, decoded data input computer, send data by computer by comparison, self check data and test data are calculated the error rate and the time of delay of test product.
Described FPGA test module be provided with clock unit, address latch, address decoder, control register, communication module and time of delay test module field programmable gate array or programmable logic device.
Described FPGA test module or be provided with random number module, replace computer to send test data to FPGA test module by random number module, and the self-test signal to the signal sending, reception and test signal are directly compared by turn by FPGA test module, input again computer after calculating the error rate.
The present invention compared with prior art has following beneficial effect:
(1), volume is little, cost is low, is conducive to system integration, be convenient to be integrated into a set of test macro with correlation function test;
(2), can be directly in the operation of computer control end, convenient test, does not need Error Detector and oscilloscope and complicated measurement circuit to build;
(3), there is very strong versatility, flexibility and practicality, can change voluntarily as requested design content, meet the test of specific applications.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention;
Fig. 2 is the invention process illustration;
Fig. 3 is embodiment work schematic diagram;
Fig. 4 is FPGA test module structural representation;
Fig. 5 is clock administration module structural representation;
Fig. 6 is communication module structural representation;
Fig. 7 is sending module structural representation;
Fig. 8 is receiver module structural representation;
Fig. 9 is test module work time of delay schematic diagram.
Embodiment
Consult accompanying drawing 1, the present invention is made up of FPGA test module 1, differential driver 2, differential receiver 3, connector 4, computer 5, crystal oscillator 6 and memory 7, and computer 5, crystal oscillator 6 and memory 7 access respectively FPGA test module 1, FPGA test module 1 output is connected with differential driver 2 inputs, differential driver 2 outputs are connected with connector 4 one inputs, connector 4 one outputs are connected with differential receiver 3 inputs, differential receiver 3 outputs are connected with 1 input of FPGA test module, and connector 4 another outputs are provided with self check branch road 9 with connector 4 another inputs and are connected, computer 5 sends test data and test instruction to FPGA test module 1, and crystal oscillator 6 provides clock source for FPGA test module 1, and memory 7 provides loading procedure for FPGA test module 1, by computer 5, the test data generating is at random inputted to FPGA test module 1, FPGA test module 1 will be inputted input difference driver 2 after data compositions synchronous data-link control sequence, differential driver 2 accesses connector 4 after transferring sequence signal to differential signal, by connector 4 output difference sub-signals, the self-test signal of test product and test signal are by connector 4 access differential receivers 3, differential receiver 3 transfers differential signal to input FPGA test module 1 after logical signal and carry out protocol-decoding to, decoded data input computer 5, send data by computer 5 by comparison, self check data and test data are calculated the error rate and the time of delay of test product.
Above-mentioned FPGA test module 1 or be provided with random number module, replace computer 5 to send test data to FPGA test module 1 by random number module, and the self-test signal to the signal sending, reception and test signal are directly compared by turn by FPGA test module 1, input again computer 5 after calculating the error rate.
Below will by specific embodiment, the present invention is further elaborated:
Embodiment 1
Consult accompanying drawing 2, connector 4 of the present invention is connected to the tested module 8 of product, FPGA test module 1 is for the test of signal error rate and time of delay; Memory 7 provides loading procedure for FPGA test module 1; Crystal oscillator 6, for FPGA test module 1 provides clock source; Differential driver 2 is converted into differential signal output for the SDLC signal that FPGA test module 1 is exported; Differential receiver 3 send FPGA test module 1 to process for the differential signal of input being converted into logical signal; Computer 5 is for sending test instruction and data to FPGA test module 1, and receives data from FPGA test module 1, carries out data processing.
The present invention is performed such bus communication test:
Consult accompanying drawing 3, FPGA test module 1 is connected to synchronised clock and data output the logic level input of differential driver 2, and the differential clocks being converted to by differential driver 2 and data access clock and the data input pin of tested module 8 by connector 4; Meanwhile, connector 4 also by the differential clocks being converted to and data by self check branch road 9 by connector 4 access differential receivers 3, differential receiver 3 transfers differential clocks and data to logic level signal access FPGA test module 1 and carries out self-checking; The input clock returning and data are passed through connector 4 access differential receivers 3 by the signal output part of tested module 8, transfer differential clocks and data to logic level signal access FPGA test module 1 by differential receiver 3, the logic level signal of input is carried out SDLC protocol-decoding by FPGA test module 1, decoded data are inputted computer 5, are sent the error rate and the time of delay of data, self check data and test data calculating test product by computer 5 by comparison.Host computer can carry out contrast test checking to output clock data, self check clock data and input clock data simultaneously like this, can effectively prevent from, because system interference causes error rate erroneous judgement, improving the reliability of test.
FPGA test module 1 is by relatively the rising edge of output and input signal or trailing edge postpone in real time, and be converted to triggering level, controlling inner high speed counter counts, counter always records one group of maximum in test, after count value, carry out zero clearing having read, can calculate signal delay time by count value and count cycle.
Consult accompanying drawing 4, FPGA test module 1 adopts Hierarchical Design, top layer by clock unit 11, address latch 12, address decoder 13, control register 14, communication module 15 and time of delay test module 16 form, bus address signal is latched into address latch 12 through control signal, and by address decoder 13 decodings, each submodule work of gating, under the control enabling in read-write, write instruction or sense data from each submodule, control register 14 comprises the control bit to global state, as Global reset, operating state lamp etc.
Consult accompanying drawing 5, the digital dock administrative unit (DCM) of Clock management module 11 for using FPGA to carry, formed by digital frequency synthesizer (DFS) 21, delay phase-locked loop (DLL) 22 and the first counter 23, Clock management module 11 provides work clock for FPGA test module 1, simultaneously for SDLC communication test provides changeable frequency clock; The 32MHz clock input of DCM receiving crystal oscillator 6, generates 224MHz high frequency clock by seven frequencys multiplication of digital frequency synthesizer (DFS) 21, for count frequency time of delay; Four frequency divisions by delay phase-locked loop (DLL) 22 generate 8MHz clock, and for FPGA normal working frequency, 8MHz clock can be changed into 1MHz ~ 8MHz clock after frequency division again through the first counter 23, for the SDLC communication test of changeable frequency.
Consult accompanying drawing 6, communication test module 14 is made up of sending module 31, self check receiver module 32 and test receiver module 33, communication test module 14 is for RS485 bus error code testing, self check receiver module 32 is for the reception test in self check loop, and test receiver module 33 is for the reception test of test product signal; Address decoder 12 gating sending modules 31, self check receiver module 32 or test receiver module 33 carry out data manipulation, and control register 13 mainly arranges SDLC operating frequency and controls sending module 31, self check receiver module 32, test receiver module 33.
Consult accompanying drawing 7, sending module 31 forms by sending state machine 40, FIFO read states machine 42, a FIFO memory 43,7E mark state machine 44,7E mark transmitter 45, MUX 46, the first shift register 47, displaced condition machine 48 and the first detected state machine 49, start after transmission order when receiving external bus, first transmission state machine 40 enters frame and starts transmission state, indicate that by 7E state machine 44,7E mark transmitter 45 send four of opening flags " 01111110 ", MUX 46 indicates that by 7E transmitter 45 is switched to output signal; When 7E mark transmitter 45 distributes after four " 01111110 ", send state machine 40 and enter data transmission state; Displaced condition machine 48 starts to coordinate FIFO read states machine 42 data fifo is read to the output that is shifted of the first shift register 47; Serial data is switched to output signal by MUX 46; The first detected state machine 49 sends state in data displaced condition machine 48 is monitored, and when finding after output continuous five " 1 ", notifies immediately displaced condition machine 48 to control output data and inserts " 0 "; After data fifo sends, send state machine 40 and enter frame end transmission state, 7E mark transmitter 45 sends 4 of end marks " 01111110 ", MUX 46 indicates that by 7E transmitter 45 is switched to output signal, when after a transmission end cycle, sending module 31 comes back to idle condition, and 46 of MUX are in high-impedance state.
Consult accompanying drawing 8, self check receiver module 32 and self-checking module 33 are the identical receiver module of functional structure, receiver module is by the second counter 52, the 3rd counter 53, accepting state machine 54, the second detected state machine 55, the 2nd FIFO memory 56, the second shift register 57, the 3rd shift register 58 forms, the 3rd shift register 58 receives external serial signal under the effect of external clock, accepting state machine 54 is monitored the 3rd shift register 58, when receiving after four " 01111110 " start of frame delimiters, accepting state machine 54 proceeds to data receiver, when again occurring after continuous four " 01111110 " frame end marks, accepting state machine 54 is got back to Idle state.The bit number that the 3rd counter 53 is received the 3rd shift register 58 is counted, in the time that accepting state machine 54 receives first " 01111110 ", count resets, and after the full byte of every meter, determine whether " 01111110 " mark, guarantee the continuity of four 7E marks, in the time receiving data, in the time finding to input " 0 " after continuous five " 1 ", the 3rd counter 53 stops a clock.The second detected state machine 55 at data receiving state to being about to send into the position of the second shift register 57, " Bit7 " of the 3rd shift register 58 monitors, when find after continuous five " 1 " " 0 " time, notify the second shift register 57, the second counter 52 and the 3rd counter 53; When in data receiving state, the second shift register 57, under the effect of external clock, receives the 3rd shift register 58 serial datas, in the time of " 0 " running into after five " 1 ", stops displacement and abandons " 0 " signal; The bit number that the second counter 52 receives the second shift register 57 is counted, and delete " 0 " signal during when receiving, the second counter 52 stops 1 clock.The 2nd FIFO memory 56 receives the data of the second shift register 57, reads clock when just exporting one after full 1 byte of the second counter 52, and the data of the second shift register 57 are read in " FIFO ".
Consult accompanying drawing 9, time of delay, test module 16 was made up of 4 groups of delay counter submodules, being respectively used to clock delay, data delay, clock self check delay and data self check postpones, delay counter submodule is made up of XOR gate, interim counter, rising edge counter and trailing edge counter, output signal and the self-test signal returning from connector 4 or the input signal returning from tested module 8 compare through XOR gate, in the time of output and input signal appearance delay, XOR gate is output as " 1 " (delay pulse); Interim counter provides 224MHz clock by DCM, and it enables the delayed pulse signal of termination XOR gate output, in the time that delayed pulse signal is " 1 ", starts counting, in the time postponing to disappear, stops counting.Count value is now the length of delay of current demand signal, after the cycle converts, can obtain time of delay.Delay pulse will judge output signal level after disappearing, if high level, is counted as rise edge delay, otherwise it is trailing edge delay, interim counter will compare with rising edge counter or trailing edge counter, always higher value will be updated in rising edge counter or trailing edge counter.
Above-described embodiment only provides one group of SDLC protocol test passage, the present invention can comprise the communication test of many groups signal of difference output, self check and input clock data, be convenient to change voluntarily design content and the integrated measuring system constructing platform of other test function, better to meet the test of specific applications.Above-mentioned test data can replace computer 5 random numbers to be handed down to FPGA test module 1 by set up random number generation module in FPGA, the self-test signal receiving and test signal, can directly be compared by turn by FPGA test module 1, calculate the error rate, then pass to computer 5; Computer 5 is for meeting the intelligent system with program control and interactive function of IBM PC standard or embedded system; The SDLC protocol sequence that described FPGA generates, only compares by turn the information in frame, and is indifferent to frame check territory wherein, does not therefore provide verification frame generation module, can add verification frame generation module, generates the frame sequence that meets SDLC agreement completely; Described FPGA generates the SDLC protocol sequence of 32 bytes, also can be the SDLC protocol sequence of other byte length; Described FPGA input clock is 32MHz, also can be other frequency, arrives 224MHz by frequency multiplication, also can frequency multiplication arrive other frequency, and the SDLC clock after frequency division is 1 ~ 8MHz, can frequency division be also other frequency.
More than just the present invention is further illustrated, and not in order to limit this patent, all is the present invention's equivalence enforcement, within all should being contained in the claim scope of this patent.

Claims (3)

1. the SDLC protocol bus communication test device based on FPGA, it is characterized in that this testing apparatus is by FPGA test module, differential driver, differential receiver, connector, computer, crystal oscillator and memory composition, computer, crystal oscillator and memory access respectively FPGA test module, the output of FPGA test module is connected with differential driver input, differential driver output is connected with connector one input, connector one output is connected with differential receiver input, differential receiver output is connected with the input of FPGA test module, another output of connector is provided with self check branch road with another input of connector and is connected, computer sends test data and test instruction to FPGA test module, and crystal oscillator provides clock source for FPGA test module, and memory provides loading procedure for FPGA test module, by computer, the test data generating is at random inputted to FPGA test module, FPGA test module will be inputted input difference driver after data compositions synchronous data-link control sequence, differential driver accesses connector after transferring sequence signal to differential signal, the self-test signal that connector forms by self check branch road when differential signal is exported accesses connector together with the test signal of test product, by connector by the test signal access differential receiver of self-test signal and test product, differential receiver transfers differential signal to input FPGA test module after logical signal and carry out protocol-decoding to, decoded data input computer, send data by computer by comparison, self check data and test data are calculated the error rate and the time of delay of test product.
2. the SDLC protocol bus communication test device based on FPGA according to claim 1, it is characterized in that described FPGA test module be provided with clock unit, address latch, address decoder, control register, communication module and time of delay test module field programmable gate array or programmable logic device.
3. according to the SDLC protocol bus communication test device based on FPGA described in claim 1 or claim 2, it is characterized in that described FPGA test module or be provided with random number module, replace computer to send test data to FPGA test module by random number module, and the self-test signal to the signal sending, reception and test signal are directly compared by turn by FPGA test module, input again computer after calculating the error rate.
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CN105404568A (en) * 2015-12-03 2016-03-16 广州汽车集团股份有限公司 CAN bus test system and test method
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CN110646723B (en) * 2018-06-27 2021-11-30 龙芯中科技术股份有限公司 Bus interface test circuit and method
CN112285542B (en) * 2020-10-14 2023-02-03 天津津航计算技术研究所 Debugging and testing method for FPGA external interface logic
CN112630567A (en) * 2020-12-14 2021-04-09 山东核电有限公司 Automatic response time testing scheme based on FPGA technology

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