CN102571503B - SDLC (System Development Life Cycle) protocol bus communication testing device based on FPGA (Field-Programmable Gate Array) - Google Patents
SDLC (System Development Life Cycle) protocol bus communication testing device based on FPGA (Field-Programmable Gate Array) Download PDFInfo
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Abstract
The invention discloses an SDLC (System Development Life Cycle) protocol bus communication testing device based on FPGA (Field-Programmable Gate Array). The testing device is characterized by being composed of an FPGA test module, a differential driver, a differential receiver, a connector, a computer, a crystal oscillator and a memory, wherein the computer inputs test data to the FPGA test module to form an SDLC sequence, the SDLC sequence is input to the differential driver, the differential driver converts the SDLC sequence into differential signals, the differential signals are input to the connector, the connector inputs test signals of self-tested and tested products to the differential receiver, the differential receiver converts the test signals into logic signals, the logic signals are input to the FPGA test module for performing SDLC protocol decoding, and the computer calculates the error rate and delay time of the tested product. As compared with the prior art, the testing device has the advantages of high testing efficiency, convenience for operation and convenience for system integration, and can automatically change the design content as required so as to meet the testing of special occasions.
Description
Technical field
The present invention relates to communication check technical field, specifically a kind of SDLC protocol bus communication test device based on FPGA.
Background technology
At present, in multipoint communication system, as in the networking of armament systems, industrial collecting and distributing compartment system and business POS cash register, all adopt serial communication, RS-485 is a kind of serial interface standard of balance transmission mode, be characterized in that antijamming capability is strong, transmission rate is high, and transmitting range is far away.While adopting twisted-pair feeder, the peak transfer rate that it allows is 10Mbit/s, and its transmitting range is 15m, and RS-485 allows to connect at most 32 transmitter/receivers pair on balanced cable, is widely applied in many aspects.
The normal a kind of agreement adopting of serial communication is synchronous data link control SDLC, the feature of this agreement is that transmitted frame data can be any positions, and it is the bit combination pattern by agreement, rather than come beginning and the end of marker frames by specific character, owing to not being with character but take binary digit as smallest transmission unit in this transformat, therefore be called the agreement of " Bit Oriented ".SDLC agreement regulation, all communications must start with a kind of identifier, and finish with same identifier, this identifier is " 01111110 ", be called mark domain (Flag), between from opening flag to end mark, form a complete information unit, be called a frame (Frame), all information is all to transmit with the form of frame, and tab character provides the border of each frame, receiving terminal can be determined by search " 01111110 " beginning and the end of frame, sets up frame synchronization with this.RS-485 serial bus communication based on SDLC agreement is a kind of more common communication form that realizes main system and each subsystem information exchange, generally, be mainly high transmission rates, low error rate, low time of delay and high reliability to the requirement of this communication interface.
At present, error code testing has been developed some code error detecting instruments, signal delay can be monitored by oscilloscope, but because its cost is high, volume is large, complicated operation, be unfavorable for system integration application, especially to-be-measured cell is carried out to the processs of the test such as functional test, seasoned, temperature cycles, high low temperature, random vibration, noise and transportation must be by a large amount of testing equipments with product transfer, fitting operation is very inconvenient.
Summary of the invention
The object of the invention is a kind of SDLC protocol bus communication test device based on FPGA designing for the deficiencies in the prior art, adopt the error rate and the time of delay of the SDLC protocol communication of FPGA test of heuristics changeable frequency, testing efficiency is high, easy to operate, be convenient to system integration, there is very strong versatility, flexibility and practicality, and can change voluntarily as requested design content, meet the test of specific applications.
The object of the present invention is achieved like this: a kind of SDLC protocol bus communication test device based on FPGA, be characterized in that this testing apparatus is by FPGA test module, differential driver, differential receiver, connector, computer, crystal oscillator and memory composition, computer, crystal oscillator and memory access respectively FPGA test module, the output of FPGA test module is connected with differential driver input, differential driver output is connected with connector one input, connector one output is connected with differential receiver input, differential receiver output is connected with the input of FPGA test module, another output of connector is provided with self check branch road with another input of connector and is connected, computer sends test data and test instruction to FPGA test module, and crystal oscillator provides clock source for FPGA test module, and memory provides loading procedure for FPGA test module, by computer, the test data generating is at random inputted to FPGA test module, FPGA test module will be inputted input difference driver after data compositions synchronous data-link control sequence, differential driver accesses connector after transferring sequence signal to differential signal, the self-test signal that connector forms by self check branch road when differential signal is exported accesses connector together with the test signal of test product, by connector by the test signal access differential receiver of self-test signal and test product, differential receiver transfers differential signal to input FPGA test module after logical signal and carry out protocol-decoding to, decoded data input computer, send data by computer by comparison, self check data and test data are calculated the error rate and the time of delay of test product.
Described FPGA test module be provided with clock unit, address latch, address decoder, control register, communication module and time of delay test module field programmable gate array or programmable logic device.
Described FPGA test module or be provided with random number module, replace computer to send test data to FPGA test module by random number module, and the self-test signal to the signal sending, reception and test signal are directly compared by turn by FPGA test module, input again computer after calculating the error rate.
The present invention compared with prior art has following beneficial effect:
(1), volume is little, cost is low, is conducive to system integration, be convenient to be integrated into a set of test macro with correlation function test;
(2), can be directly in the operation of computer control end, convenient test, does not need Error Detector and oscilloscope and complicated measurement circuit to build;
(3), there is very strong versatility, flexibility and practicality, can change voluntarily as requested design content, meet the test of specific applications.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention;
Fig. 2 is the invention process illustration;
Fig. 3 is embodiment work schematic diagram;
Fig. 4 is FPGA test module structural representation;
Fig. 5 is clock administration module structural representation;
Fig. 6 is communication module structural representation;
Fig. 7 is sending module structural representation;
Fig. 8 is receiver module structural representation;
Fig. 9 is test module work time of delay schematic diagram.
Embodiment
Consult accompanying drawing 1, the present invention is made up of FPGA test module 1, differential driver 2, differential receiver 3, connector 4, computer 5, crystal oscillator 6 and memory 7, and computer 5, crystal oscillator 6 and memory 7 access respectively FPGA test module 1, FPGA test module 1 output is connected with differential driver 2 inputs, differential driver 2 outputs are connected with connector 4 one inputs, connector 4 one outputs are connected with differential receiver 3 inputs, differential receiver 3 outputs are connected with 1 input of FPGA test module, and connector 4 another outputs are provided with self check branch road 9 with connector 4 another inputs and are connected, computer 5 sends test data and test instruction to FPGA test module 1, and crystal oscillator 6 provides clock source for FPGA test module 1, and memory 7 provides loading procedure for FPGA test module 1, by computer 5, the test data generating is at random inputted to FPGA test module 1, FPGA test module 1 will be inputted input difference driver 2 after data compositions synchronous data-link control sequence, differential driver 2 accesses connector 4 after transferring sequence signal to differential signal, by connector 4 output difference sub-signals, the self-test signal of test product and test signal are by connector 4 access differential receivers 3, differential receiver 3 transfers differential signal to input FPGA test module 1 after logical signal and carry out protocol-decoding to, decoded data input computer 5, send data by computer 5 by comparison, self check data and test data are calculated the error rate and the time of delay of test product.
Above-mentioned FPGA test module 1 or be provided with random number module, replace computer 5 to send test data to FPGA test module 1 by random number module, and the self-test signal to the signal sending, reception and test signal are directly compared by turn by FPGA test module 1, input again computer 5 after calculating the error rate.
Below will by specific embodiment, the present invention is further elaborated:
Embodiment 1
The present invention is performed such bus communication test:
FPGA test module 1 is by relatively the rising edge of output and input signal or trailing edge postpone in real time, and be converted to triggering level, controlling inner high speed counter counts, counter always records one group of maximum in test, after count value, carry out zero clearing having read, can calculate signal delay time by count value and count cycle.
Above-described embodiment only provides one group of SDLC protocol test passage, the present invention can comprise the communication test of many groups signal of difference output, self check and input clock data, be convenient to change voluntarily design content and the integrated measuring system constructing platform of other test function, better to meet the test of specific applications.Above-mentioned test data can replace computer 5 random numbers to be handed down to FPGA test module 1 by set up random number generation module in FPGA, the self-test signal receiving and test signal, can directly be compared by turn by FPGA test module 1, calculate the error rate, then pass to computer 5; Computer 5 is for meeting the intelligent system with program control and interactive function of IBM PC standard or embedded system; The SDLC protocol sequence that described FPGA generates, only compares by turn the information in frame, and is indifferent to frame check territory wherein, does not therefore provide verification frame generation module, can add verification frame generation module, generates the frame sequence that meets SDLC agreement completely; Described FPGA generates the SDLC protocol sequence of 32 bytes, also can be the SDLC protocol sequence of other byte length; Described FPGA input clock is 32MHz, also can be other frequency, arrives 224MHz by frequency multiplication, also can frequency multiplication arrive other frequency, and the SDLC clock after frequency division is 1 ~ 8MHz, can frequency division be also other frequency.
More than just the present invention is further illustrated, and not in order to limit this patent, all is the present invention's equivalence enforcement, within all should being contained in the claim scope of this patent.
Claims (3)
1. the SDLC protocol bus communication test device based on FPGA, it is characterized in that this testing apparatus is by FPGA test module, differential driver, differential receiver, connector, computer, crystal oscillator and memory composition, computer, crystal oscillator and memory access respectively FPGA test module, the output of FPGA test module is connected with differential driver input, differential driver output is connected with connector one input, connector one output is connected with differential receiver input, differential receiver output is connected with the input of FPGA test module, another output of connector is provided with self check branch road with another input of connector and is connected, computer sends test data and test instruction to FPGA test module, and crystal oscillator provides clock source for FPGA test module, and memory provides loading procedure for FPGA test module, by computer, the test data generating is at random inputted to FPGA test module, FPGA test module will be inputted input difference driver after data compositions synchronous data-link control sequence, differential driver accesses connector after transferring sequence signal to differential signal, the self-test signal that connector forms by self check branch road when differential signal is exported accesses connector together with the test signal of test product, by connector by the test signal access differential receiver of self-test signal and test product, differential receiver transfers differential signal to input FPGA test module after logical signal and carry out protocol-decoding to, decoded data input computer, send data by computer by comparison, self check data and test data are calculated the error rate and the time of delay of test product.
2. the SDLC protocol bus communication test device based on FPGA according to claim 1, it is characterized in that described FPGA test module be provided with clock unit, address latch, address decoder, control register, communication module and time of delay test module field programmable gate array or programmable logic device.
3. according to the SDLC protocol bus communication test device based on FPGA described in claim 1 or claim 2, it is characterized in that described FPGA test module or be provided with random number module, replace computer to send test data to FPGA test module by random number module, and the self-test signal to the signal sending, reception and test signal are directly compared by turn by FPGA test module, input again computer after calculating the error rate.
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CN108696288B (en) * | 2017-06-09 | 2022-02-01 | 京东方科技集团股份有限公司 | Signal transmission method, transmitting unit, receiving unit and display device |
CN110646723B (en) * | 2018-06-27 | 2021-11-30 | 龙芯中科技术股份有限公司 | Bus interface test circuit and method |
CN112285542B (en) * | 2020-10-14 | 2023-02-03 | 天津津航计算技术研究所 | Debugging and testing method for FPGA external interface logic |
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Title |
---|
梁士龙等.用FPGA实现RS-485通信接口芯片.《系统工程与电子技术》.2002,第24卷(第4期),103-106. |
用FPGA实现RS-485通信接口芯片;梁士龙等;《系统工程与电子技术》;20020430;第24卷(第4期);103-106 * |
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