CN106783787A - Electrode for chip package and the chip-packaging structure using the electrode - Google Patents
Electrode for chip package and the chip-packaging structure using the electrode Download PDFInfo
- Publication number
- CN106783787A CN106783787A CN201710059273.7A CN201710059273A CN106783787A CN 106783787 A CN106783787 A CN 106783787A CN 201710059273 A CN201710059273 A CN 201710059273A CN 106783787 A CN106783787 A CN 106783787A
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- Prior art keywords
- matrix material
- electrode
- chip
- hole
- pit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 16
- 239000011159 matrix material Substances 0.000 claims abstract description 129
- 239000002131 composite material Substances 0.000 claims abstract description 10
- 239000004020 conductor Substances 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 31
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 239000011148 porous material Substances 0.000 claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- 239000004411 aluminium Substances 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 239000010931 gold Substances 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 229910052709 silver Inorganic materials 0.000 claims description 9
- 239000004332 silver Substances 0.000 claims description 9
- 239000000203 mixture Substances 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 6
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910002804 graphite Inorganic materials 0.000 claims description 3
- 239000010439 graphite Substances 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910052574 oxide ceramic Inorganic materials 0.000 claims description 2
- 239000011224 oxide ceramic Substances 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- 208000025599 Heat Stress disease Diseases 0.000 description 3
- 230000035939 shock Effects 0.000 description 3
- 229910017083 AlN Inorganic materials 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
Abstract
There is provided a kind of electrode for chip package, the electrode includes：First matrix material, the thermal coefficient of expansion scope of first matrix material is 0 12 × 10‑6/℃；And second matrix material, second matrix material is that the thermal conductivity scope of conductive material and second matrix material is 60 600W/m ﹒ k；Wherein first matrix material and second matrix material is mixed to form composite, or one of first matrix material and second matrix material are embedded at one or more positions of another one.A kind of chip-packaging structure is additionally provided, including：Chip；And one or more electrodes as described above for being connected with the chip, wherein first matrix material and second matrix material are by weld layer or be conductively connected thing and be connected with chip.
Description
Technical field
The present invention relates to encapsulated electrode, the particularly electrode for chip package and the chip package knot using the electrode
Structure.
Background technology
Power chip application when on the one hand need good radiating, on the other hand temperature rise and decline circulation or
Will cause that chip produces damage when being mismatched with chip due to the thermal coefficient of expansion of heat sink electrodes when the heat fatigues such as impact are tested
And fail.
Traditional chip package is welded with two copper electrodes on the both sides of chip, overall to be formed using ceramics or plastic packaging again.
Because the radiating of copper and conduction are preferable, but its thermal coefficient of expansion is higher, in temperature cycles (- 40 DEG C -85 DEG C) or temperature shock
It is easy to for chip to pull damage when being tested etc. heat fatigue.Using copper as its radiating of electrode and temperature cycles or temperature shock etc.
Thermal fatigue property can not be compatible.Accordingly, it would be desirable to develop a kind of chip package electrode, prevent from being damaged in temperature cycles process chips
Hinder and fail.
The content of the invention
It is an object of the invention to provide a kind of electrode for chip package, rushed in temperature cycles or temperature with solving chip
The problem pullled by electrode and cause to damage is hit etc. in thermal fatigue course.
To realize object above, the present invention provides a kind of electrode for chip package, and the electrode includes：
First matrix material, the thermal coefficient of expansion scope of first matrix material is 0-12 × 10-6/℃；And
Second matrix material, second matrix material is that the thermal conductivity scope of conductive material and second matrix material is
60-600W/m ﹒ k；
Wherein first matrix material is mixed to form composite, or first matrix material with second matrix material
One or more positions for being embedded at another one with one of second matrix material form electrode.
Further, the first surface of the electrode exposes first matrix material and second matrix material.
Further, at least a portion of the first matrix material has porous even pore structure, and second matrix material is filled in
In the porous even hole of pore structure；Or second matrix material at least a portion have it is porous even pore structure, first matrix
Material is filled in the porous even hole of pore structure.
Further, first matrix material is provided with least one pit or through hole, and second matrix material is arranged on this
In pit or through hole.
Further, second matrix material is provided with least one pit or through hole, and first matrix material is arranged on this
In pit or through hole.
Further, first matrix material is metal material or nonmetallic materials
Preferably, the metal material be molybdenum, tungsten, iron-nickel alloy in one kind, or two or more formed mixing
Thing.
Preferably, the nonmetallic materials be graphite, aluminum oxide ceramic, aluminium nitride, beryllium oxide, one kind of carborundum,
Or the mixture of two or more formation.
Further, it is characterised in that second matrix material be copper, aluminium, silver, gold in one kind, or two or more
The mixture of formation, or be to include one or more the composite in copper, aluminium, silver, gold.
Further, the electrode also includes metal level, and the metal level covers at least the one of the outer surface of first matrix material
Part.
Preferably, the material of the metal level is copper, silver, gold, aluminium or nickel.
The present invention also provides a kind of chip-packaging structure, including：
Chip；And
One or more electrodes as described above being connected with the chip, wherein first matrix material and second base
Body material is by weld layer or is conductively connected thing and is connected with chip.
Electrode for chip package of the invention, it is 0-12 × 10 to use thermal coefficient of expansion scope-6/ DEG C the first matrix
Material and the second matrix material that thermal conductivity scope is 60-600W/m ﹒ k are mixed to form composite, or first matrix
One of material and second matrix material are embedded at one or more positions of another one, by setting above, first
The electrode general performance that matrix material and the second matrix material are formed thermal coefficient of expansion out connects with the thermal coefficient of expansion of chip
Closely, and with preferable electrical and thermal conductivity, can be as electrode material and simultaneously in the heat fatigue such as temperature cycles or temperature shock
During chip will not be pullled and cause chip to damage.
Brief description of the drawings
Fig. 1 is the microgram of the electrode of certain embodiments of the present invention.
Fig. 2A is the top view of the electrode of certain embodiments of the present invention.
Fig. 2 B-D are the longitudinal profiles of the porous even pore structure of certain embodiments of the present invention.
Fig. 3 is the profile of the electrode of another embodiment of the present invention.
Fig. 4 is the profile of the electrode of another embodiment of the present invention.
Fig. 5 is the profile of the electrode of another embodiment of the present invention.
Fig. 6 is the profile of the electrode of another embodiment of the present invention.
Fig. 7 is the profile of the electrode of another embodiment of the present invention.
Fig. 8 is the profile of the chip-packaging structure of certain embodiments of the present invention.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
In an embodiment of the present invention, the electrode for chip package includes that thermal coefficient of expansion scope is 0-12 × 10-6/℃
The first matrix material and thermal conductivity scope be second matrix material of 60-600W/m ﹒ k, first matrix material and this
Two matrix materials can be mixed to form composite to make electrode.Likewise it is possible to by first matrix material and this second
One of matrix material is embedded at one or more positions of another one to make electrode.
Electrode for chip package of the invention, it is 0-12 × 10 to use thermal coefficient of expansion scope-6/ DEG C the first matrix
Material and the second matrix material that thermal conductivity scope is 60-600W/m ﹒ k are mixed to form composite, or the first matrix material
One of material and the second matrix material are embedded at one or more positions of another one, by setting above, the first matrix
The electrode general performance that material and the second matrix material are formed thermal coefficient of expansion out is approached with the thermal coefficient of expansion of chip, and
With preferable electrical and thermal conductivity, as electrode material and while chip can will not be pullled during temperature cycles and led
Chip is caused to damage.
Specifically, referring to Fig. 1, Fig. 1 is the micro-organization chart of the electrode of certain embodiments of the present invention, for chip package
Electrode include the first matrix material 102 and the second matrix material 104, first matrix material 102 and second matrix material
104 are mixed to form composite makes electrode.
Similarly, in some embodiments it is possible to one of first matrix material and second matrix material is embedding
Electrode is formed located at one or more positions of another one, Fig. 2-7 shows the one of the electrode for chip package of the invention
A little embodiments.
Referring to Fig. 2, in certain embodiments, at least a portion of first matrix material 102 has porous even pore structure,
Second matrix material 104 is filled in the porous even hole of pore structure.In turn, in certain embodiments, second matrix
At least a portion of material has porous even pore structure, and first matrix material is filled in the porous even hole of pore structure.It is logical
Cross and porous even pore structure is set to the first matrix material or the second matrix material, then filled with the second matrix material or the first material
Hole in porous even pore structure, can adjust the thermal coefficient of expansion of whole electrode so that the overall thermal coefficient of expansion and core of electrode
Piece is matched, and can prevent electrode from producing pulling force to chip during temperature cycles and causing chip to damage failure.
Porous even pore structure herein refers to, in the structure with multiple holes, at least a portion hole in this some holes
It is up/down perforation, can be mutually communicated between Kong Yukong to be spaced from each other.Referring to Fig. 2 B-D, Fig. 2 B-D are of the invention
The longitudinal profile of the porous even pore structure of some embodiments.As shown in Figure 2 B, in certain embodiments, the hole in loose structure 20
22 bottom surfaces that material is penetrated into from the top surface of material.Also just say, when the first matrix material has loose structure, hole 22 from first
The top surface of matrix material penetrates into the bottom surface of the first matrix material, so as to be filled in second matrix material in hole 22 also from the first base
The top surface of body material penetrates into the bottom surface of the first matrix material；In turn, when the first matrix material have loose structure be also as
This, those skilled in the art is it should be appreciated that will not be repeated here.In fig. 2b, it is disconnected between each hole 22.
But can be in certain embodiments, between two holes 22 in multiple holes 22 connection, as shown in Figure 2 C.Fig. 2 B and Fig. 2 C
In the direction in hole be generallyperpendicular, but in certain embodiments, the shape in the hole in loose structure 20 can be irregular
, hole can arbitrarily extend in the material, as long as bottom surface can be extended to from the top surface of material, as shown in Figure 2 D.
Referring to Fig. 3, in certain embodiments, first matrix material 102 is provided with through hole 110, second matrix material
104 are arranged in the through hole 110.The quantity of through hole 110 is not limited to one, and the quantity of the through hole 110 can be with according to actual needs
It is more than one.It is also not necessarily limited to set through hole on first matrix material 102, one can be set on first matrix material 102
Or more than one pit, second matrix material 104 is arranged in the pit.Can also be same on first matrix material 102
When set through hole and pit.The through hole and pit of varying number can be set according to actual conditions, so as to adjust the entirety of electrode
Expansion characteristics, reduce the stress that electrode pair chip is produced.
In turn, referring to Fig. 4, in certain embodiments, second matrix material 104 is provided with pit 112, first base
Body material 102 is arranged in the pit 112.The quantity of pit 112 is not limited to one, according to actual needs the number of the pit 112
Amount can be with more than one.Equally, it is also not necessarily limited to set through hole on second matrix material 104, can on second matrix material 104
To set one or more through hole, first matrix material 102 is arranged in the through hole.Second matrix material 104
On through hole and pit can also be set simultaneously.The through hole and pit of varying number can be set according to actual conditions, so as to adjust
The bulk expansion characteristic of electrode, reduces the stress that electrode pair chip is produced.
In certain embodiments, first matrix material is metal material or nonmetallic materials.The metal material can be
One kind in molybdenum, tungsten, iron-nickel alloy, or two or more formed mixture.The nonmetallic materials can be graphite, three
Al 2 O ceramics, aluminium nitride, beryllium oxide, one kind of carborundum, or two or more formed mixture.
In certain embodiments, second matrix material is the one kind in copper, aluminium, silver, gold, or two or more shape
Into mixture, or be include copper, aluminium, silver, gold in one or more composite.
Referring to Fig. 5-7, in certain embodiments, the electrode can also include metal level, and the metal level covers first base
At least a portion of the outer surface of body material.Metal level is covered by the outer surface of matrix, electrode can be further improved
Heat conductivility, it is possible to reduce the stress that electrode pair chip is produced during temperature cycles.
Referring to Fig. 5, in certain embodiments, the metal level 106 covers the lateral wall of first matrix material 102.Referring to
Fig. 6, in certain embodiments, the metal level 106 covers the whole outer surface of first matrix material 102.Referring to Fig. 7, at certain
In a little embodiments, the matrix material 104 of the first matrix material 102 and second is coated on the inside by the metal level 106.It is superincumbent
In embodiment, the material of the metal level can be copper, silver, gold, aluminium or nickel.
In certain embodiments, the first surface of the electrode exposes first matrix material and second matrix material,
The first surface is connected for passing through solder layer or being conductively connected thing with chip.When the electrode also includes metal level or other materials
When, and the first surface of the electrode is when exposing metal level or other materials, the electrode by metal level or or other materials it is logical
Cross solder layer or be conductively connected thing and be connected with chip.
Each embodiment of electrode of the present invention is described above is, these embodiments can individually be implemented, or different implementations
Example between can combine, such as in one embodiment refer to material can another embodiment in, same one embodiment
In structure can also be combined with the structure of other embodiment, the embodiments herein be used only for citing, be not construed as to this hair
Bright limitation.
The present invention also provides a kind of chip-packaging structure, including：Chip；And one or more be connected with the chip as
Electrode recited above, wherein first matrix material and second matrix material are by weld layer or are conductively connected thing and chip
Connection.Referring to Fig. 8, in certain embodiments, chip-packaging structure includes two electrodes of the embodiment of the present invention and is arranged on two
Chip 202 between individual electrode, wherein each electrode include the first matrix material 102 and are arranged at the first matrix material 102
The second matrix material 104 in through hole 110, wherein the first matrix material 102 and the second matrix material, by solder layer 204 with
Chip 202 is connected.In other examples, the matrix and the conductive pole can also be connected by being conductively connected thing with the chip
Connect.
It should be appreciated that when the first surface of the electrode exposes first matrix material and second matrix material
When, the first surface is by solder layer or is conductively connected thing and is connected with chip, first matrix material and the second matrix material
Material is directly connected to the chip.When the electrode also includes metal level or other materials, and the first surface of the electrode exposes
When metal level or other materials, the electrode is by metal level or or other materials is by solder layer or is conductively connected thing with chip company
Connect, first matrix material and second matrix material are indirectly connected with the chip.
Below only list using the chip-packaging structure of above mentioned some of them electrode, but encapsulating structure can
To use above mentioned any one electrode structure, will not be repeated here.
In certain embodiments, the chip-packaging structure is TSS (Thyristor Surge Suppressor, IGCT
Surgesuppressor) chip-packaging structure, the TSS chip-packaging structures include TSS chips, two electrodes, one of electrode with
The upper surface connection of TSS chips, another electrode is connected with the lower surface of TSS chips.Two electrodes pass through solder layer respectively
It is connected with TSS chips.Also, it is to be understood that chip-packaging structure of the invention is not limited to TSS chip-packaging structures, the above is only
It is merely illustrative of, chip-packaging structure of the invention can also be the encapsulating structure of arbitrary semiconductor chip.The chip is sealed
Chip in assembling structure can be the semiconductor chip being made up of the base chip material such as silicon, germanium, GaAs.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, it is all in essence of the invention
Any modification, equivalent and improvement made within god and principle etc., should be included within the scope of the present invention.
Claims (12)
1. a kind of electrode for chip package, the electrode includes：
First matrix material, the thermal coefficient of expansion scope of first matrix material is 0-12 × 10-6/℃；And
Second matrix material, second matrix material is 60- for the thermal conductivity scope of conductive material and second matrix material
600W/m ﹒ k；
Wherein first matrix material and second matrix material is mixed to form composite, or first matrix material and should
One of second matrix material is embedded at one or more positions of another one.
2. electrode as claimed in claim 1, it is characterised in that the first surface of the electrode expose first matrix material and
Second matrix material.
3. electrode as claimed in claim 1, it is characterised in that at least a portion of first matrix material has porous even hole
Structure, second matrix material is filled in the porous even hole of pore structure.
4. electrode as claimed in claim 1, it is characterised in that first matrix material is provided with least one pit or through hole,
Second matrix material is arranged in the pit or through hole.
5. electrode as claimed in claim 1, it is characterised in that：Second matrix material is provided with least one pit or logical
Hole, first matrix material is arranged in the pit or through hole；Or second at least a portion of matrix material there is porous company
Pore structure, first matrix material is filled in the porous even hole of pore structure.
6. electrode as claimed in claim 1, it is characterised in that first matrix material is metal material or nonmetallic materials.
7. electrode as claimed in claim 6, it is characterised in that the metal material is the one kind in molybdenum, tungsten, iron-nickel alloy, or two
Kind or the mixture of two or more formation.
8. electrode as claimed in claim 6, it is characterised in that the nonmetallic materials are graphite, aluminum oxide ceramic, nitridation
Aluminium, beryllium oxide, one kind of carborundum, or two or more formed mixture.
9. electrode as claimed in claim 1, it is characterised in that second matrix material is the one kind in copper, aluminium, silver, gold, or
Two or more mixture for being formed, or be to include one or more the composite in copper, aluminium, silver, gold.
10. electrode as claimed in claim 1, it is characterised in that the electrode also includes metal level, the metal level cover this first
At least a portion of the outer surface of matrix material.
11. electrodes as claimed in claim 10, it is characterised in that the material of the metal level is copper, silver, gold, aluminium or nickel.
A kind of 12. chip-packaging structures, including：
Chip；And
One or more electrodes as described in claim any one of 1-11 being connected with the chip, wherein first matrix material
Pass through solder layer or be conductively connected thing with second matrix material to be connected with chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710059273.7A CN106783787A (en) | 2017-01-24 | 2017-01-24 | Electrode for chip package and the chip-packaging structure using the electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710059273.7A CN106783787A (en) | 2017-01-24 | 2017-01-24 | Electrode for chip package and the chip-packaging structure using the electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106783787A true CN106783787A (en) | 2017-05-31 |
Family
ID=58941937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710059273.7A Pending CN106783787A (en) | 2017-01-24 | 2017-01-24 | Electrode for chip package and the chip-packaging structure using the electrode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106783787A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4196442A (en) * | 1977-06-03 | 1980-04-01 | Hitachi, Ltd. | Semiconductor device |
| JPS55138275A (en) * | 1979-12-28 | 1980-10-28 | Fujitsu Ltd | Semiconductor device for high power |
| CN1685499A (en) * | 2002-09-27 | 2005-10-19 | Abb研究有限公司 | Press pack power semiconductor module |
| CN101350381A (en) * | 2007-07-18 | 2009-01-21 | 晶科电子（广州）有限公司 | Salient point LED and manufacturing method thereof |
| US20090121345A1 (en) * | 2007-10-30 | 2009-05-14 | Shinko Electric Industries Co., Ltd. | Silicon interposer producing method, silicon interposer and semiconductor device package and semiconductor device incorporating silicon interposer |
| CN103165782A (en) * | 2011-12-15 | 2013-06-19 | 铼钻科技股份有限公司 | Flip-chip light emitting diode and manufacturing method and application thereof |
| CN103871972A (en) * | 2014-03-31 | 2014-06-18 | 华为技术有限公司 | Flange, semiconductor power device and integrated circuit board |
| CN206742221U (en) * | 2017-01-24 | 2017-12-12 | 东莞市阿甘半导体有限公司 | Electrode for chip package and the chip-packaging structure using the electrode |
-
2017
- 2017-01-24 CN CN201710059273.7A patent/CN106783787A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4196442A (en) * | 1977-06-03 | 1980-04-01 | Hitachi, Ltd. | Semiconductor device |
| JPS55138275A (en) * | 1979-12-28 | 1980-10-28 | Fujitsu Ltd | Semiconductor device for high power |
| CN1685499A (en) * | 2002-09-27 | 2005-10-19 | Abb研究有限公司 | Press pack power semiconductor module |
| CN101350381A (en) * | 2007-07-18 | 2009-01-21 | 晶科电子（广州）有限公司 | Salient point LED and manufacturing method thereof |
| US20090121345A1 (en) * | 2007-10-30 | 2009-05-14 | Shinko Electric Industries Co., Ltd. | Silicon interposer producing method, silicon interposer and semiconductor device package and semiconductor device incorporating silicon interposer |
| CN103165782A (en) * | 2011-12-15 | 2013-06-19 | 铼钻科技股份有限公司 | Flip-chip light emitting diode and manufacturing method and application thereof |
| CN103871972A (en) * | 2014-03-31 | 2014-06-18 | 华为技术有限公司 | Flange, semiconductor power device and integrated circuit board |
| CN206742221U (en) * | 2017-01-24 | 2017-12-12 | 东莞市阿甘半导体有限公司 | Electrode for chip package and the chip-packaging structure using the electrode |
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