CN106783590A - 快反向恢复sj‑mos的方法及其器件结构 - Google Patents
快反向恢复sj‑mos的方法及其器件结构 Download PDFInfo
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract
本发明涉及快反向恢复SJ‑MOS的方法及其器件结构,在N+衬底上生长外延N‑;通过Trench光刻板,刻蚀出深沟槽;在沟槽表面生长一层浅掺杂的N‑ ‑;在N‑ ‑外延表面生长P+外延,使之填充满沟槽,并进行CMP工艺,将沟槽外的N‑ ‑及P型外延去掉,形成N柱P柱相交替的超结结构;通过Body光刻板注入体区并退火形成body区,淀积场氧化成并回刻,通过栅氧、多晶硅淀积回刻形成gate,再注入As或P并推阱形成Nsource;淀积ILD并回刻,孔注,最后淀积金属并回刻,形成器件的最终结构。本发明通过调整外延的掺杂浓度分布,达到减小少子存储电荷,加快反向恢复过程的目的,使得反向恢复时间明显减小。
Description
技术领域
本发明属于半导体功率器件技术领域,具体涉及一种快反向恢复SJ-MOS的方法及其器件结构。
背景技术
SJ-MOS的寄生体二极管从正向导通到反向截止需要一定的时间,因为正向导通时,由于多子扩散在pn结区内存储大量少子电荷,此时如果突然加上一个反向偏置,则由正向导通时产生的存储电荷就会形成反向电流,而将这些反向恢复电荷完全抽出或复合掉需要一定的时间,这一过程称为反向恢复过程,在这一过程中所用的时间称为反向恢复时间trr。低的反向恢复时间可以加快MOS管的关断时间,使器件适用于更高的工作频率。一般通过重金属掺杂或电子辐照来降低少子寿命,减小trr,但是这两种方式都会导致IDSS增加,且重金属掺杂工艺复杂,电子辐照成本较高。
发明内容
本发明的目的是提供一种快反向恢复SJ-MOS的方法及其器件结构,通过调整外延的掺杂浓度分布,达到减小少子存储电荷、加快反向恢复过程的目的。
本发明所采用的技术方案为:
快反向恢复SJ-MOS的方法,其特征在于:
包括以下步骤:
步骤一:在N+衬底上生长外延N-;
步骤二:通过Trench光刻板,刻蚀出深沟槽;
步骤三:在沟槽表面生长一层浅掺杂的N- -;
步骤四:随后,在N- -外延表面,生长P+外延,使之填充满沟槽,并进行CMP工艺,将沟槽外的N- -及P型外延去掉,形成N柱P柱相交替的超结结构;
步骤五:通过Body光刻板注入体区并退火形成body区,淀积场氧化成并回刻,通过栅氧、多晶硅淀积回刻形成gate,再注入As或P并推阱形成Nsource;
步骤六:淀积ILD并回刻,孔注,最后淀积金属并回刻,形成器件的最终结构。
步骤三中,在沟槽表面生长的浅掺杂的N- -,这层外延的掺杂浓度低于步骤一中的N型外延。
如所述的快反向恢复SJ-MOS的器件结构。
本发明具有以下优点:
本发明通过调整外延的掺杂浓度分布,达到减小少子存储电荷,加快反向恢复过程的目的, trr减小的同时, IDSS没有增加,击穿电压没有变化。
本发明使得反向恢复时间明显减小,且反向恢复软度未变化,通过二极管正向导通时的少子分布对比可以看到,本发明的少子存储电荷明显减少。
附图说明
图1为步骤一示意图。
图2为步骤二示意图。
图3为步骤三示意图。
图4为步骤四示意图。
图5为步骤五示意图。
图6为步骤六示意图。
图7为未做N- -外延器件的反向恢复特性对比。
图8为体二极管正向导通时的少子分布对比。
具体实施方式
下面结合具体实施方式对本发明进行详细的说明。
本发明涉及的快反向恢复SJ-MOS的方法,具体包括以下步骤:
1.在N+衬底上生长一定厚度的外延N-。(图1)
2.在通过Trench光刻板,刻蚀出深沟槽(图2)。
3.在沟槽表面生长一层浅掺杂的N- -,厚度约1um,这层外延的掺杂浓度低步骤1中的N型外延(图3)。
4.随后,在N--外延表面,生长一定浓度的P+外延,使之填充满沟槽,并进行CMP工艺,将沟槽外的N- -及P型外延去掉,形成N柱P柱相交替的超结结构(图4)。
5.通过Body光刻板注入体区并退火形成body区,淀积场氧化成并回刻,通过栅氧、多晶硅淀积回刻形成gate,再注入As(或P)并推阱形成Nsource(图5)。
6.淀积ILD并回刻,孔注,最后淀积金属并回刻,形成器件的最终结构(图6)。
上述方法通过调整外延的掺杂浓度分布,达到减小少子存储电荷,加快反向恢复过程的目的, trr减小的同时, IDSS没有增加,击穿电压没有变化。通过器件仿真,对比了相同情况下,未做N- -外延器件的反向恢复特性(图7),可以看到,本发明结构的反向恢复时间明显减小,且反向恢复软度未变化,通过二极管正向导通时的少子分布对比(图8)可以看到,本发明的少子存储电荷明显减少。
本发明的内容不限于实施例所列举,本领域普通技术人员通过阅读本发明说明书而对本发明技术方案采取的任何等效的变换,均为本发明的权利要求所涵盖。
Claims (3)
1.快反向恢复SJ-MOS的方法,其特征在于:
包括以下步骤:
步骤一:在N+衬底上生长外延N-;
步骤二:通过Trench光刻板,刻蚀出深沟槽;
步骤三:在沟槽表面生长一层浅掺杂的N- -;
步骤四:随后,在N- -外延表面,生长P+外延,使之填充满沟槽,并进行CMP工艺,将沟槽外的N- -及P型外延去掉,形成N柱P柱相交替的超结结构;
步骤五:通过Body光刻板注入体区并退火形成body区,淀积场氧化成并回刻,通过栅氧、多晶硅淀积回刻形成gate,再注入As或P并推阱形成Nsource;
步骤六:淀积ILD并回刻,孔注,最后淀积金属并回刻,形成器件的最终结构。
2.根据权利要求1所述的快反向恢复SJ-MOS的方法,其特征在于:
步骤三中,在沟槽表面生长的浅掺杂的N- -,这层外延的掺杂浓度低于步骤一中的N型外延。
3.如权利要求1所述的快反向恢复SJ-MOS的器件结构。
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CN109509792A (zh) * | 2018-10-12 | 2019-03-22 | 龙腾半导体有限公司 | 优化emi的超结mosfet版图结构及制造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030219933A1 (en) * | 2002-05-22 | 2003-11-27 | Shoichi Yamauchi | Semiconductor device having epitaxially-filled trench and method for manufacturing semiconductor device having epitaxially-filled trench |
US20090140327A1 (en) * | 2007-12-03 | 2009-06-04 | Takashi Hirao | Semiconductor device and manufacturing method of the same |
CN102403224A (zh) * | 2010-09-07 | 2012-04-04 | 上海华虹Nec电子有限公司 | 具有横向p-i-n结构的超结vdmos的制备方法 |
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US20030219933A1 (en) * | 2002-05-22 | 2003-11-27 | Shoichi Yamauchi | Semiconductor device having epitaxially-filled trench and method for manufacturing semiconductor device having epitaxially-filled trench |
US20090140327A1 (en) * | 2007-12-03 | 2009-06-04 | Takashi Hirao | Semiconductor device and manufacturing method of the same |
CN102403224A (zh) * | 2010-09-07 | 2012-04-04 | 上海华虹Nec电子有限公司 | 具有横向p-i-n结构的超结vdmos的制备方法 |
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CN109509792A (zh) * | 2018-10-12 | 2019-03-22 | 龙腾半导体有限公司 | 优化emi的超结mosfet版图结构及制造方法 |
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