CN106783570B - A kind of production method of high electron mobility transistor T-type grid - Google Patents
A kind of production method of high electron mobility transistor T-type grid Download PDFInfo
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- CN106783570B CN106783570B CN201611237056.4A CN201611237056A CN106783570B CN 106783570 B CN106783570 B CN 106783570B CN 201611237056 A CN201611237056 A CN 201611237056A CN 106783570 B CN106783570 B CN 106783570B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 31
- 238000002161 passivation Methods 0.000 claims abstract description 19
- 230000035807 sensation Effects 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 6
- 238000011161 development Methods 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 238000001704 evaporation Methods 0.000 claims abstract description 4
- 230000008020 evaporation Effects 0.000 claims abstract description 4
- 239000003292 glue Substances 0.000 claims description 14
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 claims description 3
- 229910015844 BCl3 Inorganic materials 0.000 claims description 2
- 238000005728 strengthening Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 12
- 238000010894 electron beam technology Methods 0.000 abstract description 6
- 230000008569 process Effects 0.000 abstract description 5
- 239000000853 adhesive Substances 0.000 abstract description 4
- 230000001070 adhesive effect Effects 0.000 abstract description 4
- 238000010923 batch production Methods 0.000 abstract 1
- 229910002601 GaN Inorganic materials 0.000 description 5
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The present invention provides a kind of production method of high electron mobility transistor T-type grid, comprising the following steps: S1, grows Si in transistor surface3N4Dielectric passivation layer；S2, high light sensation positive photoresist is uniformly smeared in dielectric passivation layer and is toasted；S3, it development is exposed to high light sensation positive photoresist using step printing mode forms the groove etched window of grid, and toasted；S4, etch media passivation layer formation grid slot, and remove high light sensation positive photoresist；S5, negtive photoresist is uniformly smeared in transistor surface, negtive photoresist is carried out to be lithographically formed grid cover lines；S6, evaporation grid metal and removing form grid.The present invention etches to adjust the characteristic size of target lines using step printing, contracting adhesive process and ICP-RIE, the grid line item that characteristic size is 0.1-0.5 μm can flexibly be made, compared with electron beam exposure mode, production efficiency is greatly promoted, and is suitable for batch production.
Description
Technical field
The invention belongs to technical field of manufacturing semiconductors, and in particular to a kind of system of high electron mobility transistor T-type grid
Make method.
Background technique
The distinctive high electron mobility of GaN high electron mobility transistor (HEMT), high two-dimensional electron gas surface density, high strike
Electric field is worn, so that it has higher power output density, is considered as the preferred skill of next-generation RF/Microwave power amplifier
Art.
With the sharp increase of field effect transistor (FET) frequency applications demand, device cutoff frequency f is promotedTJust seem
It is more important.
As the important parameter of characterization transistor high speed performance, device cutoff frequency fTApproximate formula are as follows:
Wherein vsFor the saturation migration rate of carrier, LgFor device grid length.As can be seen that cutoff frequency of the grid length to device
Rate has conclusive influence.
The grid length for reducing device is to promote the most straightforward approach of its frequency performance, but this method will lead to gate resistance simultaneously
Increase, gate resistance increase can deteriorate device noise performance, reduce device maximum oscillation frequency and reliability etc., the knot of T-type grid
Structure is studied personnel and is widely used due to can reduce gate resistance.In general, can consider to take when target grid length is less than 0.5 μm
T-type grid structure, and such a feature size usually alreadys exceed the technological limits of common litho machine, is typically exposed using electron beam
The mode of light is realized.
Hachure is made by the way of electron beam exposure and does not need production reticle, can be save in a set of reticle
The highest grid line engraving of grade, can save a part of plate-making expense.But electron beam exposure mode is high in addition to equipment manufacturing cost
In addition, maximum defect is that production efficiency is low, and production capacity often only has 10% or so of stepper, is difficult to meet
The demand of mass production.
Summary of the invention
The purpose of the present invention is to provide a kind of production method of high electron mobility transistor T-type grid, this method is fine
Ground solves the problems, such as low using electron beam exposure mode production efficiency.
To reach above-mentioned requirements, the present invention inscribes grid line item using step printing mode, then will by contracting adhesive process
Grid line size is adjusted to target value, and dielectric passivation layer under grid is then etched by the way of ICP-RIE, if needed can be into one
Step etches epitaxial layer to reinforce grid-control ability, removes photoresist exposure mask after this and makes grid cover again, can complete a whole set of T-type grid
Preparation.
This method specifically includes the following steps:
S1, Si is grown in transistor surface3N4Dielectric passivation layer；
S2, high light sensation positive photoresist is uniformly smeared in dielectric passivation layer and is toasted；
S3, it development is exposed to high light sensation positive photoresist using step printing mode forms the groove etched window of grid, and carry out
Baking；
S4, etch media passivation layer formation grid slot, and remove high light sensation positive photoresist；
S5, negtive photoresist is uniformly smeared in transistor surface, negtive photoresist is carried out to be lithographically formed grid cover lines；
S6, evaporation grid metal and removing form grid.
Compared with prior art, present invention has the advantage that
(1) it is etched using step printing, contracting adhesive process and ICP-RIE to adjust the characteristic sizes of target lines, it can be with
The flexibly grid line item that production characteristic size is 0.1-0.5 μm, compared with electron beam exposure mode, production efficiency is greatly promoted, and is fitted
For producing in batches；
(2) the method for the present invention technique has good implantable and operability, without increasing additional process costs,
Has very strong practicability.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present application, constitutes part of this application, at this
The same or similar part, the illustrative embodiments and their description of the application are indicated using identical reference label in a little attached drawings
For explaining the application, do not constitute an undue limitation on the present application.In the accompanying drawings:
Fig. 1-6 is the device architecture schematic diagram that each step of the present invention is formed.
Specific embodiment
To keep the purposes, technical schemes and advantages of the application clearer, below in conjunction with drawings and the specific embodiments, to this
Application is described in further detail.For the sake of simplicity, it is omitted that well known to a person skilled in the art certain skills in being described below
Art feature.
The present embodiment is by taking GaN high electron mobility transistor as an example, the production method of introducing its T-type grid.The gallium nitride
High electron mobility transistor includes SiC substrate and is located at AlGaN/GaN epitaxial layer above SiC substrate, and the device is completed
Source-drain electrode and isolation technology.The production method of its T-type grid the following steps are included:
S1, Si is grown in transistor surface3N4Dielectric passivation layer 1, dielectric passivation layer 1 with a thickness of
S2, high light sensation positive photoresist 2 is uniformly smeared in dielectric passivation layer 1, with a thickness of 0.4-0.7 μm；Using 100 DEG C of Vacuum Heats
Plate toasts the transistor for having smeared high light sensation positive photoresist 2, baking time 70-100s；
S3, high light sensation positive photoresist 2 is exposed using step printing mode, developing forms the groove etched window of grid, minimum
It can get characteristic size and be 0.4 μm of hachure, and toasted, baking temperature is 110-130 DEG C, baking time 60-
120s；The device architecture obtained after this step is as shown in Figure 1；
A, contracting glue is uniformly smeared in high light sensation positive photoresist 2, and is toasted twice, contracting glue and photoresist surface occurs anti-
Polymer 3 should be generated；The temperature of baking is 80-90 DEG C for the first time, time 60-90s；The temperature of second of baking is 100-
120 DEG C, time 60-90s；Contracting glue can react at a certain temperature with photoresist surface and generate polymer 3, not occur
The then washable removal of the part of reaction, the characteristic size of grid line item can be reduced using this step；Whether need using contracting glue work
Skill depends on the attainable lithographic accuracy of stepper institute, by taking lithographic accuracy is 0.4 μm as an example, if necessary to make grid length
It then no longer needs to introduce contracting adhesive process in 0.4 μm or more of lines；
B, cleaning removes extra contracting glue, and is toasted, and the temperature of baking is 110-120 DEG C, time 30-60s；This step
The device architecture obtained after rapid is as shown in Figure 2；
S4, grid slot 4 is formed from the groove etched opening etch dielectric passivation layer 1 of grid, and removes high light sensation positive photoresist 2；
S41, bottoming glue, rate20-30s；
CF is used in S42, ICP-RIE4Etch media passivation layer 1 forms grid slot 4, and etch rate 20-30nm/min is carved
Lose time 5-8min；The device architecture obtained after this step is as shown in Figure 3；
Cl is used in S43, ICP-RIE2And BCl3The AlGaN/GaN epitaxial layer of 1 lower section of etch media passivation layer, which is formed, to be reinforced
Slot 5, etch rate control in 5nm/min hereinafter, etching depth be 5-10nm, must ensure that epitaxy layer thickness must not be lower than 10nm；
The strengthening groove 5 of this step can reinforce grid-control ability, if need to etch epitaxial layer and depend on target grid length and grid to ditch track pitch
The ratio between from, if aforementioned proportion is greater than 10, without etching epitaxial layer；The device architecture obtained after this step is as shown in Figure 4；
S44, it uses concentration to clean 1-2min for 10% hydrochloric acid solution, removes bottom oxide.
S5, negtive photoresist 6 is uniformly smeared on transistor surface, 2.0-2.5 μm of thickness, negtive photoresist 6 is carried out to be lithographically formed grid cover
Lines, the width of grid cover are 0.8-1.5 μm；The device architecture obtained after this step is as shown in Figure 5；
S6, evaporation grid metal and removing form grid 7, grid metal Ni/Au, and Ni/Au=40-60/400-600nm；
Grid metal removing is carried out using NMP or acetone soln, splitting time 30-60min, the device architecture obtained after this step is as schemed
Shown in 6.
In above scheme, after the factor of adjustable T-type grid feature and size includes: high 2 exposure development of light sensation positive photoresist
Feature and size, contracting glue feature and size after contracting glue, Si3N4Feature and size after dielectric etch.Wherein, it makes
0.3-0.5 μm of lines need to only adjust the feature and size of high light sensation positive photoresist 2；0.2-0.3 μm of lines are made, need to adjust
Feature and size after high 2 exposure development of light sensation positive photoresist, and control feature and size of the contracting glue after contracting glue；And it makes
0.1-0.2 μm of lines need the above-mentioned all elements of comprehensive regulation.
Embodiment described above only indicates several embodiments of the invention, and the description thereof is more specific and detailed, but not
It can be interpreted as limitation of the scope of the invention.It should be pointed out that for those of ordinary skill in the art, not departing from
Under the premise of present inventive concept, various modifications and improvements can be made, these belong to the scope of the present invention.Therefore this hair
Bright protection scope should be subject to the claim.
Claims (8)
1. a kind of production method of high electron mobility transistor T-type grid, which comprises the following steps:
S1, Si is grown in transistor surface3N4Dielectric passivation layer；
S2, high light sensation positive photoresist is uniformly smeared in dielectric passivation layer and is toasted；
S3, it development is exposed to high light sensation positive photoresist using step printing mode forms the groove etched window of grid, and toasted；
S4, etch media passivation layer formation grid slot, and remove high light sensation positive photoresist；
S5, negtive photoresist is uniformly smeared in transistor surface, negtive photoresist is carried out to be lithographically formed grid cover lines；
S6, evaporation grid metal and removing form grid；
Step S4 is specifically included:
S41, bottoming glue；
S42, CF is used4Etch media passivation layer formation grid slot；
S43, using Cl2And BCl3Epitaxial layer below etch media passivation layer forms strengthening groove；
S44, concentration is used to remain for 10% hydrochloric acid solution cleaning removal bottom oxide.
2. the production method of high electron mobility transistor T-type grid according to claim 1, which is characterized in that the step
Before rapid S4 the following steps are included:
A, contracting glue is uniformly smeared in high light sensation positive photoresist, and is toasted twice, and contracting glue and photoresist surface is made to react life
At polymer；
B, cleaning removes extra contracting glue, and is toasted.
3. the production method of high electron mobility transistor T-type grid according to claim 1, which is characterized in that the step
Splitting time is 30-60min in rapid S6.
4. the production method of high electron mobility transistor T-type grid according to claim 2, which is characterized in that the step
The temperature toasted for the first time in rapid A is 80-90 DEG C, time 60-90s；The temperature of second of baking is 100-120 DEG C, the time
For 60-90s；The temperature toasted in step B is 110-120 DEG C, time 30-60s.
5. the production method of high electron mobility transistor T-type grid described in -4 any claims, feature exist according to claim 1
In, the dielectric passivation layer with a thickness of
6. the production method of high electron mobility transistor T-type grid described in -4 any claims, feature exist according to claim 1
In high light sensation positive photoresist with a thickness of 0.4-0.7 μm in the step S2.
7. the production method of high electron mobility transistor T-type grid described in -4 any claims, feature exist according to claim 1
In being toasted to transistor in the step S2 using 100 DEG C of vacuum hot plates, baking time 70-100s.
8. the production method of high electron mobility transistor T-type grid described in -4 any claims, feature exist according to claim 1
In the baking temperature in the step S3 is 110-130 DEG C, baking time 60-120s.
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| CN201611237056.4A CN106783570B (en) | 2016-12-28 | 2016-12-28 | A kind of production method of high electron mobility transistor T-type grid |
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| CN106783570B true CN106783570B (en) | 2019-10-11 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107293482B (en) * | 2017-06-14 | 2021-03-23 | 成都海威华芯科技有限公司 | Method for manufacturing gate electrode of gallium nitride high electron mobility transistor |
| CN107331608B (en) * | 2017-08-23 | 2020-11-24 | 成都海威华芯科技有限公司 | Manufacturing method of double-step T-shaped gate |
| CN108172512A (en) * | 2017-12-27 | 2018-06-15 | 成都海威华芯科技有限公司 | A kind of T-shaped grid preparation method for increasing silicon nitride medium angle of groove inclination degree |
| CN113078063B (en) * | 2021-02-08 | 2022-08-05 | 厦门市三安集成电路有限公司 | Structure for reducing heterojunction bipolar transistor b-c junction capacitance and manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101330010A (en) * | 2007-06-20 | 2008-12-24 | 中国科学院微电子研究所 | Method for manufacturing T-shaped HBT emitter/HEMT grid |
| CN101431020A (en) * | 2007-11-09 | 2009-05-13 | 上海华虹Nec电子有限公司 | Production method of T type polysilicon gate electrode |
| CN106229261A (en) * | 2016-09-12 | 2016-12-14 | 中山德华芯片技术有限公司 | A kind of method using epitaxial sacrificial layer technique to make the T-shaped grid of GaAs HEMT device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6962840B2 (en) * | 2002-09-11 | 2005-11-08 | Samsung Electronics Co., Ltd. | Method of forming MOS transistor |
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2016
- 2016-12-28 CN CN201611237056.4A patent/CN106783570B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101330010A (en) * | 2007-06-20 | 2008-12-24 | 中国科学院微电子研究所 | Method for manufacturing T-shaped HBT emitter/HEMT grid |
| CN101431020A (en) * | 2007-11-09 | 2009-05-13 | 上海华虹Nec电子有限公司 | Production method of T type polysilicon gate electrode |
| CN106229261A (en) * | 2016-09-12 | 2016-12-14 | 中山德华芯片技术有限公司 | A kind of method using epitaxial sacrificial layer technique to make the T-shaped grid of GaAs HEMT device |
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