CN107331608A - A kind of preparation method of the T-shaped grid of double step - Google Patents
A kind of preparation method of the T-shaped grid of double step Download PDFInfo
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- CN107331608A CN107331608A CN201710730784.7A CN201710730784A CN107331608A CN 107331608 A CN107331608 A CN 107331608A CN 201710730784 A CN201710730784 A CN 201710730784A CN 107331608 A CN107331608 A CN 107331608A
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- grid
- double step
- shaped grid
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 19
- 239000003292 glue Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 9
- 238000010422 painting Methods 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 238000004140 cleaning Methods 0.000 claims description 3
- 239000008367 deionised water Substances 0.000 claims description 3
- 229910021641 deionized water Inorganic materials 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 11
- 229910002601 GaN Inorganic materials 0.000 abstract description 3
- 238000001704 evaporation Methods 0.000 abstract description 3
- 230000008020 evaporation Effects 0.000 abstract description 3
- 238000001459 lithography Methods 0.000 abstract description 3
- 238000012545 processing Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 abstract description 2
- 208000002925 dental caries Diseases 0.000 abstract description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000010931 gold Substances 0.000 description 3
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
- H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a kind of preparation method of the T-shaped grid of double step, Si is grown on gallium nitride epitaxial materialses3N4, then by lithographic definition grid line bar, the Si exposed is etched in ICP RIE equipment by etch mask of photoresist3N4Medium, then, wafer is integrally even to apply contracting glue, make etching window feature size downsizing after processing, continue etch silicon nitride medium to semiconductor extension structure interface in ICP RIE cavitys again to stop, etch mask is removed afterwards, and even painting negtive photoresist or reversion glue make grid cover lines by lithography, and the evaporation stripped technique of grid metal just can form the T-shaped grid structure of double step.The T-shaped grid of double step are produced using the present invention, it is long both to have obtained less grid, smaller gate resistance can be obtained again, improved device cut-off frequency, help to obtain more preferable device performance；This method technique possesses good implantable and operability simultaneously, possesses very strong practicality.
Description
Technical field
The present invention relates to the preparation method of field of semiconductor processing and manufacturing, more particularly to a kind of T-shaped grid of double step.
Background technology
With the sharp increase of field-effect transistor (FET) frequency applications demand, boost device cut-off frequency fTSeem more
Send out important.
It is used as the important parameter for characterizing transistor high speed performance, device cut-off frequency fTApproximate formula be：
Wherein vsFor the saturation migration rate of carrier, LgIt is long for device gate.As can be seen that cutoff frequency of the grid length to device
Rate has conclusive influence.
The grid length for reducing device is the most straightforward approach for lifting its frequency performance, but this method can cause gate resistance simultaneously
Increase, gate resistance increase can deteriorate device noise performance, reduction device maximum oscillation frequency and reliability etc., the knot of T-shaped grid
Structure is due to that can reduce gate resistance and studied personnel are widely used.
T-shaped grid technique has the following disadvantages：(1) use electron beam lithography T-shaped grid, although part system can be save more
Copy fee is used, but beamwriter lithography machine cost is high, and production efficiency is low, and its production capacity often only has the 10% of stepper
Left and right, it is difficult to meet the demand of production in enormous quantities.(2) first, T-shaped grid technique gate resistance is still larger, there is further optimization
Space；
The content of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of preparation method of the T-shaped grid of double step.
The purpose of the present invention is achieved through the following technical solutions：Si is grown before device grid technique3N4Medium, is adopted
Exposed with positive photoresist, developing obtains etching window, dielectric etch is fallen by a part of left and right by ICP-RIE, contracting glue work is then used
Skill reduces etching window characteristic size, is subsequently etched off the medium of remainder thickness to semiconductor surface, next using negative
Glue exposure imaging defines grid cover, and evaporation grid metal peels off completion whole set process step again.Specifically：
A kind of preparation method of the T-shaped grid of double step, comprises the following steps：
S1：Device to completing source-drain electrode and isolation technology, surface passivation Si3N4Medium；
S2：Even painting high-res positive photoresist, and carry out front baking；
S3：It is exposed and is developed using stepper, and is toasted；
S4：In ICP-RIE, CF is used4And O2Etch away the Si of certain proportion thickness3N4Medium；
S5：It is even in positive photoresist to apply contracting glue, and front baking and rear baking are carried out respectively, reacted along positive photoresist edge and generate polymerization
Thing, reduces etching window；
S6：In ICP-RIE, CF is used4And O2Etch away remaining Si3N4Medium；
S7：Removed photoresist in nmp solution, and using IPA cleanings, hot N2Drying；；
S8：Even painting negtive photoresist, photoetching grid cover lines；
S9：Bottoming glue；
S10：Cleaned using finite concentration HCl solution；
S11：Evaporate grid metal；
S12：Peel off, form the T-shaped grid of double step.
Further, a step is also included between step S5 and S6：Cleaned with deionized water, removal does not react
Unnecessary contracting glue, and carry out after dry.
Further, described grid metal is Ni/Au.
Further, the certain proportion thickness described in step S4 is 40%-60%.
The beneficial effects of the invention are as follows：The present invention grows Si on gallium nitride epitaxial materialses3N4, then pass through lithographic definition
Grid line bar, the Si exposed is etched by etch mask of photoresist in ICP-RIE equipment3N4Medium, then, wafer are integrally even
Apply contracting glue, make etching window feature size downsizing after processing, then in ICP-RIE cavitys continuation etch silicon nitride medium to partly leading
External Yan Jiegoujiemianchu stops, and etch mask is removed afterwards, and even painting negtive photoresist or reversion glue make grid cover lines, evaporation grid gold by lithography
Belonging to stripped technique just can form the T-shaped grid structure of double step.The T-shaped grid of double step are produced using the present invention, can both obtain compared with
Small grid are long, and smaller gate resistance can be obtained again, improve device cut-off frequency, help to obtain more preferable device performance；Simultaneously
This method technique possesses good implantable and operability, possesses very strong practicality.
Brief description of the drawings
Fig. 1 is that step S3 is exposed and the schematic diagram after development；
Fig. 2 is that step S4 etches away certain thickness Si3N4The schematic diagram of medium；
Fig. 3 is to form the schematic diagram of less etching window after the completion of step S5；
Fig. 4 is that step S6 etches away remaining thickness Si3N4The schematic diagram of medium；
Fig. 5 is the grid cover lines schematic diagram that step S8 is obtained；
Fig. 6 is the T-shaped grid schematic diagram of double step that finally gives after the completion of step S12.
Embodiment
Technical scheme is described in further detail below in conjunction with the accompanying drawings：A kind of preparation method of the T-shaped grid of double step,
Comprise the following steps：
S1：Device to completing source-drain electrode and isolation technology, surface passivation Si3N4Medium, its thickness of the medium is
S2：Even painting high-res positive photoresist, thickness is 0.4-0.7 μm, and carries out front baking, using 100 DEG C of vacuum hot plates, 90s
Realize；
S3：It is exposed and is developed using stepper, it is minimum to obtain the hachure that characteristic size is 0.4 μm,
110-130 DEG C of baking 60-120s；Exposure with develop after result it is as shown in Figure 1；
S4：In ICP-RIE, CF is used4And O2(6:1-10:1) Si of 40%-60% thickness is etched away3N4Medium, ICP
Power is 50-100W, and Bias power are 10-20W, and pressure is 2-5mT, and etch rate is 20-30nm/min；In this implementation
In example, 50% thickness dielectric is etched, as shown in Figure 2；
S5：It is even in positive photoresist to apply rear baking 60-90s at front baking 60-90s at contracting glue, 80-90 DEG C, 100-120 DEG C, along positive photoresist
Edge reacts generation polymer, reduces etching window；Afterwards, cleaned with deionized water, it is unnecessary that removal does not react
Contracting glue to reduce etching window size to 0.15-0.25 μm, and at 110-120 DEG C after dry 30-60s；As shown in Figure 3；
S6：In ICP-RIE, CF is used4And O2(6:1-10:1) remaining Si is etched away3N4Medium, ICP power are
50-100W, Bias power are 10-20W, and pressure is 2-5mT, and etch rate is 20-30nm/min；In the present embodiment, carve
Lose remaining 50% thickness dielectric；After the completion of etching, GaN epitaxy surface is exposed, as shown in Figure 4；
S7：Removed photoresist in nmp solution, and using IPA cleanings, hot N2Drying；
S8：Even painting negtive photoresist, 2.0-2.5 μm of thickness, then photoetching grid cover lines, the width of grid cover is 0.8-1.5 μm；Such as Fig. 5
It is shown；
S9：Bottoming glue, speed20-30s；
S10：1-2min is cleaned using 10%HCl；
S11：Evaporate grid metal (Ni/Au=40-60/400-600nm)；
S12：Peel off, form the T-shaped grid of double step, as shown in Figure 6.
Claims (4)
1. a kind of preparation method of the T-shaped grid of double step, it is characterised in that：Comprise the following steps：
S1：Device to completing source-drain electrode and isolation technology, surface passivation Si3N4Medium；
S2：Even painting high-res positive photoresist, and carry out front baking；
S3：It is exposed, developed using stepper, and is toasted；
S4：In ICP-RIE, CF is used4And O2Etch away the Si of certain proportion thickness3N4Medium；
S5：The even painting contracting glue in positive photoresist, and carry out front baking and rear baking respectively, reacts generation polymer along positive photoresist edge, contracts
Small etching window；
S6：In ICP-RIE, CF is used4And O2Etch away remaining Si3N4Medium；
S7：Removed photoresist in nmp solution, and using IPA cleanings, hot N2Drying；
S8：Even painting negtive photoresist, photoetching grid cover lines；
S9：Bottoming glue；
S10：Cleaned using finite concentration HCl solution；
S11：Evaporate grid metal；
S12：Peel off, form the T-shaped grid of double step.
2. a kind of preparation method of the T-shaped grid of double step according to claim 1, it is characterised in that：Step S5 and S6 it
Between also include step：Cleaned with deionized water, remove and dried after the unnecessary contracting glue not reacted, and progress.
3. a kind of preparation method of the T-shaped grid of double step according to claim 1, it is characterised in that：Described grid metal is
Ni/Au。
4. a kind of preparation method of the T-shaped grid of double step according to claim 1, it is characterised in that：Described in step S4
Certain proportion thickness is 40%-60%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710730784.7A CN107331608B (en) | 2017-08-23 | 2017-08-23 | Manufacturing method of double-step T-shaped gate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710730784.7A CN107331608B (en) | 2017-08-23 | 2017-08-23 | Manufacturing method of double-step T-shaped gate |
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| Publication Number | Publication Date |
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| CN107331608A true CN107331608A (en) | 2017-11-07 |
| CN107331608B CN107331608B (en) | 2020-11-24 |
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| CN201710730784.7A Active CN107331608B (en) | 2017-08-23 | 2017-08-23 | Manufacturing method of double-step T-shaped gate |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108172512A (en) * | 2017-12-27 | 2018-06-15 | 成都海威华芯科技有限公司 | A kind of T-shaped grid preparation method for increasing silicon nitride medium angle of groove inclination degree |
| CN108172511A (en) * | 2017-12-27 | 2018-06-15 | 成都海威华芯科技有限公司 | A kind of T-shaped grid preparation method for having air ditch structure |
| CN111092012A (en) * | 2018-10-24 | 2020-05-01 | 东莞新科技术研究开发有限公司 | Semiconductor cleaning method |
| CN112002641A (en) * | 2020-07-21 | 2020-11-27 | 中电科工程建设有限公司 | Method for manufacturing grid of GaN power device for 5G communication |
| CN112992668A (en) * | 2021-04-26 | 2021-06-18 | 度亘激光技术（苏州）有限公司 | Processing method of semiconductor structure and semiconductor structure |
| CN113690132A (en) * | 2021-07-30 | 2021-11-23 | 华南理工大学 | double-T-shaped gate preparation method based on double-layer passivation precise etching |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569047A (en) * | 2010-12-07 | 2012-07-11 | 中国科学院微电子研究所 | Method for preparing T-shaped gate on indium phosphide substrate |
| CN102569046A (en) * | 2010-12-07 | 2012-07-11 | 中国科学院微电子研究所 | Method for preparing T-shaped gate on indium phosphide substrate |
| CN102598275A (en) * | 2009-08-28 | 2012-07-18 | 特兰斯夫公司 | Semiconductor devices with field plates |
| US20130146944A1 (en) * | 2011-12-13 | 2013-06-13 | Electronics And Telecommunications Research Institute | Semiconductor device including stepped gate electrode and fabrication method thereof |
| US20140097471A1 (en) * | 2007-01-10 | 2014-04-10 | International Rectifier Corporation | Active Area Shaping of III-Nitride Devices Utilizing A Field Plate Defined By A Dielectric Body |
| CN104218079A (en) * | 2013-06-03 | 2014-12-17 | 瑞萨电子株式会社 | Semiconductor device and method of manufacturing a semiconductor device |
| CN104701154A (en) * | 2015-03-11 | 2015-06-10 | 北京工业大学 | Preparation method for sub-half-micron T-shaped gate via chemical shrinkage method |
| CN105164811A (en) * | 2013-02-15 | 2015-12-16 | 创世舫电子有限公司 | Electrodes for semiconductor devices and methods of forming the same |
| CN106783570A (en) * | 2016-12-28 | 2017-05-31 | 成都海威华芯科技有限公司 | A kind of preparation method of the T-shaped grid of HEMT |
-
2017
- 2017-08-23 CN CN201710730784.7A patent/CN107331608B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140097471A1 (en) * | 2007-01-10 | 2014-04-10 | International Rectifier Corporation | Active Area Shaping of III-Nitride Devices Utilizing A Field Plate Defined By A Dielectric Body |
| CN102598275A (en) * | 2009-08-28 | 2012-07-18 | 特兰斯夫公司 | Semiconductor devices with field plates |
| CN102569047A (en) * | 2010-12-07 | 2012-07-11 | 中国科学院微电子研究所 | Method for preparing T-shaped gate on indium phosphide substrate |
| CN102569046A (en) * | 2010-12-07 | 2012-07-11 | 中国科学院微电子研究所 | Method for preparing T-shaped gate on indium phosphide substrate |
| US20130146944A1 (en) * | 2011-12-13 | 2013-06-13 | Electronics And Telecommunications Research Institute | Semiconductor device including stepped gate electrode and fabrication method thereof |
| CN105164811A (en) * | 2013-02-15 | 2015-12-16 | 创世舫电子有限公司 | Electrodes for semiconductor devices and methods of forming the same |
| CN104218079A (en) * | 2013-06-03 | 2014-12-17 | 瑞萨电子株式会社 | Semiconductor device and method of manufacturing a semiconductor device |
| CN104701154A (en) * | 2015-03-11 | 2015-06-10 | 北京工业大学 | Preparation method for sub-half-micron T-shaped gate via chemical shrinkage method |
| CN106783570A (en) * | 2016-12-28 | 2017-05-31 | 成都海威华芯科技有限公司 | A kind of preparation method of the T-shaped grid of HEMT |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108172512A (en) * | 2017-12-27 | 2018-06-15 | 成都海威华芯科技有限公司 | A kind of T-shaped grid preparation method for increasing silicon nitride medium angle of groove inclination degree |
| CN108172511A (en) * | 2017-12-27 | 2018-06-15 | 成都海威华芯科技有限公司 | A kind of T-shaped grid preparation method for having air ditch structure |
| CN108172511B (en) * | 2017-12-27 | 2020-11-24 | 成都海威华芯科技有限公司 | Manufacturing method of T-shaped grid with air channel structure |
| CN111092012A (en) * | 2018-10-24 | 2020-05-01 | 东莞新科技术研究开发有限公司 | Semiconductor cleaning method |
| CN112002641A (en) * | 2020-07-21 | 2020-11-27 | 中电科工程建设有限公司 | Method for manufacturing grid of GaN power device for 5G communication |
| CN112992668A (en) * | 2021-04-26 | 2021-06-18 | 度亘激光技术（苏州）有限公司 | Processing method of semiconductor structure and semiconductor structure |
| CN112992668B (en) * | 2021-04-26 | 2021-08-06 | 度亘激光技术（苏州）有限公司 | Processing method of semiconductor structure and semiconductor structure |
| CN113690132A (en) * | 2021-07-30 | 2021-11-23 | 华南理工大学 | double-T-shaped gate preparation method based on double-layer passivation precise etching |
| WO2023006036A1 (en) * | 2021-07-30 | 2023-02-02 | 华南理工大学 | Double t-shaped gate preparation method based on double-layer passivation and accurate etching |
| CN113690132B (en) * | 2021-07-30 | 2024-04-19 | 华南理工大学 | Double-layer passivation accurate etching-based preparation method of double-T-shaped gate |
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