CN106774581B - Low pressure difference linear voltage regulator and integrated system-on-chip - Google Patents
Low pressure difference linear voltage regulator and integrated system-on-chip Download PDFInfo
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- CN106774581B CN106774581B CN201710056684.0A CN201710056684A CN106774581B CN 106774581 B CN106774581 B CN 106774581B CN 201710056684 A CN201710056684 A CN 201710056684A CN 106774581 B CN106774581 B CN 106774581B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
This application discloses low pressure difference linear voltage regulator and integrated system-on-chips.The voltage supplied that the low pressure difference linear voltage regulator is used to provide feeder ear is converted into the output voltage of output end, comprising: base modules, for generating bias current and bandgap voltage reference；Amplification module, for output voltage to be compared with the bandgap voltage reference, to obtain the error signal of the two；And output module, for controlling the voltage drop of adjustment pipe according to error signal, to stabilize the output voltage.The output module includes the first transistor and second transistor being connected in series between the feeder ear and ground terminal, and the intermediate node of the two provides the output voltage as the output end.The low pressure difference linear voltage regulator can built-in compensating electric capacity, reduction volume and power consumption and the driving capability for improving capacitive load.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly, to the low pressure difference linearity for being used for integrated system-on-chip (SOC)
Voltage-stablizer (LDO) circuit.
Background technique
Integrated system-on-chip (SOC) is the system of integrated processor, memory and major peripheral circuit in one single chip.
For example, SOC can be single-chip wireless system, including multiple analog circuits and multiple digital circuit blocks to be used for, for providing
The major function of function of Bluetooth communication and mobile communication.Due to the functional completeness and efficient Integrated Trait of SOC, SOC is various
It is widely used in electronic product.
The suspend mode of lower power consumption is provided in the chip design of SOC, to guarantee the low power consumption of electronic product.However,
In suspend mode, it is also necessary to the work of a part of digital circuit is maintained, to maintain the state of Digital Logic.SOC chip is
Supply voltage of uniting is higher than the operating voltage of digital circuit.Therefore, low pressure difference linear voltage regulator (LDO) circuit is used in SOC chip
System power supply voltage is converted into the operating voltage of digital circuit.LDO circuit maintains the power supply of digital circuit in the hibernation mode.
For the conventional architectures of LDO circuit, low-power consumption and small area are unavoidably two factors mutually restricted.
Fig. 1 shows a kind of schematic circuit of the LDO circuit according to prior art.The LDO circuit 100 includes benchmark mould
Block 110, amplification module 120, output module 130 and compensating module 140.Base modules 110 include band-gap reference circuit (BGR)
111 and biasing circuit 112, it is respectively configured to provide reference voltage and bias current.Amplification module 120 includes operational amplifier U1,
For the feedback signal of output voltage Vout to compare with reference voltage, to obtain the error signal of the two.Output module 130
Adjustment pipe Q1 and resistance R1 and R2 including series connection.The output end of the adjustment pipe provides output voltage Vout, resistance R1 and
R2 forms potential-divider network to obtain the feedback signal of output voltage.The voltage drop that pipe controls adjustment pipe according to error signal is adjusted,
To stabilize the output voltage Vout.Compensating module 140 includes concatenated capacitor Co and resistance Ro, such as piece of compensating module 140
Outer capacitor and its dead resistance are connected in series, and form a pole and zero to play the role of stablizing compensation.
The band-gap reference circuit 111 used in LDO circuit can be realized using a variety of frameworks.Fig. 2 shows shown in Fig. 1
A kind of schematic circuit of band-gap reference circuit used in LDO circuit.The band-gap reference circuit 111 includes 3 metal oxygens
Compound semiconductor field effect transistor (MOSFET) M1 to M3,10 bipolar transistor B1 to B3, an operational amplifier U11 and
Two resistance R11 and R21, wherein bipolar transistor B2 includes one group of totally 8 bipolar transistor.During LDO circuit work, fortune
A large amount of electric energy will be consumed by calculating amplifier and transistor.Fig. 3 shows another kind band gap base used in LDO circuit shown in Fig. 1
The schematic circuit of quasi- circuit.The band-gap reference circuit 111 includes 5 MOSFET MP1 to MP3 and MN1, MN2,10 couples
Gated transistors B1 to B3 and two resistance R11 and R21, wherein bipolar transistor B2 includes one group of totally 8 bipolar transistor.The band
Gap reference circuit 111 eliminates an operational amplifier U11, is suitble to the application of extensive uA rank power consumption requirements, but for super
For low-power consumption (nA rank power consumption performance) application, resistance can occupy huge area, substantially be unsatisfactory for actual product demand.
In addition, the adjustment pipe of output module 130 mostly uses greatly p-type power transistor in existing LDO circuit.Using P
High amplifier gain and low supply voltage is more easily done in type power transistor, but when for super low-power consumption, will cause ring instead
Road is unstable, especially needs to reach several hundred pf and load current again under the application environment of very little in capacitive load, substantially can not
The demand of stability can be realized under nA rank power consumption.
Therefore, it is intended that further decreasing the volume and power consumption of LDO circuit, and the driving capability of capacitive load is improved, from
And it reduces cost and improves the market competitiveness.
Summary of the invention
In view of the above problems, the purpose of the invention is to provide a kind of low pressure difference linear voltage regulators, wherein using novelty
Circuit structure be able to built-in compensating electric capacity, reduce volume and power consumption and improve capacitive load driving capability.
According to the first aspect of the invention, a kind of low pressure difference linear voltage regulator is provided, the power supply for providing feeder ear
Voltage is converted into the output voltage of output end, comprising: base modules, for generating bias current and bandgap voltage reference；Amplification
Module is connected with the base modules, for output voltage to be compared with the bandgap voltage reference, to obtain the two
Error signal；And output module, it is connected with the amplification module, for controlling the voltage of adjustment pipe according to error signal
Drop, to stabilize the output voltage, wherein the output module includes: to be connected in series between the feeder ear and ground terminal
The control terminal of the first transistor and second transistor, the first transistor receives the error signal, the second transistor
The bias current is obtained from the amplification module using mirror-image fashion, to provide the biased electrical for the first transistor
The intermediate node of stream, the first transistor and the second transistor provides the output voltage as the output end.
Preferably, the base modules include: the third transistor being connected in series between the feeder ear and ground terminal,
4th transistor and at least one the 5th transistor；And it is connected in series in the 6th crystal between the feeder ear and ground terminal
Pipe, the 7th transistor, resistance and at least one the 8th transistor, wherein the third transistor and the 6th transistor constitute electricity
Mirror is flowed, the 4th transistor and the 7th transistor constitute current mirror, at least one described the 5th transistor is connected in parallel with each other,
At least one described the 8th transistor is connected in parallel with each other, also, at least one described the 5th transistor and it is described at least one
The control terminal of 8th transistor is connected to each other and is grounded, and the reference current flows through the 6th transistor.
Preferably, the quantity ratio of at least one described the 5th transistor and at least one the 8th transistor is greater than 1:8
And it is less than or equal to 1:1.
Preferably, the base modules further include: the 9th crystal being connected in series between the feeder ear and ground terminal
Pipe, the tenth transistor and the 11st transistor, wherein the 9th transistor and the 6th transistor constitute current mirror, from
And the reference current is obtained, the tenth transistor connects into diode structure, the control termination of the 11st transistor
The intermediate node of ground, the 9th transistor and the tenth transistor provides the bandgap voltage reference.
Preferably, it by the way that the proportionate relationship of the breadth length ratio of the 9th transistor and the 6th transistor is arranged, obtains
The bandgap voltage reference of required numerical value.
Preferably, the numberical range of the bandgap voltage reference is 1V to 1.8V.
Preferably, the third transistor, the 6th transistor, the 9th transistor are respectively the metal oxygen of p-type
Compound semiconductor field effect transistor, the first transistor, the second transistor, the 4th transistor, the described 7th
Transistor is respectively the Metal Oxide Semiconductor Field Effect Transistor of N-type, and the tenth transistor is the metal of N-type or p-type
Oxide semiconductor field effect transistor, the 5th transistor, the 8th transistor and the 11st transistor difference
For positive-negative-positive bipolar transistor.
Preferably, the amplification module includes: operational amplifier, and the non-inverting input terminal and reverse phase of the operational amplifier are defeated
Enter end and receive the bandgap voltage reference and the output voltage respectively, output end provides the error signal.
Preferably, the amplification module further include: the 12nd be connected in series between the feeder ear and ground terminal is brilliant
Body pipe and the 13rd transistor, wherein the tenth two-transistor is obtained using mirror-image fashion from the base modules described inclined
Set electric current.
Preferably, the second transistor and the 13rd transistor form current mirror.
Preferably, the tenth two-transistor be p-type Metal Oxide Semiconductor Field Effect Transistor, the described 13rd
Transistor is the Metal Oxide Semiconductor Field Effect Transistor of N-type.
Preferably, further includes: compensating module is connected with the amplification module, for compensating the output voltage,
In, the compensating module includes the 14th crystalline substance of the series connection between the feeder ear and the output end of the amplification module
Body pipe and capacitor, the 14th transistor work in linear zone and make to play compensation as compensation resistance and the capacitor
With.
Preferably, the 14th transistor is the Metal Oxide Semiconductor Field Effect Transistor of p-type.
According to the second aspect of the invention, a kind of base modules are provided, comprising: be connected in series in the feeder ear and ground connection
Third transistor, the 4th transistor and at least one the 5th transistor between end；And be connected in series in the feeder ear and
The 6th transistor, the 7th transistor, resistance and at least one the 8th transistor between ground terminal, wherein the third crystal
Pipe and the 6th transistor constitute current mirror, and the 4th transistor and the 7th transistor constitute current mirror, it is described at least one the
Five transistors are connected in parallel with each other, at least one described the 8th transistor is connected in parallel with each other, also, it is described at least one the 5th
The control terminal of transistor and at least one the 8th transistor is connected to each other and is grounded, and the reference current flows through the described 6th
Transistor.
Preferably, the quantity ratio of at least one described the 5th transistor and at least one the 8th transistor is greater than 1:8
And it is less than or equal to 1:1.
Preferably, the base modules further include: the 9th crystal being connected in series between the feeder ear and ground terminal
Pipe, the tenth transistor and the 11st transistor, wherein the 9th transistor and the 6th transistor constitute current mirror, from
And the reference current is obtained, the tenth transistor connects into diode structure, the control termination of the 11st transistor
The intermediate node of ground, the 9th transistor and the tenth transistor provides the bandgap voltage reference.
Preferably, it by the way that the proportionate relationship of the breadth length ratio of the 9th transistor and the 6th transistor is arranged, obtains
The bandgap voltage reference of required numerical value.
Preferably, the numberical range of the bandgap voltage reference is 1V to 1.8V.
Preferably, the third transistor, the 6th transistor, the 9th transistor are respectively the metal oxygen of p-type
Compound semiconductor field effect transistor, the first transistor, the second transistor, the 4th transistor, the described 7th
Transistor is respectively the Metal Oxide Semiconductor Field Effect Transistor of N-type, and the tenth transistor is the metal of N-type or p-type
Oxide semiconductor field effect transistor, the 5th transistor, the 8th transistor and the 11st transistor difference
For positive-negative-positive bipolar transistor.
According to the third aspect of the invention we, a kind of integrated system-on-chip is provided, comprising: processor；Memory；Peripheral electricity
Road；And above-mentioned low pressure difference linear voltage regulator, for powering for the processor and the memory.
Low pressure difference linear voltage regulator according to an embodiment of the present invention, output module include be connected in series in the feeder ear and
The first transistor and second transistor between ground terminal, second transistor provide the bias current for the first transistor, the
The intermediate node of one transistor and the second transistor provides output voltage as output end.Using work in linear zone
Second transistor replaces the compensation resistance in existing structure to reduce domain while can achieve the super low-power consumption of nA rank
Area occupied.
In a preferred embodiment, in the output module of low pressure difference linear voltage regulator, the first transistor uses N-type
MOSFET, instead of the p-type MOSFET in conventional architectures.Since the source electrode of N-type MOSFET exports, low pressure difference linear voltage regulator
Output resistance greatly reduce, compensated so as to realize in piece, and reach under nA rank power consumption realize stability need
It asks.
The low pressure difference linear voltage regulator can built-in compensating electric capacity, realize operating current down to 200nA, domain realizes area
Less than 0.04mm2.Due to holding without outer contact pin dispatch from foreign news agency, the pin resource of a chip can be saved, and capacitive load capacity reaches
To 1nF, the application requirement that SOC powers to internal logic can satisfy.Thus, which has the extremely strong market competitiveness.
In a further preferred embodiment, in the base modules of low pressure difference linear voltage regulator, it can reduce current mirror
The quantity ratio of middle transistor, and transistor is connected into diode structure to generate bandgap voltage reference, to correspondingly subtract
The numerical value of small resistance and its area occupied of domain.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1 shows the schematic circuit of LDO circuit according to prior art.
Fig. 2 shows a kind of schematic circuits of band-gap reference circuit used in LDO circuit shown in Fig. 1.
Fig. 3 shows the schematic circuit of another kind band-gap reference circuit used in LDO circuit shown in Fig. 1.
Fig. 4 shows the schematic diagram of base modules according to a first embodiment of the present invention.
Fig. 5 shows a kind of example schematic circuit of base modules according to a first embodiment of the present invention.
Fig. 6 shows another example schematic circuit of base modules according to a first embodiment of the present invention.
Fig. 7 shows the schematic circuit of LDO circuit according to a second embodiment of the present invention.
Fig. 8 shows the schematic circuit of operational amplifier used in LDO circuit shown in Fig. 7.
Fig. 9 shows the working waveform figure of LDO circuit according to a second embodiment of the present invention.
Figure 10 shows the corresponding phase margin waveform of output load capacitance of LDO circuit according to a second embodiment of the present invention
Figure.
Specific embodiment
The various embodiments that the present invention will be described in more detail that hereinafter reference will be made to the drawings.In various figures, identical element
It is indicated using same or similar appended drawing reference.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.
In this application, MOSFET includes first end, second end and control terminal, in the on state of MOSFET, electric current from
First end flow to second end.First end, second end and the control terminal of p-type MOSFET is respectively source electrode, drain and gate, N-type
First end, second end and the control terminal of MOSFET is respectively drain electrode, source electrode and grid.Bipolar transistor includes first end, second
End and control terminal, in the on state of bipolar transistor, electric current flow to second end from first end.The of positive-negative-positive bipolar transistor
One end, second end and control terminal are respectively emitter, collector and base stage, the first end of npn type bipolar transistor, second end and
Control terminal is respectively collector, emitter and base stage.
Present invention will be further explained below with reference to the attached drawings and examples.
Fig. 4 shows the schematic diagram of base modules according to a first embodiment of the present invention.As shown in figure 4, the base modules 210
Including current mirror 2101, operational amplifier 2102, pressure difference generation circuit 2103, pressure stream conversion circuit 2104 and stream pressure conversion
Circuit 2105.
The schematic circuit of the different instances of base modules according to a first embodiment of the present invention is shown respectively in Figures 5 and 6.
As shown in figure 5, current mirror 2101 include p-type MOSFET MP1 to MP3, operational amplifier 2102 include N-type MOSFET MN1 and
MN2, pressure difference generation circuit 2103 include bipolar transistor B1 and B2, and pressure stream conversion circuit 2104 includes resistance R11, stream pressure conversion
Circuit 2105 includes N-type MOSFET MN3 and bipolar transistor B3.The difference of example shown in Fig. 6 and example shown in Fig. 5 is, flows
Voltage conversion circuit 2105 includes p-type MOSFET MP6 and bipolar transistor B3, and then the two is identical for other aspects.
Referring to fig. 4 with 5, an output end of current mirror 2101, i.e. the drain electrode of p-type MOSFET MP1, with operational amplifier
2102 offset side is connected, and provides the bias current of operational amplifier 2102.Meanwhile the bias current passes through operational amplifier
2102 N-type MOSFET MN1 flows into the emitter of bipolar transistor B1, and the electric current as pressure difference generation circuit 2103 inputs.
The non-inverting input terminal of operational amplifier 2102, the i.e. source electrode of N-type MOSFET MN1, with pressure difference generation circuit 2103
One output end, the i.e. emitter of bipolar transistor B1 are connected.The inverting input terminal of operational amplifier 2102, i.e. N-type
The source electrode of MOSFET MN2, the output end with pressure stream conversion circuit 2104, i.e. one end of resistance R11 is connected.Operational amplifier
One output end of 2102 output end, the i.e. drain electrode of N-type MOSFET MN2 and current mirror 2101, i.e. p-type MOSFET MP2's
Drain and gate is connected.
The input terminal of pressure stream conversion circuit 2104, the i.e. other end of resistance R11, it is defeated with one of pressure difference generation circuit 2103
The emitter of outlet, i.e. bipolar transistor B2 is connected.The base stage of bipolar transistor B1 and B2 in pressure difference generation circuit 2103
It is all connected to the ground with collector.
The another output of current mirror 2101, i.e. draining for p-type MOSFET MP3 are defeated with stream voltage conversion circuit 2105
Enter end, i.e. the drain and gate of N-type MOSFET MN3 is connected, and provides bandgap voltage reference VBG1.Flow voltage conversion circuit
The source electrode of 2105 N-type MOSFET MN3 is connected with the emitter of bipolar transistor B3.It flows double in voltage conversion circuit 2105
The base stage and collector of gated transistors B3 is all connected to the ground.
As shown in figure 5, p-type MOSFET MP1, N-type MOSFET MN1 and bipolar transistor B1 are connected in series in supply voltage
Between AVDD and ground AGND.In the on state of three, electric current is via p-type MOSFET MP1, N-type MOSFET MN1 and bipolar crystalline substance
Body pipe B1 flow to ground AGND from feeder ear.
P-type MOSFET MP2, N-type MOSFET MN2, resistance R11 and bipolar transistor B2 are connected in series in supply voltage
Between AVDD and ground AGND.In the on state of three transistors, electric current via p-type MOSFET MP2, N-type MOSFET MN2,
Resistance R11 and bipolar transistor B2 flow to ground AGND from feeder ear.
P-type MOSFET MP3, N-type MOSFET MN3 and bipolar transistor B3 are connected in series in supply voltage AVDD and ground
Between AGND.In the on state of three, electric current via p-type MOSFET MP3, N-type MOSFET MN3 and bipolar transistor B3,
Ground AGND is flow to from feeder ear.
The grid of p-type MOSFET MP1, MP2 and MP3 are connected to each other, and are connected to the drain electrode of p-type MOSFET MP2, that
This forms mirrored transistor.The breadth length ratio of p-type MOSFET MP1 and MP2 are set as equal, guarantee that the electric current flowed through is equal.P-type
The breadth length ratio of MOSFET MP2 and MP3 are configured according to the desired value of bandgap voltage reference VBG1.
The grid of N-type MOSFET MN1 and MN2 are connected to each other, and are connected to the drain electrode of N-type MOSFET MN1, each other shape
It is mirrored into transistor.The breadth length ratio of N-type MOSFET MN1 and MN2 are set as equal, guarantee that the electric current flowed through is equal.
The base stage of bipolar transistor B1 and B2 are connected to each other, and are further grounded AGND.The base stage of bipolar transistor B3
It is connected to each other with collector, and is further grounded AGND.
The grid of N-type MOSFET MN3 and drain electrode connect, and form diode structure.
Alternatively, as shown in fig. 6, the grid of p-type MOSFET MP6 and drain electrode connect, diode structure is formed.
In this embodiment, bias current and bandgap voltage reference VBG1 needed for base modules 210 generate LDO circuit.
Since p-type MOSFET MP1 and MP2 constitute mirrored transistor, N-type MOSFET MN1 and MN2 constitute mirrored transistor, therefore, N
The voltage VB of the source electrode of the voltage VA and MN2 of the source electrode of type MOSFET MN1 is equal.
The bias current that base modules 210 generate:
IB1=IB2=(VB-VBE (B2))/R=(VBE (B1)-VBE (B2))/R (1)
VBE=VTln(IB/ISB) (2)
N*ISB1=ISB2 (3)
In conjunction with above formula, obtain:
IB1=IB2=VTlnN/R (4)
Wherein, ISB1, ISB2 are the saturation current of bipolar transistor B1, bipolar transistor B2, and VBE is bipolar transistor
The base-emitter voltage of B1, bipolar transistor B2, N are the number ratio of bipolar transistor B1 and bipolar transistor B2, VTNormal
The lower about 26mV of temperature, R is the resistance value of resistance R11.
The band-gap reference circuit of the prior art shown in many aspects and Fig. 2 and 3 of the band-gap reference circuit of the embodiment
It is different.
The first aspect of the embodiment is, in band-gap reference circuit 210, bipolar transistor B1 and bipolar transistor B2
Number be respectively 1 and 3, i.e., both number ratio N=1:3.According to above-mentioned formula (4), it is assumed that the resistance value R=of resistance R11
1.4M, so that it may obtain the bias current of IB1=20nA.
If according to traditional scheme, the number ratio N=1:8 of bipolar transistor B1 and bipolar transistor B2, it is desirable to obtain IB1=
The bias current of 20nA then needs to be arranged the resistance value R=2.7M of resistance R11.The present invention can reduce compared with traditional scheme
The resistance value of resistance R11, so as to save the resistor area of half.
The second aspect of the embodiment is, as shown in figure 5, N-type MOSFET MN3 connects into diode structure, such as Fig. 6
Shown, p-type MOSFET MP6 connects into diode structure, to replace the resistance R21 in Fig. 2 and 3.
Mirror image pipe of the p-type MOSFET MP3 of base modules 210 as p-type MOSFET MP2, mirror image p-type MOSFET MP2
Electric current, flow to bipolar transistor B3 and N-type MOSFET MN3, generate bandgap voltage reference VBG1.By the way that p-type MOSFET is arranged
The proportionate relationship of the breadth length ratio of the breadth length ratio and p-type MOSFET MP2 of MP3, bandgap voltage reference VBG1 can obtain 1V to 1.8V
Between any voltage value.
The N-type MOSFET MN3 of present invention diode type of attachment, replaces the resistance of traditional structure, is greatly saved
Chip area.According to the resistance of traditional structure, if to obtain the voltage of 1.2V, the resistance value that the bias current of 20nA needs is about
For 30M, it is not able to satisfy actual demand.
Fig. 7 shows the schematic circuit of LDO circuit according to an embodiment of the present invention.The LDO circuit 200 includes benchmark mould
Block 210, amplification module 220, compensating module 230 and output module 240.Base modules 210 are for generating bias current IB1 and band
Gap reference voltage VBG1, amplification module 220 is for output voltage Vout to be compared with bandgap voltage reference VBG1, to obtain
The error signal of the two.Output module 240 controls the voltage drop of adjustment pipe according to error signal, to stabilize the output voltage
Vout.Compensating module 230 by work linear zone MOSFET be used as resistance, with capacitor C1 generate a zero point come play surely
Surely the effect compensated.
In LDO circuit 200, individual operational amplifier itself is not used in band-gap reference circuit 210, only output module
240 use an operational amplifier, thus, entire LDO circuit includes an operational amplifier, so as to simplify circuit knot
Structure.Further, output module 240 thereby may be ensured that the stabilization of output voltage Vout using N-type MOSFET as adjustment pipe
Property.
Amplification module 220 includes p-type MOSFET MP4, N-type MOSFET MN4 and operational amplifier U1.
P-type MOSFET MP4 and N-type MOSFET MN4 are connected in series between voltage supplied AVDD and ground AGND.P-type
The grid of MOSFET MP4 and MP3 are connected to each other, and the drain electrode of N-type MOSFET MN4 and grid are connected to each other.Operational amplifier U1
Non-inverting input terminal be connected with the drain electrode of p-type MOSFET MP3, inverting input terminal receive output voltage Vout.
Compensating module 230 includes p-type MOSFET MP5 and capacitor C1.
P-type MOSFET MP5 and capacitor C1 be connected in series in supply voltage AVDD and operational amplifier U1 output end it
Between.Further, the grid of p-type MOSFET MP5 is connected with the grid of p-type MOSFET MP3.
Compensating module 230, in the p-type MOSFET MP5 of linear zone, replaces the compensation resistance of traditional structure using work, into
One step reduces chip area.Compensating module 230 produces the zero point of a Left half-plane, compensates for loop.
Output module 240 includes N-type MOSFET MN6 and N-type MOSFET MN5.
N-type MOSFET MN6 and N-type MOSFET MN5 are connected in series between supply voltage AVDD and ground AGND.Further
Ground, the grid of N-type MOSFET MN6 are connected to the output end of operational amplifier U1, and the grid of N-type MOSFET MN5 is connected to N-type
The grid of MOSFET MN4, to form mirrored transistor.The intermediate node of N-type MOSFET MN6 and N-type MOSFET MN5 mention
For output voltage Vout.
Output module 240 replaces the divider resistance of traditional structure using N-type MOSFET MN5.According to the partial pressure of traditional structure
Resistance, if LDO circuit will export the voltage of 1.2V, the resistance value that 20nA exports the divider resistance that electric current needs is about 60M, no
It is able to satisfy actual demand.
The first aspect of the embodiment is, using N-type MOSFET MN6, replaces the p-type MOSFET conduct of traditional structure
Power tube output, and N-type MOSFET MN5 is used, replace the divider resistance in Fig. 1.
The second aspect of the embodiment is, using work in the p-type MOSFET MP5 of linear zone, replaces the benefit in Fig. 1
Repay resistance Ro.
During the work of LDO circuit 200, base modules 210 generate bandgap voltage reference VBG1.In amplification module 220
The non-inverting input terminal of operational amplifier U1 connect with base modules 210 to receive bandgap voltage reference VBG1, inverting input terminal
It is connected with the output end of output module 240 to receive output voltage Vout, the N-type MOSFET of output end and output module 240
The grid of MN6 is connected.
The N-type MOSFET MN5 current mirror of output module 240 directly generates bias current, for biasing N-type MOSFET
MN6.The output voltage Vout of LDO circuit 200 is directly connected to the inverting input terminal of operational amplifier U1.In the work of feedback control loop
Under, output voltage Vout is directly equal to the bandgap voltage reference VBG1 of the non-inverting input terminal of operational amplifier U1.Operation amplifier
Output voltage Vout and bandgap voltage reference VBG1 are compared by device U1, are output to output module after the difference of the two is amplified
240, the voltage drop of the N-type MOSFET MN6 in output module 240 is controlled, to stabilize the output voltage Vout.
There are two poles in the loop of LDO circuit 200, one be operational amplifier U1 output pole P1, one is
The output pole P2 of LDO circuit 200, is respectively calculated as follows:
Wherein, Rop is the equivalent resistance of operational amplifier U1 output end over the ground, and Cop is operational amplifier U1 output end pair
The equivalent capacity on ground, Rout are equivalent resistance of 200 output end of LDO circuit to ground, and Cout is 200 output end of LDO circuit to ground
Equivalent capacity.
Due to the effect in loop bandwidth there are two pole, it is inadequate to will lead to loop phase nargin, so that exporting can generate
Oscillation cannot stablize.The method of compensation is to manufacture a zero point with compensation circuit, compensation phase margin is gone, so that loop phase
Position nargin meets the requirement of stability.
In traditional architectures, zero point value calculates as follows:
Wherein, Z1 is compensation phase margin, and Cout and Resr are respectively equivalent capacity of 200 output end of LDO circuit to ground
With ESR internal resistance.
Output capacitance and resistance in compensation circuit is for manufacturing zero point.It compensates phase margin Z1 and offsets pole P1 to loop
The influence of stability, while using pole P2 as the dominant pole of loop, so that loop phase nargin meets the requirement of stability.So
And the compensation method of the prior art requires the bulky capacitor of external uF rank.Due to defeated as power tube using p-type MOSFET
Out, Rout is larger, and it is smaller to will lead to pole P2, suffers close with P1, is more not easy compensation and reaches steady-working state.
In the LDO circuit of the embodiment, compensating electric capacity is built in chip, therefore, the capacitance of compensating electric capacity is not
The bulky capacitor of uF rank can be used.N-type MOSFET MN6 is used in output module 240, the p-type MOSFET of traditional structure is replaced to make
For power tube.Since the source electrode of N-type MOSFET exports, so that output resistance Rout is greatly reduced, pole P2 pole is far from pole
P1, so that the embodiment can use pole P1 as dominant pole, pole P2 is as time dominant pole.
Further, the p-type MOSFET MP5 and capacitor C1 of compensating module 230 generate a zero point to compensate P2 pairs of pole
The influence of phase margin, so that system loop is stablized.
Fig. 8 shows the schematic circuit of operational amplifier used in LDO circuit shown in Fig. 7.
Level-one amplifier structure is used in the operational amplifier U1 that amplification module 220 uses, as shown in Figure 5.The operation amplifier
Device U1 includes p-type MOSFET MP11 and MP12, N-type MOSFET MN11 to MN13.P-type MOSFET MP11 and N-type MOSFET
MN11 is connected in series between supply voltage AVDD and node N1, and in the on state of the two, electric current is via p-type MOSFET
MP11 and N-type MOSFET MN11, flow to node N1 from feeder ear.P-type MOSFET MP12 and N-type MOSFET MN12 series connection connects
It connects between supply voltage AVDD and node N1, in the on state of the two, electric current is via p-type MOSFET MP12 and N-type
MOSFET MN12 flow to node N1 from feeder ear.N-type MOSFET MN13 is connected between node N1 and ground AGND.
The grid of p-type MOSFET MP11 and MP12 are connected to each other, and are connected to the drain electrode of p-type MOSFET MP11, that
This forms mirrored transistor.The breadth length ratio of p-type MOSFET MP11 and MP12 are set as equal, guarantee that the electric current flowed through is equal.
The grid of N-type MOSFET MN11 and MN12 constitute difference respectively as non-inverting input terminal and inverting input terminal, the two
It is right.Current mirror load of the p-type MOSFET MP11 and MP12 as the differential pair.
The grid of N-type MOSFET MN13 is connected with the grid of the N-type MOSFET MN4 in amplification module 220, to produce
Raw bias current.
The intermediate node of p-type MOSFET MP12 and N-type MOSFET MN12 provide error signal as output end.
Fig. 9 shows the working waveform figure of LDO circuit according to an embodiment of the present invention.The output voltage Vout of the LDO circuit
Stable 1.2V waveform is maintained, and operating current is less than 200nA.
Figure 10 shows the corresponding phase margin waveform diagram of output load capacitance of LDO circuit according to an embodiment of the present invention.
The LDO circuit is that can guarantee system stability well within 1nF in capacitive load.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.Protection model of the invention
The range that the claims in the present invention are defined should be subject to by enclosing.
Claims (13)
1. a kind of low pressure difference linear voltage regulator, the supply voltage for providing feeder ear is converted into the output voltage of output end,
Include:
Base modules, for generating bias current and bandgap voltage reference；
Amplification module is connected with the base modules, for output voltage to be compared with the bandgap voltage reference, with
Obtain the error signal of the two；
Compensating module connects between the feeder ear and the output end of the amplification module, for compensating the output voltage；With
And
Output module is connected with the amplification module, for controlling the voltage drop of adjustment pipe according to error signal, to stablize
Output voltage,
Wherein, the output module includes:
The first transistor and second transistor being connected in series between the feeder ear and ground terminal, the first transistor are
The Metal Oxide Semiconductor Field Effect Transistor of N-type, for optimizing zero pole point position,
The control terminal of the first transistor receives the error signal,
The second transistor obtains the bias current from the amplification module using mirror-image fashion, thus brilliant for described first
Body pipe provides the bias current,
The intermediate node of the first transistor and the second transistor provides the output voltage as the output end,
The compensating module includes: the 14 of the series connection between the feeder ear and the output end of the amplification module
Transistor and capacitor, wherein the control terminal of the 14th transistor is connected to the base modules to obtain the biased electrical
Stream, the 14th transistor work in linear zone to play compensating action, and root as compensation resistance and the capacitor
The compensation resistance is adjusted according to the bias current.
2. low pressure difference linear voltage regulator according to claim 1, wherein the base modules include:
Third transistor, the 4th transistor and at least one the 5th crystal being connected in series between the feeder ear and ground terminal
Pipe；And
Be connected in series in the 6th transistor between the feeder ear and ground terminal, the 7th transistor, resistance and at least one
Eight transistors,
Wherein, the third transistor and the 6th transistor constitute current mirror, and the 4th transistor and the 7th transistor are constituted
Current mirror, at least one described the 5th transistor are connected in parallel with each other, at least one described the 8th transistor is connected in parallel with each other,
Also, the control terminal of at least one described the 5th transistor and at least one the 8th transistor is connected to each other and is grounded,
The bias current flows through the 6th transistor.
3. low pressure difference linear voltage regulator according to claim 2, wherein at least one described the 5th transistor and it is described extremely
The quantity ratio of few 8th transistor is greater than 1:8 and is less than or equal to 1:1.
4. low pressure difference linear voltage regulator according to claim 3, wherein the base modules further include:
The 9th transistor, the tenth transistor and the 11st transistor being connected in series between the feeder ear and ground terminal,
Wherein, the 9th transistor and the 6th transistor constitute current mirror, so that the bias current is obtained,
Tenth transistor connects into diode structure, and the control terminal of the 11st transistor is grounded,
The intermediate node of 9th transistor and the tenth transistor provides the bandgap voltage reference.
5. low pressure difference linear voltage regulator according to claim 4, by the way that the 9th transistor and the 6th crystalline substance is arranged
The proportionate relationship of the breadth length ratio of body pipe, the bandgap voltage reference of numerical value needed for obtaining.
6. the numberical range of low pressure difference linear voltage regulator according to claim 5, the bandgap voltage reference arrives for 1V
1.8V。
7. low pressure difference linear voltage regulator according to claim 4, wherein the third transistor, the 6th transistor,
9th transistor is respectively the Metal Oxide Semiconductor Field Effect Transistor of p-type,
The second transistor, the 4th transistor, the 7th transistor are respectively the MOS field of N-type
Effect transistor,
Tenth transistor is the Metal Oxide Semiconductor Field Effect Transistor of N-type or p-type,
5th transistor, the 8th transistor and the 11st transistor are respectively positive-negative-positive bipolar transistor.
8. low pressure difference linear voltage regulator according to claim 1, wherein the amplification module includes:
Operational amplifier, the non-inverting input terminal and inverting input terminal of the operational amplifier receive the bandgap voltage reference respectively
With the output voltage, output end provides the error signal.
9. low pressure difference linear voltage regulator according to claim 8, wherein the amplification module further include:
The tenth two-transistor and the 13rd transistor being connected in series between the feeder ear and ground terminal,
Wherein, the tenth two-transistor obtains the bias current from the base modules using mirror-image fashion.
10. low pressure difference linear voltage regulator according to claim 9, wherein the second transistor and the 13rd crystalline substance
Body pipe forms current mirror.
11. low pressure difference linear voltage regulator according to claim 9, wherein the tenth two-transistor is the metal oxygen of p-type
Compound semiconductor field effect transistor, the 13rd transistor are the Metal Oxide Semiconductor Field Effect Transistor of N-type.
12. low pressure difference linear voltage regulator according to claim 11, wherein the 14th transistor is the metal of p-type
Oxide semiconductor field effect transistor.
13. a kind of integrated system-on-chip, comprising:
Processor；
Memory；
Peripheral circuit；And
Low pressure difference linear voltage regulator according to any one of claim 1 to 12, for for the processor and described depositing
Reservoir power supply.
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| CN109450234B (en) * | 2018-12-14 | 2024-10-11 | 杭州士兰微电子股份有限公司 | Ideal diode and its control circuit |
| CN111669136B (en) * | 2019-03-07 | 2023-04-18 | 雅特力科技(重庆)有限公司 | Multi-stage amplifier with stabilizing circuit |
| CN110320956B (en) * | 2019-08-02 | 2021-01-05 | 深圳贝特莱电子科技股份有限公司 | LDO (low dropout regulator) regulating circuit without off-chip capacitor in chip |
| CN111399580A (en) * | 2020-05-21 | 2020-07-10 | 深圳市泛海数据科技有限公司 | Linear voltage stabilizing circuit |
| CN111367345B (en) * | 2020-05-26 | 2021-04-20 | 江苏长晶科技有限公司 | Compensation method for improving full load stability of low dropout linear regulator and circuit thereof |
| CN114389450B (en) * | 2020-10-21 | 2024-06-28 | 圣邦微电子（北京）股份有限公司 | Bootstrap switch converter and driving circuit thereof |
| CN112783257B (en) * | 2021-01-04 | 2022-03-25 | 深圳市南方硅谷半导体股份有限公司 | Series compensation circuit in high-voltage linear voltage converter |
| CN114326892B (en) * | 2021-12-10 | 2023-05-02 | 湖南国科微电子股份有限公司 | Power supply circuit and electronic equipment |
| CN115454186B (en) * | 2022-09-15 | 2023-05-05 | 芯洲科技(北京)股份有限公司 | Linear voltage regulator for power supply system and power supply system |
| CN117075669A (en) * | 2023-09-20 | 2023-11-17 | 江苏帝奥微电子股份有限公司 | High PSRR reference current generation circuit and method without starting circuit |
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