CN114326892B - Power supply circuit and electronic equipment - Google Patents
Power supply circuit and electronic equipment Download PDFInfo
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- CN114326892B CN114326892B CN202111509293.2A CN202111509293A CN114326892B CN 114326892 B CN114326892 B CN 114326892B CN 202111509293 A CN202111509293 A CN 202111509293A CN 114326892 B CN114326892 B CN 114326892B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The application provides a power supply circuit and electronic equipment. The power supply circuit includes: the bias current generation unit comprises a first mirror module and a first resistor, and is used for generating bias current under the action of the first mirror module and the first resistor; the reference voltage generating unit comprises a second mirror image module and a second resistor, wherein the bias current is mirrored on the second resistor to form a reference current under the action of the second mirror image module, and the reference current flows through the second resistor to form a reference voltage; the voltage stabilizing unit comprises a third mirror image module and a voltage following module, and generates stable power supply voltage under the action of the voltage following module, namely the circuit can provide stable power supply voltage, and the whole circuit has no operational amplifier structure, so that the problem of high power consumption of the high-voltage-resistant power supply circuit in the prior art is solved.
Description
Technical Field
The present disclosure relates to the field of electronic circuits, and in particular, to a power supply circuit and an electronic device.
Background
In many power supply systems, the power supply voltage is higher than 12V, if all circuits work in a 12V voltage domain, each circuit needs to consider the problem of high voltage withstand, the corresponding layout area and cost are large, the conventional solution is to obtain a conventional voltage of 5V, and most other circuits are made in the voltage domain, so that only few circuits and pipes need to consider the problem of withstand voltage.
Fig. 1 is a diagram of a high voltage bandgap reference implemented at high voltage, as is conventional at present, and used to provide a reference voltage for a subsequent LDO (Low Dropout Regulator, low voltage linear regulator). In the scheme, the band gap reference and the LDO circuit are all required to use an operational amplifier and a high-voltage tube, and the number of functional module circuits is relatively large, and the implementation mode is relatively traditional, so that the scheme has high power consumption and high cost.
Disclosure of Invention
The main aim of the application is to provide a power supply circuit and electronic equipment, so as to solve the problem of high power consumption of the high-voltage-resistant power supply circuit in the prior art.
To achieve the above object, according to one aspect of the present application, there is provided a power supply circuit including: the bias current generation unit comprises a first mirror module and a first resistor, and generates bias current under the action of the first mirror module and the first resistor; the reference voltage generating unit is electrically connected with the bias current generating unit and comprises a second mirror image module and a second resistor, the bias current is mirrored on the second resistor under the action of the second mirror image module to form reference current, and the reference current flows through the second resistor to form reference voltage; the voltage stabilizing unit is electrically connected with the reference voltage generating unit and comprises a third mirror image module and a voltage following module, the bias current is mirrored into the voltage stabilizing unit under the action of the third mirror image module, the reference voltage is input into the voltage following module, and the stable power supply voltage is generated under the action of the voltage following module.
Optionally, the first mirror module includes a first P-type field effect transistor, a third P-type field effect transistor, a first N-type field effect transistor and a second N-type field effect transistor, where the first P-type field effect transistor is mirror symmetrical with the third P-type field effect transistor, the first N-type field effect transistor is mirror symmetrical with the second N-type field effect transistor, the first P-type field effect transistor is electrically connected with the second N-type field effect transistor, the third P-type field effect transistor is electrically connected with the first N-type field effect transistor, and the second N-type field effect transistor is electrically connected with the first resistor.
Optionally, the second mirror module includes a fifth P-type field effect transistor, and the fifth P-type field effect transistor is mirror symmetrical to the first P-type field effect transistor.
Optionally, the third mirror module includes a seventh P-type field effect transistor and a fourth N-type field effect transistor, where the seventh P-type field effect transistor and the fourth N-type field effect transistor are electrically connected to the voltage follower module, the seventh P-type field effect transistor is mirror symmetrical to the first P-type field effect transistor, and the fourth N-type field effect transistor is mirror symmetrical to the second N-type field effect transistor.
Optionally, the voltage follower module includes a third N-type field effect tube, a ninth P-type field effect tube and a tenth P-type field effect tube, where a gate of the third N-type field effect tube and a gate of the tenth P-type field effect tube are electrically connected with the high voltage end of the second resistor, a source of the third N-type field effect tube and a drain of the tenth P-type field effect tube are electrically connected with a drain of the fourth N-type field effect tube, a drain of the third N-type field effect tube is electrically connected with a gate of the ninth P-type field effect tube, a source of the tenth P-type field effect tube is electrically connected with a drain of the ninth P-type field effect tube, and a source of the ninth P-type field effect tube is electrically connected with a source of the seventh P-type field effect tube.
Optionally, the power supply circuit further includes a high voltage tolerant unit electrically connected to the bias current generating unit, the reference voltage generating unit, and the voltage stabilizing unit, respectively.
Optionally, the power supply circuit further includes a third resistor, and the third resistor provides a bias voltage for the high voltage resistant unit.
Optionally, the high voltage resistant unit includes a first high voltage resistant module, a second high voltage resistant module and a third high voltage resistant module, the first high voltage resistant module is electrically connected with the first mirror image module, the first high voltage resistant module includes a second P-type field effect transistor and a fourth P-type field effect transistor, the second P-type field effect transistor and the fourth P-type field effect transistor are in mirror symmetry, the high voltage resistant unit includes a second high voltage resistant module, the second high voltage resistant module is electrically connected with the second mirror image module, the second high voltage resistant module includes a sixth P-type field effect transistor, the sixth P-type field effect transistor is in mirror symmetry with the second P-type field effect transistor, the high voltage resistant unit includes a third high voltage resistant module, the third high voltage resistant module is respectively electrically connected with the third mirror image module and the voltage following module, the third high voltage resistant module includes an eighth P-type field effect transistor, the eighth P-type field effect transistor is in mirror symmetry with the second P-type field effect transistor.
Optionally, the second P-type field effect transistor, the fourth P-type field effect transistor, the sixth P-type field effect transistor and the eighth P-type field effect transistor are respectively high-voltage transistors.
According to another aspect of the present application, there is provided an electronic device including any one of the power supply circuits.
By applying the technical scheme of the application, a power supply circuit is provided, and the circuit comprises: the bias current generation unit comprises a first mirror module and a first resistor, and is used for generating bias current under the action of the first mirror module and the first resistor; the reference voltage generating unit is electrically connected with the bias current generating unit and comprises a second mirror image module and a second resistor, the bias current is mirrored on the second resistor under the action of the second mirror image module to form reference current, and the reference current flows through the second resistor to form reference voltage; the voltage stabilizing unit is electrically connected with the reference voltage generating unit and comprises a third mirror image module and a voltage following module, the bias current is mirrored in the voltage stabilizing unit under the action of the third mirror image module, the reference voltage is input into the voltage following module, and stable power supply voltage is generated under the action of the voltage following module, namely, the circuit can provide stable power supply voltage, and the whole circuit has no operational amplifier structure, so that the problem of high power consumption of the high-voltage-resistant power supply circuit in the prior art is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 shows a schematic diagram of a prior art power supply circuit;
fig. 2 shows a schematic diagram of a power supply circuit according to an embodiment of the present application.
Wherein the above figures include the following reference numerals:
10. a bias current generating unit; 11. a first mirror module; 20. a reference voltage generation unit; 21. a second mirror module; 30. a voltage stabilizing unit; 31. a third mirror module; 32. a voltage follower module; 40. and a high pressure resistant unit.
Detailed Description
It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, the high voltage resistant power supply circuit in the prior art has large power consumption, so as to solve the problem of large power consumption of the high voltage resistant power supply circuit, and the embodiment of the application provides a power supply circuit and electronic equipment.
In an exemplary embodiment of the present application, a power supply circuit is provided, as shown in fig. 2, including: a bias current generating unit 10, a reference voltage generating unit 20 and a voltage stabilizing unit 30, wherein the bias current generating unit 10 comprises a first mirror module 11 and a first resistor R1, and is used for generating a bias current I1 under the action of the first mirror module 11 and the first resistor R1; the reference voltage generating unit 20 is electrically connected to the bias current generating unit 10, the reference voltage generating unit 20 includes a second mirror module 21 and a second resistor R2, the bias current I1 is mirrored to the second resistor R2 by the second mirror module 21 to form a reference current I3, and the reference current I3 flows through the second resistor R2 to form a reference voltage; the voltage stabilizing unit 30 is electrically connected to the reference voltage generating unit 20, and the voltage stabilizing unit 30 includes a third mirroring module 31 and a voltage following module 32, mirrors the bias current I1 to the voltage stabilizing unit 30 by the third mirroring module 31, inputs the reference voltage to the voltage following module 32, and generates a stable power supply voltage by the voltage following module 32. The circuit can provide stable power supply voltage, no operational amplifier exists in the whole circuit, the power consumption is low, and the problem that the high-voltage-resistant power supply circuit in the prior art is large in power consumption is solved.
Specifically, as shown in fig. 2, the first mirror module 11 includes a first P-type field effect transistor P1, a third P-type field effect transistor P3, a first N-type field effect transistor N1 and a second N-type field effect transistor N2, the first P-type field effect transistor P1 is mirror symmetrical to the third P-type field effect transistor P3, the first N-type field effect transistor N1 and the second N-type field effect transistor N2 are mirror symmetrical, the first P-type field effect transistor P1 is electrically connected to the second N-type field effect transistor N2, the third P-type field effect transistor P3 is electrically connected to the first N-type field effect transistor N1, the second N-type field effect transistor N2 is electrically connected to the first resistor R1, the first P-type field effect transistor P1, the third P-type field effect transistor P3, the first N-type field effect transistor N1, the second N-type field effect transistor N2 and the first resistor R1 are mirror symmetrical to each other, the first P-type field effect transistor P1 and the second N-type field effect transistor N2 are used to generate a bias current, and the first P-type field effect transistor N1 and the first gate voltage v 1 and the second gate voltage v 1 (i.sn=sn 1 and sn 1) are formed between the first P1 and the first P-type field effect transistor N2 and the first P1 and the second P-type field effect transistor sn).
Specifically, as shown in fig. 2, the second mirror module 21 includes a fifth P-type field effect transistor P5, the fifth P-type field effect transistor P5 is mirror-symmetrical to the first P-type field effect transistor P1, and the bias current I1 generates a reference voltage at the second resistor R2 by the mirror action of the fifth P-type field effect transistor P5, and the voltage across the second resistor R2 is the reference voltage. The fifth P-type field effect transistor P5 forms a mirror image with the first P-type field effect transistor P1, so that the current i3=i1 flowing through the second resistor R2, the voltage applied to the second resistor R2 is VR3 (VR 3=i3×r2), and VR3 is the reference voltage.
Specifically, as shown in fig. 2, the third mirror module 31 includes a seventh P-type fet P7 and a fourth N-type fet N4. The seventh P-type field effect transistor P7 and the fourth N-type field effect transistor N4 are electrically connected with the voltage follower module 32, respectively, the seventh P-type field effect transistor P7 is mirror symmetrical to the first P-type field effect transistor P1 and is used for copying the current of the bias current I1, the fourth N-type field effect transistor N4 is mirror symmetrical to the second N-type field effect transistor N2 and provides the bias current I4, the bias current I4 is larger than the current flowing through the seventh P-type field effect transistor P7, the circuit function can be normal, and parameters such as the size, the model and the like of the fourth N-type field effect transistor N4 and the second N-type field effect transistor N2 are set according to different proportions, so that the value of the bias current I4 is 200nA.
Specifically, as shown in fig. 2, the voltage follower module 32 includes a third N-type fet N3, a ninth P-type fet P9, and a tenth P-type fet P10. The source electrode of the seventh P-type field effect transistor P7 and the source electrode of the ninth P-type field effect transistor P9 are electrically connected to the power source terminal, the gate electrode of the seventh P-type field effect transistor P7 is electrically connected to the gate electrode of the first P-type field effect transistor P1, the gate electrode of the third N-type field effect transistor N3 and the gate electrode of the tenth P-type field effect transistor P10 are electrically connected to the high voltage terminal of the second resistor R2, the source electrode of the third N-type field effect transistor N3 and the drain electrode of the tenth P-type field effect transistor P10 are electrically connected to the drain electrode of the fourth N-type field effect transistor N4, the source electrode of the fourth N-type field effect transistor N4 is grounded, the gate electrode of the fourth N-type field effect transistor N4 is electrically connected to the gate electrode of the first N-type field effect transistor N1, the drain electrode of the third N-type field effect transistor N3 is electrically connected to the gate electrode of the ninth P10, the drain electrode of the tenth P-type field effect transistor P10 is electrically connected to the gate electrode of the ninth P9, and the drain electrode of the ninth P9 is electrically connected to the gate electrode of the fourth N-type field effect transistor P4, and the drain electrode of the ninth P9 is electrically connected to the gate electrode of the fourth N1. The voltage of the power supply voltage VO output by the voltage following module is equal to the sum of VR3 and VGS (voltage between the grid and the source) of the tenth P-type field effect transistor P10, meanwhile, the voltage of the power supply voltage VO is stable and does not change along with the power supply voltage, and other module circuits can be safely powered.
In one embodiment of the present application, as shown in fig. 2, the power supply circuit further includes a high voltage tolerant unit 40, and the high voltage tolerant unit 40 is electrically connected to the bias current generating unit 10, the reference voltage generating unit 20, and the voltage stabilizing unit 30, respectively.
Specifically, as shown in fig. 2, the power supply circuit further includes a third resistor R3, where the third resistor R3 provides bias voltages for the high voltage tolerant unit 40, that is, bias voltages are provided for the gates of the second P-type field effect transistor P2, the fourth P-type field effect transistor P4, the sixth P-type field effect transistor P6, and the eighth P-type field effect transistor P8, and the third resistor R3 is used for providing bias currents for the second P-type field effect transistor P2.
Specifically, as shown in fig. 2, the high voltage tolerant unit 40 includes a first high voltage tolerant module electrically connected to the first mirror module 11, the first high voltage tolerant module includes a second P-type fet P2 and a fourth P-type fet P4, the second P-type fet P2 and the fourth P-type fet P4 are mirror symmetrical, a power supply terminal of the power supply circuit is connected to a voltage of 12V, the voltage of 12V is input to the first mirror module 11, the first P-type fet P1 and the third P-type fet P3 of the first mirror module 11 generate mirror currents, a withstand voltage of the first high voltage tolerant module is 12V, most of voltages in the voltages of 12V can be separated, the first N-type fet N1 and the second N-type fet N2 of the first mirror module 11 generate bias currents I1, and the withstand voltage of the first mirror module 11 is smaller.
Specifically, as shown in fig. 2, the second P-type field effect transistor P2 and the fourth P-type field effect transistor P4 are high voltage transistors.
The source electrode of the first P-type field effect transistor P1 and the source electrode of the third P-type field effect transistor P3 are electrically connected to a power source terminal, the gate electrode of the first P-type field effect transistor P1 and the gate electrode of the third P-type field effect transistor P3 are electrically connected, the drain electrode of the first P-type field effect transistor P1 is electrically connected to the source electrode of the second P-type field effect transistor P2, the drain electrode of the third P-type field effect transistor P3 is electrically connected to the source electrode of the fourth P-type field effect transistor P4, the gate electrode of the second P-type field effect transistor P2 and the gate electrode of the fourth P-type field effect transistor P4 are electrically connected, the drain electrode of the second P-type field effect transistor P2 is electrically connected to the drain electrode of the second N-type field effect transistor N2, the drain electrode of the fourth P4 is electrically connected to the drain electrode of the first N-type field effect transistor N1, the gate electrode of the second N-type field effect transistor N2 is electrically connected to the first N-type field effect transistor N1, and the first resistor N1 is connected to the first N-type field effect transistor N1.
The second P-type field effect transistor P2 and the fourth P-type field effect transistor P4 divide most of the 12V voltage, so that the voltages applied to the first P-type field effect transistor P1, the third P-type field effect transistor P3, the first N-type field effect transistor N1 and the second N-type field effect transistor N2 are low voltages, and the first P-type field effect transistor P1, the third P-type field effect transistor P3, the first N-type field effect transistor N1 and the second N-type field effect transistor N2 are prevented from being broken down by high voltages. Namely, the circuit has the performances of high voltage resistance, low power consumption and low cost.
Specifically, as shown in fig. 2, the high voltage tolerant unit 40 includes a second high voltage tolerant module electrically connected to the second mirror module 21, the second high voltage tolerant module includes a sixth P-type field effect transistor P6, the sixth P-type field effect transistor P6 is mirror-symmetrical to the second P-type field effect P2, and the sixth P-type field effect transistor P6 is a high voltage transistor.
The source electrode of the fifth P-type field effect transistor P5 is electrically connected to the power supply terminal, the gate electrode of the fifth P-type field effect transistor P5 is electrically connected to the gate electrode of the first P-type field effect transistor P1, the drain electrode of the fifth P-type field effect transistor P5 is electrically connected to the source electrode of the sixth P-type field effect transistor P6, the gate electrode of the sixth P-type field effect transistor P6 is electrically connected to the gate electrode of the second P-type field effect transistor P6, the drain electrode of the sixth P-type field effect transistor P6 is electrically connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is grounded.
The sixth P-type field effect transistor P6 splits most of the 12V voltage so that the voltage applied to the fifth P-type field effect transistor P5 is reduced, preventing the fifth P-type field effect transistor P5 from being broken down.
Specifically, as shown in fig. 2, the high voltage tolerant unit 40 includes a third high voltage tolerant module electrically connected to the third mirror module 31 and the voltage follower module 32, where the third high voltage tolerant module includes an eighth P-type fet P8, the eighth P-type fet P8 is mirror symmetrical to the second P-type fet P2 for high voltage tolerance, and the eighth P-type fet P8 and the ninth P-type fet P9 are high voltage tubes, respectively.
The drain electrode of the seventh P-type field effect transistor P7 is electrically connected with the source electrode of the eighth P-type field effect transistor P8, the grid electrode of the eighth P-type field effect transistor P8 is electrically connected with the grid electrode of the second P-type field effect transistor P2, the drain electrode of the eighth P-type field effect transistor P8 is respectively electrically connected with the grid electrode of the ninth P-type field effect transistor P9 and the drain electrode of the third N-type field effect transistor N3,
the eighth P-type field effect transistor P8 and the ninth P-type field effect transistor P9 divide most of the 12V voltage, so that the voltages applied to the seventh P-type field effect transistor P7, the third N-type field effect transistor N3 and the fourth N-type field effect transistor N4 are low voltages, and the seventh P-type field effect transistor P7, the third N-type field effect transistor N3 and the fourth N-type field effect transistor N4 are prevented from being broken down.
In one embodiment, as shown in fig. 2, the bias current I1 can be made as low as 100Na by setting reasonable circuit parameters. This bias current replicates the current through the current mirror onto resistor R2 to produce voltage VR3. The voltage VR3 is a reference voltage independent of the power supply voltage. The voltage VR3 is a voltage follower circuit formed by a seventh P-type field effect transistor P7, an eighth P-type field effect transistor P8, a ninth P-type field effect transistor P9, a tenth P-type field effect transistor P10 and a third N-type field effect transistor N3, and the voltage VR3 added with VGSp10 is the output voltage of the supply voltage VO. Meanwhile, the voltage of the power supply voltage VO is stable and does not change along with the power supply voltage, and other module circuits can be safely supplied with power. The whole circuit is realized by a current mirror, and an operational amplifier is not used, so that the total no-load power consumption is 500nA, and the circuit has extremely low power consumption. Meanwhile, only the second P-type field effect tube P2, the fourth P-type field effect tube P4, the sixth P-type field effect tube P6, the eighth P-type field effect tube P8 and the ninth P-type field effect tube P9 are high-voltage tubes, the Vds withstand voltage of the high-voltage tubes is 12V, VGS, VGD, VDS of other low-voltage tubes can be protected from high voltage, the purpose of high-voltage resistance is achieved, the number of the high-voltage tubes in the implementation mode is far less than that of the traditional architecture of FIG. 1, and the structure is simple.
In another exemplary embodiment of the present application, an electronic device is provided that includes any of the above-described power supply circuits. The current bias unit in the power supply circuit in the electronic equipment outputs bias current, the reference voltage generation unit generates reference voltage based on the bias current, and the voltage following module plays a role of following the reference voltage so as to generate stable power supply voltage which can supply power for the circuit module. And the current bias unit, the reference voltage generation unit and the voltage following module in the application are all provided with no operational amplifier, so that the power consumption is low.
From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
1) According to the power supply circuit, the current bias unit outputs bias current, the reference voltage generation unit generates reference voltage based on the bias current, the voltage following module plays a role of following the reference voltage so as to generate stable power supply voltage, and the stable power supply voltage can supply power for the circuit module. The current bias unit, the reference voltage generation unit and the voltage following module in the application are all provided with no operational amplifier, namely, the operational amplifier is not needed to realize LDO (linear voltage regulator) and a reference circuit, the power consumption is low, and the scheme is simple and the cost is low.
2) According to the electronic equipment, the current bias unit in the power supply circuit in the electronic equipment outputs bias current, the reference voltage generation unit generates reference voltage based on the bias current, the voltage following module plays a role of following the reference voltage so as to generate stable power supply voltage, and the stable power supply voltage can supply power for the circuit module. And the current bias unit, the reference voltage generation unit and the voltage following module in the application are all provided with no operational amplifier, so that the power consumption is low.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (8)
1. A power supply circuit, comprising:
the bias current generation unit comprises a first mirror image module and a first resistor, and generates bias current under the action of the first mirror image module and the first resistor;
the reference voltage generation unit is electrically connected with the bias current generation unit and comprises a second mirror image module and a second resistor, the bias current is mirrored on the second resistor under the action of the second mirror image module to form reference current, and the reference current flows through the second resistor to form reference voltage;
the voltage stabilizing unit is electrically connected with the reference voltage generating unit and comprises a third mirror image module and a voltage following module, the bias current is mirrored into the voltage stabilizing unit under the action of the third mirror image module, the reference voltage is input into the voltage following module, and a stable power supply voltage is generated under the action of the voltage following module;
the high voltage resistant unit comprises a first high voltage resistant module, a second high voltage resistant module and a third high voltage resistant module, wherein the first high voltage resistant module is electrically connected with the first mirror image module, the first high voltage resistant module comprises a second P-type field effect transistor and a fourth P-type field effect transistor, the second P-type field effect transistor and the fourth P-type field effect transistor are in mirror symmetry, the second high voltage resistant module is electrically connected with the second mirror image module, the second high voltage resistant module comprises a sixth P-type field effect transistor, the sixth P-type field effect transistor is in mirror symmetry with the second P-type field effect transistor, the third high voltage resistant module is respectively electrically connected with the third mirror image module and the voltage following module, the third high voltage resistant module comprises an eighth P-type field effect transistor, and the eighth P-type field effect transistor is in mirror symmetry with the second P-type field effect transistor.
2. The power supply circuit of claim 1, wherein the first mirror module comprises a first P-type field effect transistor, a third P-type field effect transistor, a first N-type field effect transistor, and a second N-type field effect transistor, wherein the first P-type field effect transistor is mirror symmetrical to the third P-type field effect transistor, the first N-type field effect transistor is mirror symmetrical to the second N-type field effect transistor, the first P-type field effect transistor is electrically connected to the second N-type field effect transistor, the third P-type field effect transistor is electrically connected to the first N-type field effect transistor, and the second N-type field effect transistor is electrically connected to the first resistor.
3. The power supply circuit of claim 2, wherein the second mirroring module comprises a fifth P-type field effect transistor that is mirror symmetric with the first P-type field effect transistor.
4. The power supply circuit of claim 2, wherein the third mirror module comprises a seventh P-type field effect transistor and a fourth N-type field effect transistor, the seventh P-type field effect transistor and the fourth N-type field effect transistor are respectively electrically connected with the voltage follower module, the seventh P-type field effect transistor is in mirror symmetry with the first P-type field effect transistor, and the fourth N-type field effect transistor is in mirror symmetry with the second N-type field effect transistor.
5. The power supply circuit of claim 4, wherein the voltage follower module comprises a third N-type field effect transistor, a ninth P-type field effect transistor, and a tenth P-type field effect transistor, wherein a gate of the third N-type field effect transistor and a gate of the tenth P-type field effect transistor are electrically connected to the high voltage end of the second resistor, a source of the third N-type field effect transistor and a drain of the tenth P-type field effect transistor are electrically connected to a drain of the fourth N-type field effect transistor, a drain of the third N-type field effect transistor is electrically connected to a gate of the ninth P-type field effect transistor, a source of the tenth P-type field effect transistor is electrically connected to a drain of the ninth P-type field effect transistor, and a source of the ninth P-type field effect transistor is electrically connected to a source of the seventh P-type field effect transistor.
6. The power supply circuit of claim 1, further comprising a third resistor, the third resistor providing a bias voltage for the high voltage tolerant unit.
7. The power supply circuit of claim 1, wherein the second P-type field effect transistor, the fourth P-type field effect transistor, the sixth P-type field effect transistor, and the eighth P-type field effect transistor are each high voltage transistors.
8. An electronic device comprising the power supply circuit of any one of claims 1 to 7.
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| CN202111509293.2A CN114326892B (en) | 2021-12-10 | 2021-12-10 | Power supply circuit and electronic equipment |
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| CN202111509293.2A CN114326892B (en) | 2021-12-10 | 2021-12-10 | Power supply circuit and electronic equipment |
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| JP3808867B2 (en) * | 2003-12-10 | 2006-08-16 | 株式会社東芝 | Reference power circuit |
| JP2008225952A (en) * | 2007-03-14 | 2008-09-25 | Ricoh Co Ltd | Voltage regulator |
| CN106774581B (en) * | 2017-01-25 | 2019-09-13 | 杭州士兰微电子股份有限公司 | Low pressure difference linear voltage regulator and integrated system-on-chip |
| CN110568902B (en) * | 2019-10-18 | 2021-06-01 | 广东工业大学 | Reference voltage source circuit |
| CN214042146U (en) * | 2021-01-20 | 2021-08-24 | 珠海格力电器股份有限公司 | Band-gap reference voltage generator |
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2021
- 2021-12-10 CN CN202111509293.2A patent/CN114326892B/en active Active
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