CN114326892A - Power supply circuit and electronic equipment - Google Patents
Power supply circuit and electronic equipment Download PDFInfo
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- CN114326892A CN114326892A CN202111509293.2A CN202111509293A CN114326892A CN 114326892 A CN114326892 A CN 114326892A CN 202111509293 A CN202111509293 A CN 202111509293A CN 114326892 A CN114326892 A CN 114326892A
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Abstract
The application provides a power supply circuit and an electronic device. The power supply circuit includes: the bias current generating unit comprises a first mirror image module and a first resistor and is used for generating bias current under the action of the first mirror image module and the first resistor; the reference voltage generating unit comprises a second mirror image module and a second resistor, the bias current is mirrored onto the second resistor under the action of the second mirror image module to form reference current, and the reference current flows through the second resistor to form reference voltage; the voltage stabilizing unit comprises a third mirror image module and a voltage following module, stable power supply voltage is generated under the action of the voltage following module, namely the circuit can provide stable power supply voltage, and the whole circuit is free of an operational amplifier structure, so that the problem that the power consumption of a high-voltage-resistant power supply circuit in the prior art is large is solved.
Description
Technical Field
The application relates to the field of electronic circuits, in particular to a power supply circuit and electronic equipment.
Background
In many power supply systems, the power supply voltage is higher than 12V, if all circuits work in a 12V voltage domain, each circuit needs to consider the problem of high voltage withstand voltage, the corresponding layout area and the cost are large, the traditional solution is to obtain 5V conventional voltage, most other circuits are in the voltage domain, and only a few circuits and pipes need to consider the problem of withstand voltage.
Fig. 1 shows a conventional method for implementing a high-voltage bandgap reference at a high voltage, and using the reference to provide a reference voltage for a subsequent LDO (Low drop out Regulator). In the scheme, the band gap reference and the LDO circuit need to use an operational amplifier and a high-voltage tube, and more functional module circuits and more traditional implementation modes are adopted, so that the scheme has high power consumption and high cost.
Disclosure of Invention
The main objective of the present application is to provide a power supply circuit and an electronic device, so as to solve the problem that the power consumption of a high voltage tolerant power supply circuit in the prior art is large.
In order to achieve the above object, according to one aspect of the present application, there is provided a power supply circuit including: the bias current generating unit comprises a first mirror image module and a first resistor, and generates a bias current under the action of the first mirror image module and the first resistor; the reference voltage generation unit is electrically connected with the bias current generation unit and comprises a second mirror image module and a second resistor, the bias current is mirrored onto the second resistor under the action of the second mirror image module to form reference current, and the reference current flows through the second resistor to form reference voltage; the voltage stabilizing unit is electrically connected with the reference voltage generating unit and comprises a third mirror image module and a voltage following module, the bias current is mirrored into the voltage stabilizing unit under the action of the third mirror image module, the reference voltage input into the voltage following module is input, and stable power supply voltage is generated under the action of the voltage following module.
Optionally, the first mirror module includes a first P-type field effect transistor, a third P-type field effect transistor, a first N-type field effect transistor and a second N-type field effect transistor, the first P-type field effect transistor is mirror symmetric with the third P-type field effect transistor, the first N-type field effect transistor is mirror symmetric with the second N-type field effect transistor, the first P-type field effect transistor is electrically connected with the second N-type field effect transistor, the third P-type field effect transistor is electrically connected with the first N-type field effect transistor, and the second N-type field effect transistor is electrically connected with the first resistor.
Optionally, the second mirror module includes a fifth P-type field effect transistor, and the fifth P-type field effect transistor is mirror-symmetrical to the first P-type field effect transistor.
Optionally, the third mirror module includes a seventh P-type field effect transistor and a fourth N-type field effect transistor, the seventh P-type field effect transistor and the fourth N-type field effect transistor are electrically connected to the voltage follower module respectively, the seventh P-type field effect transistor is mirror-symmetric to the first P-type field effect transistor, and the fourth N-type field effect transistor is mirror-symmetric to the second N-type field effect transistor.
Optionally, the voltage following module includes a third N-type field effect transistor, a ninth P-type field effect transistor and a tenth P-type field effect transistor, a gate of the third N-type field effect transistor and a gate of the tenth P-type field effect transistor are respectively electrically connected to the high-voltage end of the second resistor, a source of the third N-type field effect transistor and a drain of the tenth P-type field effect transistor are respectively electrically connected to a drain of the fourth N-type field effect transistor, a drain of the third N-type field effect transistor is electrically connected to a gate of the ninth P-type field effect transistor, a source of the tenth P-type field effect transistor is electrically connected to a drain of the ninth P-type field effect transistor, and a source of the ninth P-type field effect transistor is electrically connected to a source of the seventh P-type field effect transistor.
Optionally, the power supply circuit further includes a high voltage resistant unit, and the high voltage resistant unit is electrically connected to the bias current generating unit, the reference voltage generating unit, and the voltage stabilizing unit, respectively.
Optionally, the power supply circuit further includes a third resistor, and the third resistor provides a bias voltage for the high voltage resistant unit.
Optionally, the high voltage resistant unit includes a first high voltage resistant module, a second high voltage resistant module and a third high voltage resistant module, the first high voltage resistant module is electrically connected to the first mirror module, the first high voltage resistant module includes a second P-type field effect transistor and a fourth P-type field effect transistor, the second P-type field effect transistor and the fourth P-type field effect transistor are in mirror symmetry, the high voltage resistant unit includes a second high voltage resistant module, the second high voltage resistant module is electrically connected to the second mirror module, the second high voltage resistant module includes a sixth P-type field effect transistor, the sixth P-type field effect transistor is in mirror symmetry to the second P-type field effect transistor, the high voltage resistant unit includes a third high voltage resistant module, the third high voltage resistant module is electrically connected to the third mirror module and the voltage follower module, respectively, the third high voltage resistant module includes an eighth P-type field effect transistor, the eighth P-type field effect transistor is in mirror symmetry with the second P-type field effect transistor.
Optionally, the second P-type field effect transistor, the fourth P-type field effect transistor, the sixth P-type field effect transistor, and the eighth P-type field effect transistor are high-voltage transistors, respectively.
According to another aspect of the present application, there is provided an electronic device including any one of the power supply circuits.
By applying the technical scheme of the application, a power supply circuit is provided, and the circuit comprises: the bias current generating unit comprises a first mirror image module and a first resistor, and is used for generating a bias current under the action of the first mirror image module and the first resistor; the reference voltage generation unit is electrically connected with the bias current generation unit and comprises a second mirror image module and a second resistor, the bias current is mirrored onto the second resistor under the action of the second mirror image module to form a reference current, and the reference current flows through the second resistor to form a reference voltage; the voltage stabilizing unit is electrically connected with the reference voltage generating unit and comprises a third mirror image module and a voltage following module, the bias current is mirrored into the voltage stabilizing unit under the action of the third mirror image module and is input into the reference voltage in the voltage following module, and stable power supply voltage is generated under the action of the voltage following module, namely the circuit can provide stable power supply voltage, and the whole circuit is free of an operational amplifier structure, so that the problem of large power consumption of a high-voltage-resistant power supply circuit in the prior art is solved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 shows a schematic diagram of a prior art power supply circuit;
fig. 2 shows a schematic diagram of a supply circuit according to an embodiment of the application.
Wherein the figures include the following reference numerals:
10. a bias current generating unit; 11. a first mirror module; 20. a reference voltage generating unit; 21. a second mirror module; 30. a voltage stabilization unit; 31. a third mirror module; 32. a voltage following module; 40. a high pressure resistant unit.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As introduced in the background art, a high voltage tolerant power supply circuit in the prior art has large power consumption, and in order to solve the problem of large power consumption of the high voltage tolerant power supply circuit, embodiments of the present application provide a power supply circuit and an electronic device.
In an exemplary embodiment of the present application, there is provided a power supply circuit, as shown in fig. 2, including: a bias current generating unit 10, a reference voltage generating unit 20 and a voltage stabilizing unit 30, wherein the bias current generating unit 10 comprises a first mirror module 11 and a first resistor R1 for generating a bias current I1 under the action of the first mirror module 11 and the first resistor R1; the reference voltage generating unit 20 is electrically connected to the bias current generating unit 10, the reference voltage generating unit 20 includes a second mirror module 21 and a second resistor R2, the bias current I1 is mirrored to the second resistor R2 by the second mirror module 21 to form a reference current I3, and the reference current I3 flows through the second resistor R2 to form a reference voltage; the voltage stabilizing unit 30 is electrically connected to the reference voltage generating unit 20, the voltage stabilizing unit 30 includes a third mirror module 31 and a voltage follower module 32, the bias current I1 is mirrored to the voltage stabilizing unit 30 by the third mirror module 31, and the reference voltage input to the voltage follower module 32 generates a stable supply voltage by the voltage follower module 32. Can provide stable supply voltage through this circuit, and all do not have operational amplifier in the whole circuit, the low power dissipation has solved the problem that high voltage resistant supply circuit consumption is big among the prior art.
Specifically, as shown in fig. 2, the first mirror module 11 includes a first pfet P1, a third pfet P3, a first nfet N1 and a second nfet N2, the first pfet P1 is mirror-symmetric with the third pfet P3, the first nfet N1 is mirror-symmetric with the second nfet N2, the first pfet P1 is electrically connected with the second nfet N2, the third pfet P3 is electrically connected with the first nfet N1, the second nfet N2 is electrically connected with the first resistor R1, the first pfet P1, the third pfet P3, the first nfet N1, the second fet N2 and the first resistor R1 are used for generating a first bias current, the first pfet P3 and the third pfet P57324, VGSN2 (voltage between the gate and the source) on the second N-type fet N2, VGSN1 (voltage between the gate and the source) on the first N-type fet N1, and the first resistor R1, (VGSN2-VGSN1)/R1 ═ I1, I1 is the bias current.
Specifically, as shown in fig. 2, the second mirror module 21 includes a fifth pfet P5, the fifth pfet P5 is mirror-symmetrical to the first pfet P1, the bias current I1 generates a reference voltage in a second resistor R2 by a mirror effect of the fifth pfet P5, and a voltage across the second resistor R2 is the reference voltage. The fifth pfet P5 mirrors the first pfet P1, such that the current I3 flowing through the second resistor R2 is I1, the voltage applied to the second resistor R2 is VR3(VR3 is I3 × R2), and VR3 is the reference voltage.
Specifically, as shown in fig. 2, the third mirror module 31 includes a seventh P-fet P7 and a fourth N-fet N4. The seventh pfet P7 and the fourth pfet N4 are electrically connected to the voltage follower module 32, respectively, the seventh pfet P7 is mirror-symmetric to the first pfet P1 and is configured to copy the current of the bias current I1, the fourth pfet N4 is mirror-symmetric to the second pfet N2 and provides the bias current I4, the circuit function is normal only when the bias current I4 is larger than the current flowing through the seventh pfet P7, and the fourth pfet N4 and the second pfet N2 are configured according to different ratios such as size and model, so that the value of the bias current I4 is 200 nA.
Specifically, as shown in fig. 2, the voltage follower module 32 includes a third N-fet N3, a ninth P-fet P9 and a tenth P-fet P10. A source of the seventh pfet P7 and a source of the ninth pfet P9 are electrically connected to the power source terminal, a gate of the seventh pfet P7 is electrically connected to a gate of the first pfet P1, a gate of the third nfet N3 and a gate of the tenth pfet P10 are electrically connected to a high voltage terminal of the second resistor R2, a source of the third nfet N3 and a drain of the tenth pfet P10 are electrically connected to a drain of the fourth nfet N4, a source of the fourth nfet N4 is grounded, a gate of the fourth nfet N4 is electrically connected to a gate of the first nfet N1, a drain of the third nfet N3 is electrically connected to a drain of the ninth pfet P9, and a source of the tenth pfet P10 is electrically connected to a source of the ninth pfet P9, a source of the ninth pfet P9 is electrically connected to a source of the seventh pfet P7, the third nfet N3, the ninth pfet P9 and the tenth pfet P10 form a voltage regulator circuit to output VO, a gate of the first nfet N1 is shorted to a drain of the first nfet N1, and a gate of the third nfet N3 and a gate of the tenth pfet P10 are respectively connected to the reference voltage. The power supply voltage VO output by the voltage following module is equal to the sum of VR3 and VGS (voltage between a grid electrode and a source electrode) of a tenth P-type field effect transistor P10, and meanwhile, the voltage of the power supply voltage VO is stable and does not change along with the power supply voltage, so that power can be safely supplied to other module circuits.
In an embodiment of the present invention, as shown in fig. 2, the power supply circuit further includes a high voltage withstanding unit 40, and the high voltage withstanding unit 40 is electrically connected to the bias current generating unit 10, the reference voltage generating unit 20, and the voltage stabilizing unit 30, respectively.
Specifically, as shown in fig. 2, the power supply circuit further includes a third resistor R3, the third resistor R3 provides a bias voltage to the high voltage tolerant unit 40, that is, provides a bias voltage to the gates of the second P-type fet P2, the fourth P-type fet P4, the sixth P-type fet P6 and the eighth P-type fet P8, respectively, and the third resistor R3 is configured to provide a bias current to the second P-type fet P2.
Specifically, as shown in fig. 2, the high voltage unit 40 includes a first high voltage module electrically connected to the first mirror module 11, the first high voltage tolerant module comprises a second P-type field effect transistor P2 and a fourth P-type field effect transistor P4, the second P-fet P2 and the fourth P-fet P4 are mirror images, the power supply terminal of the power supply circuit is connected with 12V voltage for high voltage resistance, the 12V voltage is input to the first mirror module 11, the first P-type field effect transistor P1 and the third P-type field effect transistor P3 of the first mirror module 11 generate mirror current, the voltage resistance of the first high voltage resistance module is 12V, most of the 12V voltage can be divided, the bias current I1 is generated by the first N-type fet N1 and the second N-type fet N2 of the first mirror module 11, and the withstand voltage of the first mirror module 11 is small.
Specifically, as shown in fig. 2, the second P-type fet P2 and the fourth P-type fet P4 are high-voltage tubes.
A source of the first PFET P1 and a source of the third PFET P3 are electrically connected to a power source, a gate of the first PFET P1 and a gate of the third PFET P3 are electrically connected, a drain of the first PFET P1 is electrically connected to a source of the second PFET P2, a drain of the third PFET P3 is electrically connected to a source of the fourth PFET P4, a gate of the second PFET P2 and a gate of the fourth PFET P4 are electrically connected, a drain of the second PFET P2 is electrically connected to a drain of the second NFET N2, a drain of the fourth PFET P4 is electrically connected to a drain of the first NFET N1, a gate of the second NFET N2 is electrically connected to a gate of the first NFET N1, the source of the second N-type fet N2 is electrically connected to the first terminal of the first resistor R1, the second terminal of the first resistor R1 is grounded, and the source of the first N-type fet N1 is grounded.
The second P-fet P2 and the fourth P-fet P4 are separated by most of the 12V voltage, so that the voltages applied to the first P-fet P1, the third P-fet P3, the first N-fet N1 and the second N-fet N2 are low, thereby preventing the first P-fet P1, the third P-fet P3, the first N-fet N1 and the second N-fet N2 from being broken down by high voltage. The circuit has the performances of high voltage resistance, low power consumption and low cost.
Specifically, as shown in fig. 2, the high voltage tolerant unit 40 includes a second high voltage tolerant module electrically connected to the second mirror module 21, the second high voltage tolerant module includes a sixth pfet P6, the sixth pfet P6 is mirror-symmetrical to the second pfet P2, and the sixth pfet P6 is a high voltage tube.
The source of the fifth pfet P5 is electrically connected to the power source terminal, the gate of the fifth pfet P5 is electrically connected to the gate of the first pfet P1, the drain of the fifth pfet P5 is electrically connected to the source of the sixth pfet P6, the gate of the sixth pfet P6 is electrically connected to the gate of the second pfet P6, the drain of the sixth pfet P6 is electrically connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is grounded.
The sixth pfet P6 taps most of the 12V voltage to reduce the voltage applied to the fifth pfet P5, thereby preventing the fifth pfet P5 from breaking down.
Specifically, as shown in fig. 2, the high voltage tolerant unit 40 includes a third high voltage tolerant module electrically connected to the third mirror module 31 and the voltage follower module 32, respectively, the third high voltage tolerant module includes an eighth pfet P8, the eighth pfet P8 is mirror-symmetrical to the second pfet P2 for high voltage tolerance, and the eighth pfet P8 and the ninth pfet P9 are high voltage tubes, respectively.
A drain of the seventh pfet P7 is electrically connected to a source of the eighth pfet P8, a gate of the eighth pfet P8 is electrically connected to a gate of the second pfet P2, a drain of the eighth pfet P8 is electrically connected to a gate of the ninth pfet P9 and a drain of the third nfet N3,
the eighth pfet P8 and the ninth pfet P9 divide most of the 12V voltage to make the voltage applied to the seventh pfet P7, the third nfet N3 and the fourth nfet N4 low, thereby preventing the seventh pfet P7, the third nfet N3 and the fourth nfet N4 from being broken down.
In one embodiment, as shown in fig. 2, the bias current I1 can be made as low as 100Na by setting reasonable circuit parameters. The bias current replicates the current through a current mirror onto resistor R2 producing voltage VR 3. Voltage VR3 is a reference voltage independent of the supply voltage. The voltage VR3 is a voltage follower circuit formed by the seventh P-type fet P7, the eighth P-type fet P8, the ninth P-type fet P9, the tenth P-type fet P10 and the third N-type fet N3, and the voltage VR3 is the output voltage of the supply voltage VO by adding the voltage VGSp 10. Meanwhile, the voltage of the power supply voltage VO is relatively stable and does not change along with the power supply voltage, and the power supply voltage VO can safely supply power to other module circuits. The whole circuit is realized by a current mirror, an operational amplifier is not used, and the total no-load power consumption is 500nA, so that the circuit has extremely low power consumption. Meanwhile, only the second P-type field effect transistor P2, the fourth P-type field effect transistor P4, the sixth P-type field effect transistor P6, the eighth P-type field effect transistor P8 and the ninth P-type field effect transistor P9 are high-voltage transistors, the Vds withstand voltage of the high-voltage transistors is 12V, the VGS, VGD and VDS of other low-voltage transistors can be protected from high voltage, the purpose of high voltage resistance is achieved, the number of the high-voltage transistors in the implementation mode is far less than that of the traditional framework in the figure 1, and the structure is simple.
In another exemplary embodiment of the present application, there is provided an electronic device including any one of the above-described power supply circuits. A current bias unit in a power supply circuit in the electronic equipment outputs bias current, a reference voltage generating unit generates reference voltage based on the bias current, a voltage following module plays a role of following the reference voltage to generate stable power supply voltage, and the stable power supply voltage can supply power for a circuit module. And the current bias unit, the reference voltage generation unit and the voltage following module in the application are all provided with no operational amplifier, so that the power consumption is low.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) the power supply circuit comprises a current bias unit, a reference voltage generation unit, a voltage following module and a circuit module, wherein the current bias unit outputs bias current, the reference voltage generation unit generates reference voltage based on the bias current, and the voltage following module plays a role in following the reference voltage so as to generate stable power supply voltage which can supply power for the circuit module. And the current bias unit, the reference voltage generation unit and the voltage following module in the scheme all have no operational amplifier, namely the LDO (linear regulator) and the reference circuit are realized without the operational amplifier, the power consumption is low, and the scheme is simple and has low cost.
2) The electronic equipment comprises a current bias unit, a reference voltage generation unit, a voltage following module and a circuit module, wherein the current bias unit in the power supply circuit of the electronic equipment outputs bias current, the reference voltage generation unit generates reference voltage based on the bias current, the voltage following module plays a role in following the reference voltage so as to generate stable power supply voltage, and the stable power supply voltage can supply power for the circuit module. And the current bias unit, the reference voltage generation unit and the voltage following module in the application are all provided with no operational amplifier, so that the power consumption is low.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A power supply circuit, comprising:
the bias current generation unit comprises a first mirror image module and a first resistor, and generates a bias current under the action of the first mirror image module and the first resistor;
the reference voltage generating unit is electrically connected with the bias current generating unit, comprises a second mirror image module and a second resistor, and mirrors the bias current onto the second resistor under the action of the second mirror image module to form reference current which flows through the second resistor to form reference voltage;
and the voltage stabilizing unit is electrically connected with the reference voltage generating unit and comprises a third mirror image module and a voltage following module, the bias current is mirrored into the voltage stabilizing unit under the action of the third mirror image module, the reference voltage input into the voltage following module is input, and the stable power supply voltage is generated under the action of the voltage following module.
2. The power supply circuit according to claim 1, wherein the first mirror module comprises a first P-type fet, a third P-type fet, a first N-type fet, and a second N-type fet, the first P-type fet and the third P-type fet are mirror symmetric, the first N-type fet and the second N-type fet are mirror symmetric, the first P-type fet is electrically connected to the second N-type fet, the third P-type fet is electrically connected to the first N-type fet, and the second N-type fet is electrically connected to the first resistor.
3. The power supply circuit of claim 2, wherein the second mirror module comprises a fifth PFET, and the fifth PFET is mirror symmetric with the first PFET.
4. The power supply circuit according to claim 2, wherein the third mirror module comprises a seventh P-type fet and a fourth N-type fet, the seventh P-type fet and the fourth N-type fet are electrically connected to the voltage follower module, respectively, the seventh P-type fet is mirror-symmetric to the first P-type fet, and the fourth N-type fet is mirror-symmetric to the second N-type fet.
5. The power supply circuit according to claim 4, wherein the voltage follower module comprises a third N-type field effect transistor, a ninth P-type field effect transistor and a tenth P-type field effect transistor, a gate of the third N-type field effect transistor and a gate of the tenth P-type field effect transistor are respectively electrically connected to the high voltage end of the second resistor, a source of the third N-type field effect transistor and a drain of the tenth P-type field effect transistor are respectively electrically connected to a drain of the fourth N-type field effect transistor, a drain of the third N-type field effect transistor is electrically connected to a gate of the ninth P-type field effect transistor, a source of the tenth P-type field effect transistor is electrically connected to a drain of the ninth P-type field effect transistor, and a source of the ninth P-type field effect transistor is electrically connected to a source of the seventh P-type field effect transistor.
6. The power supply circuit according to claim 1, further comprising a high voltage withstanding unit electrically connected to the bias current generating unit, the reference voltage generating unit, and the voltage stabilizing unit, respectively.
7. The power supply circuit of claim 6, further comprising a third resistor, wherein the third resistor provides a bias voltage for the high voltage tolerant unit.
8. The power supply circuit of claim 6, wherein the high voltage tolerant unit comprises a first high voltage tolerant module, a second high voltage tolerant module and a third high voltage tolerant module, the first high-voltage resistant module is electrically connected with the first mirror image module and comprises a second P-type field effect transistor and a fourth P-type field effect transistor, the second P-type field effect transistor and the fourth P-type field effect transistor are in mirror symmetry, the second high-voltage resistant module is electrically connected with the second mirror image module, the second high-voltage resistant module comprises a sixth P-type field effect transistor which is in mirror symmetry with the second P-type field effect transistor, the third high-voltage resistant module is respectively and electrically connected with the third mirror image module and the voltage following module, the third high-voltage-resistant module comprises an eighth P-type field effect transistor, and the eighth P-type field effect transistor and the second P-type field effect transistor are in mirror symmetry.
9. The power supply circuit according to claim 8, wherein the second P-type fet, the fourth P-type fet, the sixth P-type fet, and the eighth P-type fet are each high voltage transistors.
10. An electronic device characterized by comprising the power supply circuit of any one of claims 1 to 9.
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| CN106774581A (en) * | 2017-01-25 | 2017-05-31 | 杭州士兰微电子股份有限公司 | Low pressure difference linear voltage regulator and integrated system-on-chip |
| CN110568902A (en) * | 2019-10-18 | 2019-12-13 | 广东工业大学 | Reference voltage source circuit |
| CN214042146U (en) * | 2021-01-20 | 2021-08-24 | 珠海格力电器股份有限公司 | Band-gap reference voltage generator |
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| CN114326892B (en) | 2023-05-02 |
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