JP4823829B2 - Reference voltage generator - Google Patents

Description

  The present invention relates to a reference voltage generation circuit using the principle of work function difference between gate electrodes of two field effect transistors.

Conventionally, as shown in FIG. 11, a depletion type field effect transistor and an enhancement type field effect transistor are connected in series, and the difference between the threshold voltages Vth of these field effect transistors is taken out as a reference voltage Vref. There was a reference voltage generation circuit (see, for example, Patent Document 1).
In FIG. 11, a transistor 105 is a depletion type n-type field effect transistor, and a transistor 107 is an enhancement type n-type field effect transistor.
When the field effect transistor is saturated, the drain current id is expressed by the following equation (a).
id = K × (Vgs−Vth) ² ……………… (a)
In the equation (a), K represents a conductivity coefficient, and Vgs represents a gate-source voltage.

Since the same current flows through the transistors 105 and 107, the voltage Vgs7 at the node 108 is expressed by the following equation (b).
Vgs7 = Vth7− (K5 / K7) ^1/2 × Vth5 (b)
In the equation (b), K5 represents the conductivity coefficient of the transistor 105, K7 represents the conductivity coefficient of the transistor 107, Vth5 represents the threshold voltage of the transistor 105, and Vth7 represents the threshold voltage of the transistor 107. ing.
Here, when the conductivity coefficients K5 and K7 are made equal, the equation (b) becomes the following equation (c).
Vgs7 = Vth7−Vth5 (c)
As described above, the voltage Vgs7 at the node 108 is the difference between the threshold voltages of the transistors 105 and 107 to form the reference voltage Vref. FIG.

On the other hand, as shown in FIG. 13, there is a reference voltage generation circuit for supplying a constant current to each of a transistor having an n-type gate and a transistor having a p-type gate and taking out a difference between threshold voltages of these transistors as a reference voltage Vref. (For example, refer to Patent Document 2).
In FIG. 13, the constant current Io can be expressed by the following equation (d) by flowing a constant current Io through the transistor T1 having an n-type gate and the transistor T2 having a p-type gate having substantially the same conductivity coefficient K. .
Io = K × (V1−Vth1) ² = K × (V2−Vth2) ² (d)
In the equation (d), V1 is the drain-source voltage of the transistor T1, Vth1 is the threshold voltage of the transistor T1, V2 is the drain-source voltage of the transistor T2, and Vth2 is the threshold voltage of the transistor T2. Each threshold voltage is shown.

From the equation (d),
V2-V1 = Vth2-Vth1
Thus, by extracting the difference between the drain voltages of the transistors T1 and T2, the difference between the threshold voltages of the transistors T1 and T2 can be extracted.
FIG. 14 shows a circuit diagram for extracting the drain voltage difference (see, for example, Patent Document 2). In the circuit of FIG. 14, the threshold voltages of the transistors T1 and T2 are set to different values by changing the composition of the gate electrode of the transistor, instead of using two types of transistors of depletion type and enhancement type.
Japanese Patent Publication No. 4-65546 JP 54-132753 A

However, the circuit of FIG. 11 has the following three problems.
The first problem is that since two types of transistors, a depletion type and an enhancement type, are used, the threshold voltage Vth of each transistor fluctuates independently due to process variation, and the initial value of the reference voltage Vref The accuracy will be worse. As shown in FIG. 15, if the variation of the threshold voltage Vth of each transistor is ΔVth5 and ΔVth7, the variation of the reference voltage Vref varies from − (ΔVth5 + ΔVth7) to (ΔVth5 + ΔVth7). For example, when Vth5 = −0.5V, Vth7 = 0.5V, and ΔVth5 = ΔVth7 = 0.15V, the reference voltage Vref varies from 0.7V to 1.3V (± 30%). There was a problem that the fluctuation of the voltage Vref was large.

  The second problem is that, since two types of transistors, a depletion type and an enhancement type, are used, the temperature characteristics of the potential difference in the channel region of these transistors are not the same, so that the temperature characteristics deteriorate. is there. Therefore, in order to improve temperature characteristics, the ratio S5 (= W / L) of the channel width W and the channel length L of the transistor 105 and the ratio S7 (= W / L) of the channel width W and the channel length L of the transistor 107 Even when the ratio (S5 / S7) was adjusted, it was only about 300 ppm / ° C. Thus, there is a problem that the temperature characteristic of the reference voltage Vref is large.

The third problem is that the source-drain voltages Vds5 and Vds7 of the transistors 105 and 107 are
Vds5 = VCC-Vg7
Vds7 = Vg7
It becomes. Therefore, when the power supply voltage VCC varies, the source-drain voltage Vds5 of the transistor 105 also varies, and the reference voltage Vref varies according to the variation of the power supply voltage VCC. As shown in FIG. 16, when the power supply voltage VCC increases, the curve indicating the relationship between the gate-source voltage Vgs of the transistor 105 and the drain current id shifts, and the reference voltage Vref increases by ΔVref. there were.

  On the other hand, in the circuit of FIG. 14, the first and second problems can be solved, but the third problem cannot be solved because a resistor is used as a constant current source. It was.

  The present invention has been made to solve such a problem, and an object of the present invention is to obtain a reference voltage generating circuit capable of reducing variations in the reference voltage due to process variations, temperature variations, and power supply voltage variations. .

The reference voltage generation circuit according to the present invention is a reference voltage generation circuit that generates and outputs a predetermined reference voltage.
A first field effect transistor that is a depletion type n-channel field effect transistor, one end of which is connected to a predetermined power supply voltage;
A second field effect transistor having a high concentration n-type gate, one end connected to the other end of the first field effect transistor;
A resistor having one end connected to the other end of the second field effect transistor;
A third field effect transistor having a high concentration p-type gate, one end connected to the other end of the resistor and the other end connected to a ground voltage;
With
A gate of the first field effect transistor is connected to a connection portion between the first field effect transistor and the second field effect transistor, and a substrate of each of the first and third field effect transistors. The gates are respectively connected to a ground voltage, and the gate and substrate gate of the second field effect transistor, and the gate of the third field effect transistor are connection portions of the second field effect transistor and the resistor. And the reference voltage is output from a connection portion between the resistor and the third field effect transistor.

The reference voltage generation circuit according to the present invention is a reference voltage generation circuit that generates and outputs a predetermined reference voltage.
A first field effect transistor that is a depletion type n-channel field effect transistor, one end of which is connected to a predetermined power supply voltage;
A second field effect transistor having a high concentration n-type gate, one end connected to the other end of the first field effect transistor;
A resistor having one end connected to the other end of the second field effect transistor;
A third field effect transistor having a high concentration p-type gate, one end connected to the other end of the resistor and the other end connected to a ground voltage;
With
A gate of the first field effect transistor is connected to a connection portion between the first field effect transistor and the second field effect transistor, and a substrate of each of the first to third field effect transistors. The gates are respectively connected to a ground voltage, and the gates of the second and third field effect transistors are respectively connected to connection portions of the second field effect transistors and the resistors, and the resistors and the third The reference voltage is output from the connection with the field effect transistor.

  Specifically, the resistor is a metal thin film resistor, for example, made of CrSi.

  Further, the resistor may be a variable resistor.

  The second field effect transistor may be a field effect transistor having a variable channel length.

  According to the reference voltage generating circuit of the present invention, for example, the reference voltage generated by the reference voltage generating circuit has an initial accuracy from ± 30% to ± 6% and a temperature characteristic from 300 ppm / ° C. relative to the conventional circuit. It is improved to 40ppm / ° C respectively, and the fluctuation of the reference voltage Vref with respect to the fluctuation of the power supply voltage can be reduced to 1/10 or less, and the fluctuation of the reference voltage due to the process fluctuation, the temperature fluctuation and the fluctuation of the power supply voltage can be reduced. Furthermore, since the reference voltage can be set freely, the reference voltage can be supplied to a circuit that requires low voltage operation.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a circuit diagram showing an example of a reference voltage generation circuit according to the first embodiment of the present invention.
In FIG. 1, a reference voltage generating circuit 1 is composed of n-channel field effect transistors M1 to M3 and a metal thin film resistor resistor R1 formed of CrSi, and an electric field between a power supply voltage VCC and a ground voltage GND. The effect transistor M1, the field effect transistor M2, the resistor R1, and the field effect transistor M3 are connected in series in this order. The field effect transistor M1 serves as a first field effect transistor, the field effect transistor M2 serves as a second field effect transistor, and the field effect transistor M3 serves as a third field effect transistor.

  The field effect transistor M1 is a depletion type transistor formed in a p-well of an n-type substrate, the gate and source are connected, and the substrate gate is connected to the ground voltage GND. The field effect transistors M2 and M3 have the same substrate and channel-doped impurity concentrations and are respectively formed in the p-well of the n-type substrate. The field-effect transistor M2 has a high-concentration n-type gate, and the field-effect transistor M3 has a high concentration. Has a p-type gate. The gates of the field effect transistors M2 and M3 and the substrate gate of the field effect transistor M2 are connected to a connection node A1 between the field effect transistor M2 and the resistor R1, respectively. A connection portion between the resistor R1 and the field effect transistor M3 forms an output terminal for outputting the reference voltage Vref, and the field effect transistor M2 forms a constant current source. The substrate gate of the field effect transistor M3 is connected to the ground voltage.

In such a configuration, first, a reference voltage generation circuit having the configuration of FIG. 2 without the resistor R1 of FIG. 1 will be described. In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals.
In the case of FIG. 2, the reference voltage Vref is expressed by the following equation (1).
Vref = VthM3− (KM2 / KM3) ^1/2 × VthM2 (1)
In the equation (1), KM2 is the conductivity coefficient of the field effect transistor M2, KM3 is the conductivity coefficient of the field effect transistor M3, VthM2 is the threshold voltage of the field effect transistor M2, and VthM3 is the threshold of the field effect transistor M3. Each value voltage is shown.
When the conductivity coefficients of the field effect transistors M2 and M3 are made equal, the equation (1) becomes the following equation (2).
Vref = VthM3-VthM2 (2)
From the equation (2), the reference voltage Vref is a voltage difference between the threshold voltages of the field effect transistors M2 and M3.

Next, FIG. 3 shows the respective Vgs-id characteristics showing the relationship between the gate-source voltage Vgs and the drain current id in the field effect transistors M2 and M3.
In FIG. 3, since the source and gate of the field effect transistor M2 are connected, the drain current of id2 flows. Since the field effect transistor M3 is connected in series with the field effect transistor M2, the current of id2 similarly flows, and the voltage difference between the gate-source voltages Vgs of the field effect transistors M2 and M3 at this time is the reference voltage. Vref.

  Therefore, even if the impurity concentration of the substrate and the channel dope varies due to process variations, the respective concentrations of the field effect transistors M2 and M3 also vary. For this reason, as shown in FIG. 4, the Vgs-id characteristics of the field effect transistors M2 and M3 are merely shifted to the left and right while maintaining the relationship of FIG. 3, and the absolute value of the reference voltage Vref is hardly affected. A stable reference voltage Vref can be generated without giving Also, from the experimental results, the variation in the reference voltage Vref is about ± 1%, and the variation in the reference voltage Vref can be reduced.

  The field effect transistors M2 and M3 are depletion type transistors having the same substrate and channel-doped impurity concentration, the field effect transistor M2 has a high concentration n-type gate, and the field effect transistor M3 has a high concentration p-type gate. Even if the temperature characteristics of the potential difference between the channel regions of the field effect transistors M2 and M3 are made equal, that is, the conductivity coefficient in the above equation (1) is made equal, The obtained reference voltage Vref has a temperature characteristic of about −500 ppm / ° C. However, the temperature characteristic uses two types of field effect transistors of depletion type and enhancement type, and there is no temperature characteristic of the work function difference of the gate, but the potential difference between the channel regions of the field effect transistors M2 and M3. The temperature characteristics are smaller than those of the prior art shown in FIG.

Therefore, the ratio S2 (= W2 / L2) of the channel width W2 and the channel length L2 of the field effect transistor M2 and the ratio S3 (= W3 / L3) of the channel width W3 and the channel length L3 of the field effect transistor M3 are respectively adjusted. Further, the temperature characteristics of the reference voltage Vref are improved.
FIG. 5 is a diagram showing experimental data of temperature characteristics of the reference voltage Vref when the ratio of S3 / S2 is changed, and FIG. 5 shows experimental data when 25 ° C. is set as the center.
In FIG. 5, the solid line indicates a case where S3 / S2 = 1.00, and the temperature characteristic of the reference voltage Vref at this time is negative and is −545 ppm / ° C. Further, the broken line in FIG. 5 shows the case of S3 / S2 = 0.67, and the temperature characteristic of the reference voltage Vref at this time is negative and is −191 ppm / ° C.

  The one-dot chain line in FIG. 5 shows a case where S3 / S2 = 0.50, and the temperature characteristic of the reference voltage Vref at this time is positive and becomes 60 ppm / ° C. The two-dot chain line in FIG. 5 indicates the case where S3 / S2 = 0.45, and the temperature characteristic of the reference voltage Vref at this time is positive and is 154 ppm / ° C. That is, it can be seen that there is a minimum point of the temperature characteristic of the reference voltage Vref when S3 / S2 is a value between 0.5 and 0.67. The value of S3 / S2 at which the minimum point is estimated is 0.54 to 0.58, and the temperature characteristic of the reference voltage Vref at that time is about 40 ppm / ° C. Thus, the temperature characteristic of the reference voltage Vref can be reduced by changing the value of S3 / S2. However, in this case, since the conductivity coefficient of the equation (1) remains, the variation in the reference voltage Vref becomes as large as about ± 5 to 6%, but the variation in the reference voltage Vref can be made smaller than in the past.

Next, FIG. 6 is a diagram showing an example of the Vs-is characteristic showing the relationship between the source voltage Vs and the source current is of the field effect transistor M1.
FIG. 6 shows the source current is that flows when the power supply voltage VCC is changed to VA, VB, and VC to increase the source voltage Vs in the field effect transistor M1. For example, when the power supply voltage VCC is VA, the source current is rapidly decreases when the source voltage Vs approaches VA, and the source current is becomes 0 when Vs = VA. As shown in FIG. 3, the drain current of id2 flows through the field effect transistor M2 forming the constant current source, and the current of id2 flows through the field effect transistor M1 on the same current path.

  Therefore, the source voltage Vs of the field effect transistor M1 is fixed to VCC2 regardless of the power supply voltage VCC. However, since the value of the source voltage Vs of the field effect transistor M1 when id2 becomes too small and becomes id2a is VCC2a, when VCC = VB or VCC = VC, VCC2a <VB and VCC2a <VC. Yes, the source voltage Vs of the field effect transistor M1 is fixed to VCC2a. However, when VCC = VA, since VCC2a> VA, the source voltage Vs of the field effect transistor M1 is only VA. Therefore, the necessary current id2 or VCC2 must be set according to the minimum operating voltage of the circuit, but this can be easily obtained by adjusting the gate width W / gate length L of the field effect transistor M1. .

As described above, by providing the field effect transistor M1, the source-drain voltages VdsM2 and VdsM3 of the field effect transistors M2 and M3 are
VdsM2 = VCC2-Vref
VdsM3 = Vref
Therefore, even if the power supply voltage VCC varies, the source-drain voltages of the field effect transistors M2 and M3 are not affected and the reference voltage Vref does not vary.

FIG. 7 is experimental data showing the power supply voltage dependence of the reference voltage Vref with and without the field effect transistor M1.
As can be seen from FIG. 7, the voltage fluctuation of the reference voltage Vref in the presence of the field effect transistor M1 is 0.4 mV, which is 1/10 or less that in the absence of the field effect transistor M1. As described above, by providing the field effect transistor M1, it is possible to reduce the fluctuation of the reference voltage Vref with respect to the fluctuation of the power supply voltage VCC.
However, in the case of the circuit of FIG. 2, the reference voltage Vref is the voltage difference between the threshold voltages of the field effect transistors M2 and M3 as shown in the above equation (2), so that the voltage can be set freely. In particular, the reference voltage Vref cannot be supplied to a circuit that requires low voltage operation.

Therefore, in the reference voltage generating circuit 1 in the first embodiment, a resistor R1 is inserted between the field effect transistors M2 and M3 as shown in FIG. Hereinafter, the reference voltage generation circuit 1 of FIG. 1 will be described.
In the case of FIG. 1, when the voltage of the connection node A1 is V1, the voltage V1 is the same as the reference voltage Vref of FIG.
V1 = VthM3− (KM2 / KM3) ^1/2 × VthM2 (3)
When the conductivity coefficients of the field effect transistors M2 and M3 are made equal, the equation (3) becomes the following equation (4).
V1 = VthM3-VthM2 (4)
From the equation (4), the voltage V1 is the voltage difference between the threshold voltages of the field effect transistors M2 and M3.

The voltage V1 varies in the same manner as the reference voltage Vref shown in FIG. 4 because the respective concentrations of the field effect transistors M2 and M3 vary in the same manner even if the impurity concentration of the substrate or channel dope varies due to process variations. The absolute value is hardly affected.
Next, in FIG. 1, there is a resistor R1 between the reference voltage Vref and the voltage V1, and a voltage drop due to the resistor R1 occurs. Therefore, the reference voltage Vref is expressed by the following equation (5).
Vref = V1-R × id2 (5)
In the equation (5), R is the resistance value of the resistor R1, and id2 is a constant current.
In this way, it is possible to obtain the reference voltage Vref whose voltage is small by the voltage drop (= R × id2) due to the resistor R1. The voltage drop due to the resistor R1 can be controlled by the resistance value of the resistor R1 and the constant current id2 from the field effect transistor M2.

FIG. 8 is a diagram showing a configuration example when the resistor R1 is a variable resistor.
In FIG. 8, the resistor R1 includes resistors R10 to R16, which are metal thin film resistors made of CrSi, and fuses F10 and F11.
Resistors R10, R11, and R13 are connected in series between the field effect transistors M2 and M3, and a resistor R12 and a fuse F10 are connected in parallel to the resistor R11. In addition, resistors R14 to R16 and a fuse F11 are connected in parallel to the resistor R13.
In such a configuration, since the resistance value of the resistor R1 can be adjusted by trimming the fuse F10 and / or F11 with a laser, the voltage drop of the resistor R1 can be made constant.

FIG. 9 is a diagram showing a configuration example when the channel length of the field effect transistor M2 of FIG. 1 is made variable. In FIG. 9, the field effect transistor M2 includes n-channel field effect transistors M20 to M26 having high-concentration n-type gates and fuses F20 and F21.
Field effect transistors M20, M21 and M23 are connected in series between the field effect transistor M1 and the resistor R1. In the field effect transistors M20, M21 and M23, the gates are connected and the substrate gates are connected. The connection portions are connected to the connection node A1.

  A field effect transistor M22 and a fuse F20 are respectively connected in parallel to the field effect transistor M21, and a gate and a substrate gate of the field effect transistor M22 are respectively connected to a connection node A1. Further, field effect transistors M24 to M26 and a fuse F21 are connected in parallel to the field effect transistor M23. In the field effect transistors M24 to M26, each gate and each substrate gate are respectively connected to the connection node A1. .

In such a configuration, by trimming the fuse F20 and / or F21 with a laser, the channel length L of the field effect transistor M2 can be adjusted to adjust the drain current id2, so that the voltage drop of the resistor R1 can be reduced. Can be constant.
1 may be configured as shown in FIG. 8, and / or the field effect transistor M2 shown in FIG. 1 may be configured as shown in FIG.

Thus, a stable voltage V1 and a voltage drop across the resistor R1 can be obtained, so that a stable reference voltage Vref that is resistant to process variations can be obtained.
Further, since the reference voltage generating circuit 1 of FIG. 1 is simply the addition of the resistor R1 having almost no temperature characteristics to the circuit of FIG. 2, the temperature characteristics are also as shown in FIG. However, when the channel length L of the field effect transistor M2 is adjusted as shown in FIG. 9, the field effect transistor M3 is also adjusted to have the same circuit configuration as that of FIG. The ratio needs to be 0.54 to 0.58. However, in this case, even when the resistance R1 has temperature characteristics due to process variations, the ratio of S3 / S2 can be adjusted so as to cancel the temperature characteristics of the resistance R1.

Further, since the source voltage of the field effect transistor M1 is fixed to VCC2 regardless of the power supply voltage VCC as shown in FIG. 6, the source-drain voltages VdsM2 and VdsM3 of the field effect transistors M2 and M3 are:
VdsM2 = VCC2- (R × id2 + Vref)
VdsM3 = Vref
Therefore, even if the power supply voltage VCC fluctuates, the source-drain voltages of the field effect transistors M2 and M3 are constant without being affected by them, and the reference voltage Vref does not fluctuate.

  As described above, the reference voltage generation circuit in the first embodiment has an initial accuracy improved from ± 30% to ± 6% and a temperature characteristic from 300 ppm / ° C. to 40 ppm / ° C. with respect to the conventional circuit. Furthermore, the fluctuation of the reference voltage Vref with respect to the fluctuation of the power supply voltage can be reduced to 1/10 or less, and the voltage of the reference voltage Vref can be freely set. Vref can be supplied.

Second embodiment.
In the first embodiment, the substrate gate of the field effect transistor M2 is connected to the source of the field effect transistor M2. However, the substrate gate of the field effect transistor M2 is connected to the ground voltage GND. This is what is described as a second embodiment of the present invention.
FIG. 10 is a circuit diagram showing an example of a reference voltage generation circuit according to the second embodiment of the present invention. In FIG. 10, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted here, and only differences from FIG. 1 are described.
10 is different from FIG. 1 in that the substrate gate of the field effect transistor M2 is connected to the ground voltage GND. Accordingly, the reference voltage generation circuit 1 of FIG. 1 is changed to a reference voltage generation circuit 1a.

In such a configuration, the respective concentrations of the field effect transistors M2 and M3 similarly vary even if the impurity concentration of the substrate and the channel dope varies due to process variations, as in FIG. For this reason, as shown in FIG. 4, the Vgs-id characteristics of the field effect transistors M2 and M3 are merely shifted to the left and right while maintaining the relationship of FIG. 3, and the absolute value of the reference voltage Vref is hardly affected. A stable reference voltage Vref can be generated without giving
Further, since a substrate bias effect is generated in the field effect transistor M2, the potential difference in the channel region has a slight temperature characteristic as compared with the first embodiment, but the temperature characteristic is smaller than the conventional one. .

Therefore, the temperature characteristic of the reference voltage Vref can be reduced by adjusting the ratio of S3 / S2 as in the first embodiment.
Since the source-drain voltages VdsM2 and VdsM3 of the field effect transistors M2 and M3 are the same as those in the first embodiment, even if the power supply voltage VCC varies, the source-drain voltages VdsM2 and VdsM3 of the field effect transistors M2 and M3 The drain-to-drain voltage is not affected and the reference voltage Vref does not fluctuate.

  As described above, the reference voltage generation circuit according to the second embodiment can obtain the same effects as those of the first embodiment. For example, the field effect transistors M1 to M3 are provided in a p-type substrate. This can be used when the substrate voltage of the field effect transistor M2 is fixed to the ground voltage GND, such as when configured. Furthermore, since all the substrate voltages of the field effect transistors M1 to M3 are the ground voltage GND, it is not necessary to provide a space between the field effect transistors, and the chip area can be reduced.

  In addition, what is necessary is just to select the said 1st Embodiment or 2nd Embodiment on a case-by-case basis, such as a noise characteristic.

FIG. 3 is a circuit diagram illustrating an example of a reference voltage generation circuit according to the first embodiment of the present invention. FIG. 2 is a circuit diagram for explaining a basic operation of the reference voltage generation circuit 1 of FIG. 1. It is the figure which showed the example of each Vgs-id characteristic in field effect transistor M2 and M3. It is the figure which showed the dispersion | variation by the process fluctuation | variation in the Vgs-id characteristic of the field effect transistors M2 and M3. It is the figure which showed the experimental data of the temperature characteristic of the reference voltage Vref when changing ratio of S3 / S2. It is the figure which showed the example of the Vs-is characteristic of the field effect transistor M1. It is experimental data which showed the power supply voltage dependence of the reference voltage Vref by the presence or absence of the field effect transistor M1. It is the figure which showed the structural example of resistance R1 of FIG. It is the figure which showed the structural example of the field effect transistor M2 of FIG. It is the circuit diagram which showed the example of the reference voltage generation circuit in the 2nd Embodiment of this invention. It is a circuit diagram showing an example of a conventional reference voltage generation circuit. It is the figure which showed the example of each Vgs-id characteristic in the field effect transistors 105 and 107 of FIG. FIG. 6 is a circuit diagram showing another example of a conventional reference voltage generation circuit. FIG. 6 is a circuit diagram showing another example of a conventional reference voltage generation circuit. It is the figure which showed the dispersion | variation by the process variation in the Vgs-id characteristic of the field effect transistors 105 and 107 of FIG. It is the figure which showed the fluctuation | variation of the Vgs-id characteristic of the field effect transistor 105 of FIG. 11 accompanying a power supply voltage fluctuation.

Explanation of symbols

1,1a Reference voltage generation circuit M1-M3, M20-M26 Field effect transistor R1, R10-R16 Resistance F10, F11, F20, F21 Fuse

Claims (6)

In a reference voltage generation circuit that generates and outputs a predetermined reference voltage,
A first field effect transistor that is a depletion type n-channel field effect transistor, one end of which is connected to a predetermined power supply voltage;
A second field effect transistor having a high concentration n-type gate, one end connected to the other end of the first field effect transistor;
A resistor having one end connected to the other end of the second field effect transistor;
A third field effect transistor having a high concentration p-type gate, one end connected to the other end of the resistor and the other end connected to a ground voltage;
With
A gate of the first field effect transistor is connected to a connection portion between the first field effect transistor and the second field effect transistor, and a substrate of each of the first and third field effect transistors. The gates are respectively connected to a ground voltage, and the gate and substrate gate of the second field effect transistor, and the gate of the third field effect transistor are connection portions of the second field effect transistor and the resistor. And a reference voltage generating circuit, wherein the reference voltage is output from a connection portion between the resistor and the third field effect transistor. In a reference voltage generation circuit that generates and outputs a predetermined reference voltage,
A first field effect transistor that is a depletion type n-channel field effect transistor, one end of which is connected to a predetermined power supply voltage;
A second field effect transistor having a high concentration n-type gate, one end connected to the other end of the first field effect transistor;
A resistor having one end connected to the other end of the second field effect transistor;
A third field effect transistor having a high concentration p-type gate, one end connected to the other end of the resistor and the other end connected to a ground voltage;
With
A gate of the first field effect transistor is connected to a connection portion between the first field effect transistor and the second field effect transistor, and a substrate of each of the first to third field effect transistors. The gates are respectively connected to a ground voltage, and the gates of the second and third field effect transistors are respectively connected to connection portions of the second field effect transistors and the resistors, and the resistors and the third A reference voltage generating circuit, wherein the reference voltage is output from a connection portion with the field effect transistor.   3. The reference voltage generating circuit according to claim 1, wherein the resistor is a metal thin film resistor.   4. The reference voltage generating circuit according to claim 3, wherein the resistor is made of CrSi.   5. The reference voltage generating circuit according to claim 3, wherein the resistor is a variable resistor.   6. The reference voltage generating circuit according to claim 1, wherein the second field effect transistor is a field effect transistor having a variable channel length.

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