CN106773905A - A kind of being disappeared based on power supply sequential trembles the switching value output circuit of control - Google Patents
A kind of being disappeared based on power supply sequential trembles the switching value output circuit of control Download PDFInfo
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- CN106773905A CN106773905A CN201611050607.6A CN201611050607A CN106773905A CN 106773905 A CN106773905 A CN 106773905A CN 201611050607 A CN201611050607 A CN 201611050607A CN 106773905 A CN106773905 A CN 106773905A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
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Abstract
Tremble the switching value output circuit of control the invention discloses a kind of disappearing based on power supply sequential, including be connected with each other power supply sequential disappear tremble control circuit and switching value output circuit；Power supply sequential disappears twitter circuit including power supply circuit and sequential control circuit, power supply circuit provides the control signal of power supply input signal and sequential control circuit, sequential control circuit processes power supply input signal, and the power supply signal of optimization is exported to switching value output circuit.Therefore, the present invention utilizes the speed-sensitive switch and voltage stabilization characteristic of metal-oxide-semiconductor, design a kind of power supply sequential and disappear and tremble control circuit, improve the input timing relation and driving force of power supply signal, optimization power supply signal quality, the control signal of the sequential control circuit is provided by power supply circuit itself, and multiple power sources input signal is carried out into serial process, ensure that whole power output signals are managed by unified signal, it is ensured that the uniformity of power supply signal sequential.
Description
Technical field
The invention belongs to Digital Circuit Control field, particularly a kind of being disappeared based on power supply sequential trembles the output switch parameter of control
Circuit.
Background technology
Output switch parameter is that the analog signal or digital controlled signal of sensor sensing are converted into on-off model, and is carried
The switch for being provided as load circuit is used.Under normal circumstances, switching value is realized using electromagnetism or solid-state relay.Switching value is present
Disconnect and closure two states, the occupation mode of switching value output signal ensures that switch is in a kind of steady state, that is, keep disconnected
Open or closure state, be output loading circuit stability.
Due to design on control circuit problem, traditional numerical control switch amount output signal may be produced of short duration in closure
Switch from fluttering phenomenon.I.e. before the closure state that on-off model is stabilization, switch occurs once or many in very short time
Secondary intersection break-make.In most cases, for response time requirement control system not high or the relatively low system of control accuracy,
The influence that switching value is shaken to system is smaller.But, for the precision equipment in high-precision control system or system, what it was required
Control accuracy and response time are very high, it will usually be accurate to " microsecond " level.Fault diagnosis is commonly provided with High Definition Systems to set
It is standby, if there is jitter phenomenon in switching value, it will cause failure diagnosis apparatus to alarm.If not having fault diagnosis in system to set
Standby, then the intersection break-make of switching value can cause the unstable of load circuit, under extreme case, may cause the toning of system or shake
Swing.
The content of the invention
The present invention is provided a kind of being disappeared based on power supply sequential and trembles the switching value output circuit of control, its power supply sequencing control circuit
The advantages of possessing simple design, Parameter adjustable, control accuracy high, it is adaptable in the complex control system of high-precision requirement, switch
The precise control of output signal is measured, the smoothing processing of the break-make of on-off model is effectively realized, meanwhile, power supply sequential of the invention
Control circuit can be widely applied for other numerical control system fields.
The technical solution for realizing the object of the invention is：A kind of being disappeared based on power supply sequential trembles the output switch parameter electricity of control
Road, including be connected with each other power supply sequential disappear tremble control circuit and switching value output circuit；The power supply sequential disappears twitter circuit
Including power supply circuit and sequential control circuit, the power supply circuit provides the control of power supply input signal and sequential control circuit
Signal processed, sequential control circuit treatment power supply input signal, the power supply signal of optimization is exported to switching value output circuit.
As a further improvement, the power supply circuit include signal output part, first resistor, second resistance, 3rd resistor,
4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the first triode, the second triode, the 3rd triode；
Power supply signal input+1.8V-A is connected with one end of first resistor, and the other end of first resistor is respectively with the 4th
The ground level connection of one end of resistance and the 3rd triode, the other end of the 4th resistance respectively with one end, the 6th of the 5th resistance
The emitter stage of one end of resistance and the 3rd triode is connected, and the emitter stage of the 3rd triode is grounded simultaneously；Power supply signal
Input+5V-CPCI is connected with one end of second resistance, the other end of second resistance respectively with the other end of the 5th resistance and
The ground level connection of the second triode；Power supply signal input+3.3V-CPCI is connected with one end of 3rd resistor, 3rd resistor
The other end is connected with the other end of the 6th resistance and the base stage of the first triode respectively；Power supply signal input+5V-CPCI with
One end connection of the 7th resistance, the other end of the 7th resistance is connected and signal output part with the colelctor electrode of the first triode respectively
Connection, the emitter stage of the first triode is connected with the colelctor electrode of the second triode, the emitter stage of the second triode and the three or three pole
The colelctor electrode connection of pipe.
As a further improvement, the sequential control circuit includes signal input part, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the
Three metal-oxide-semiconductors, the first electric capacity, the second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity, the 8th electricity
Hold and the 9th electric capacity；
The grid of signal input part grid, the grid of the second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor respectively with the first metal-oxide-semiconductor connects
Connect；
Power supply signal input+5V-CPCI is connected with the source electrode of the first metal-oxide-semiconductor, first electric capacity, the second electric capacity and
3rd electric capacity is in parallel and is arranged in the drain electrode of the first metal-oxide-semiconductor, positive electrode and signal+the 5VRUN connection of the 3rd electric capacity, negative electrode
Ground connection；
Power supply signal input+3.3V-CPCI is connected with the source electrode of the second metal-oxide-semiconductor, the 4th electric capacity, the 5th electric capacity with
And the 6th electric capacity it is in parallel and be arranged in the drain electrode of the second metal-oxide-semiconductor, positive electrode and signal+the 3.3VRUN connection of the 6th electric capacity are born
Electrode is grounded；
Power supply signal input+1.8V-A is connected with the source electrode of the 3rd metal-oxide-semiconductor, the 7th electric capacity, the 8th electric capacity and
9th electric capacity is in parallel and is arranged in the drain electrode of the 3rd metal-oxide-semiconductor, positive electrode and signal+the 1.8VRUN connection of the 9th electric capacity, negative electricity
Pole is grounded.
As a further improvement, the switching value output circuit includes the FPGA circuitry, the bus driving circuits that are sequentially connected
And solid-state relay circuit；FPGA circuitry provides the control signal of relay, and bus driving circuits strengthen the electricity of control signal
Flat driving force, 5V level signals are converted to by the 3.3V level signals of FPGA, and solid-state relay circuit provides output switch parameter
Signal, for the load of rear end provides controlled output.
As a further improvement, the FPGA circuitry includes fpga chip, configuration chip and clock chip, the bus
Drive circuit includes general line system chip and the 8th resistance, and the solid-state relay circuit includes solid-state relay chip, the
Nine resistance, diode and fuse；
Power supply signal input+3.3VRUN is turned with the GPIOn pins and bus of fpga chip respectively by the 8th resistance
The pin IN1 connections of chip are changed, power supply signal input+1.8VRUN is connected with the pin EN of general line system chip, general line system
The pin OUT1 of chip is connected with the pin 3 of solid-state relay chip, and the pin 1 and pin 4 of solid-state relay chip are hanging, Gu
The pin 2 of body relay chip is connected by the 9th resistance with power supply input signal+5VRUN；
The pin 5 of the solid-state relay chip is connected with pin 8, pin 7 respectively with the positive pole of pin 6, diode with
And digital switch quantity output signal anode OUTn+ connections, the negative pole and pin 8 of the diode connect, and by fuse and
Digital switch quantity output signal negative terminal OUTn- is connected.
Compared with prior art, its remarkable advantage is the present invention：1) compared to existing power supply SECO technology, the present invention
Designed using simplifying, power supply SECO parameter configuration is more flexible, has for specific design on control circuit scheme stronger
Specific aim, be with a wide range of applications.2) compared to existing switching value output circuit, power supply sequencing control circuit effectively disappears
Except switching value is because of on off state shake caused by the minimum power supply time difference, the levels of precision of output switch parameter control is improved.3) effectively
FPGA is avoided in initialization procedure, the influence of its I/O signal level variation switch amount control signal.So that output switch parameter
Signal smoothing, improves the service life and functional reliability of relay.
The present invention is described in further detail below in conjunction with the accompanying drawings.
Brief description of the drawings
Fig. 1 is the switching value output circuit theory diagram of power supply SECO of the invention.
Fig. 2 is power supply circuit of the invention.
Fig. 3 is sequential control circuit figure of the invention.
Fig. 4 is output switch parameter application circuit of the invention.
Fig. 5 is solid-state relay of the invention inside schematic diagram.
Specific embodiment
In the digital circuit of cpci bus framework, power supply circuit by cpci bus power supply signal and power transfer module
There is provided, need the power supply timing of the power supply signal of different voltage magnitudes, various power supply signals to exist successively in same functional module
Sequential relationship, will cause backend application circuit operation irregularity, reduce the stability and reliability of application circuit, can be led when serious
The hyperharmonic vibration of cause system.
Application circuit in the present invention is the switching value output circuit based on extensive Programmable Logic Controller FPGA controls, should
Electricity consumption route FPGA circuitry, bus driving circuits, solid-state relay circuit are constituted.Requirement of the application circuit to power supply sequential compared with
Height, if power supply signal has time sequence difference relation, will cause FPGA control signals to be moved with the switch of solid-state relay
Make simultaneously match, cause solid-state relay to produce frequently switch motion, i.e., switched during application circuit is initialized
Amount output produces jitter phenomenon.The circuit causes that the generation timing sequence of power supply is strictly controlled, and then ensures that digital output modul is believed
The uniformity of number state, the pattern is applied to high-precision control system field.
With reference to Fig. 1 to Fig. 4, a kind of being disappeared based on power supply sequential of the invention trembles the switching value output circuit of control, including mutual
The power supply sequential of connection disappears and trembles control circuit and switching value output circuit；Power supply sequential disappear twitter circuit including power supply circuit and
Sequential control circuit, power supply circuit provides the control signal of power supply input signal and sequential control circuit, sequential control circuit
Treatment power supply input signal, the power supply signal of optimization is exported to switching value output circuit.
Power supply circuit include signal output part a, first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4,
5th resistance R5, the 6th resistance R6, the 7th resistance R7, the first triode D1, the second triode D2, the 3rd triode D3；
Power supply signal input+1.8V-A is connected with one end of first resistor R1, the other end of first resistor R1 respectively with
The ground level connection of one end of the 4th resistance R4 and the 3rd triode D3, the other end of the 4th resistance R4 respectively with the 5th resistance R5
One end, one end of the 6th resistance R6 and the 3rd triode D3 emitter stage be connected, the emitter stage of the 3rd triode D3
It is grounded simultaneously；Power supply signal input+5V-CPCI is connected with one end of second resistance R2, the other end difference of second resistance R2
It is connected with the other end of the 5th resistance R5 and the ground level of the second triode D2；Power supply signal input+3.3V-CPCI and the 3rd
One end connection of resistance R3, the other end of 3rd resistor R3 respectively with the other end of the 6th resistance R6 and the first triode D1
Base stage is connected；Power supply signal input+5V-CPCI is connected with one end of the 7th resistance R7, the other end difference of the 7th resistance R7
It is connected with the colelctor electrode of the first triode D1 and signal output part a connections, the emitter stage of the first triode D1 and the two or three pole
The colelctor electrode connection of pipe D2, the emitter stage of the second triode D2 is connected with the colelctor electrode of the 3rd triode D3.
Sequential control circuit includes signal input part b, the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, the 3rd metal-oxide-semiconductor Q3, first
Electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5, the 6th electric capacity C6, the 7th electric capacity C7, the 8th
Electric capacity C8 and the 9th electric capacity C9；
Signal input part b grids respectively with the first metal-oxide-semiconductor Q1, the grid of the second metal-oxide-semiconductor Q2 and the 3rd metal-oxide-semiconductor Q3's
Grid is connected；
Power supply signal input+5V-CPCI is connected with the source electrode of the first metal-oxide-semiconductor Q1, the first electric capacity C1, the second electric capacity
C2 and the 3rd electric capacity C3 are in parallel to be simultaneously arranged in the drain electrode of the first metal-oxide-semiconductor Q1, and the positive electrode and signal of the 3rd electric capacity C3+
5VRUN is connected, negative electrode ground connection；
Power supply signal input+3.3V-CPCI is connected with the source electrode of the second metal-oxide-semiconductor Q2, the 4th electric capacity C4, the 5th electric capacity C5
And the 6th electric capacity C6 it is in parallel and be arranged in the drain electrode of the second metal-oxide-semiconductor Q2, the positive electrode and signal of the 6th electric capacity C6+
3.3VRUN is connected, negative electrode ground connection；
Power supply signal input+1.8V-A is connected with the source electrode of the 3rd metal-oxide-semiconductor Q3, the 7th electric capacity C7, the 8th electric capacity C8 with
And the 9th electric capacity C9 it is in parallel and be arranged in the drain electrode of the 3rd metal-oxide-semiconductor Q3, the positive electrode and signal+1.8VRUN of the 9th electric capacity C9
Connection, negative electrode ground connection.
Switching value output circuit includes the FPGA circuitry, bus driving circuits and the solid-state relay circuit that are sequentially connected；
FPGA circuitry provides the control signal of relay, and bus driving circuits strengthen the level driver ability of control signal, by FPGA's
3.3V level signals are converted to 5V level signals, and solid-state relay circuit provides switching value output signal, is that the load of rear end is carried
For controlled output.
FPGA circuitry includes fpga chip U1, configuration chip U4 and clock chip U5, and the bus driving circuits include
General line system chip U2 and the 8th resistance R8, the solid-state relay circuit includes solid-state relay chip U3, the 9th resistance
R9, diode V1 and fuse F1；
Power supply signal input+3.3VRUN by the 8th resistance R8 respectively with the GPIOn pins of fpga chip U1 and total
The pin IN1 connections of line conversion chip U2, power supply signal input+1.8VRUN is connected with the pin EN of general line system chip U2,
The pin OUT1 of general line system chip U2 is connected with the pin 3 [V-] of solid-state relay chip U3, solid-state relay chip U3's
Pin 1 [V0+] and pin 4 [V0-] are hanging, and the pin 2 [V-] of solid-state relay chip U3 is defeated with power supply by the 9th resistance R9
Enter signal+5VRUN connections；
The pin 5 [K1+] of solid-state relay chip U3 is connected with pin 8 [K2+], pin 7 [K2-] respectively with pin 6
[K1-], the positive pole of diode V1 and digital switch quantity output signal anode OUTn+ are connected, the negative pole and pin 8 of diode V1
[K2+] is connected, and is connected by fuse F1 and digital switch quantity output signal negative terminal OUTn-.
Further detailed description is done to the present invention with reference to embodiment：
Embodiment
With reference to Fig. 2, the power supply circuit includes three kinds of power supply signals used in circuit, including 5V-CPCI power supplys letter
Number, 3.3V-CPCI power supply signals, 1.8V-A power supply signals, the circuit and sequential control circuit and output switch parameter application circuit
Connection.First resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th electricity in the circuit
Three kinds of power supply signals being input into are carried out appropriate partial pressure by resistance R6, meet the emitter junction forward conduction of triode.In the circuit
First triode D1, the second triode D2, the 3rd triode D3 are connected in series, three kinds of power supply signals as control signal,
It is input to the base stage and transmitting interpolar of D1, D2, D3.A signaling points are believed for sequential control circuit provides control in the power supply circuit
Number.During for loading power signal, a signaling points are high-impedance state.After+5V-CPCI power supply signals are produced, corresponding first triode
D1 is opened, and colelctor electrode and the emitter stage of the triode form conductive channel.Now, a signaling points are pulled to 5V in the circuit.
If after three kinds of power supply signals are produced, the colelctor electrode and emitter stage of corresponding triode D1, D2, D3 are respectively formed conductive channel, make
Obtain a signaling points and be pulled down to GND.After the design ensures that three kinds of power supply signals are produced, the state of the control signal a of output
Low level is changed into from high level.If existing in three kinds of power supply signals, a kind of power supply is delayed, a signaling points are maintained as high level.
With reference to Fig. 3, the sequential control circuit, including power supply circuit output the sequential that constitutes of control signal and metal-oxide-semiconductor
Control circuit, including the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, the 3rd metal-oxide-semiconductor Q3.The power supply circuit is by triode by three kinds
Power supply merges into single control signal, controls the opening and closing of metal-oxide-semiconductor raceway groove, with sequential in three kinds of power supplys relatively after one kind electricity
Source signal is used as clock reference, it is ensured that metal-oxide-semiconductor is opened in the same time, for output switch parameter application circuit provides unified power supply
Power supply signal.The first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, the 3rd metal-oxide-semiconductor Q3 select P-channel metal-oxide-semiconductor.Three kinds of metal-oxide-semiconductors
Operation principle is consistent.By taking the first metal-oxide-semiconductor Q1 as an example, a signaling points are connected with b signaling points.When control signal b is high level (5V), P
The grid voltage of the first metal-oxide-semiconductor of raceway groove Q1 is 5V with source voltage, then the metal-oxide-semiconductor cannot be turned on, now the second metal-oxide-semiconductor Q2 and
3rd metal-oxide-semiconductor Q3 cannot also be turned on.If after three kinds of power supply signals are produced, control signal b is low level (GND), the first metal-oxide-semiconductor
The UGS of Q1 is -5V, meets the cut-in voltage UT of the metal-oxide-semiconductor, and then causes that the drain D of metal-oxide-semiconductor and source S form conducting channel,
Path is formed between drain electrode and source electrode.Now ,+5V-CPCI signals are converted to+5VRUN signals by metal-oxide-semiconductor, now the second metal-oxide-semiconductor
Q2 and the 3rd metal-oxide-semiconductor Q3 can normally.The first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, the ON time of the 3rd metal-oxide-semiconductor Q3
It is basically identical.Therefore, three kinds of systems of power supply signal sequential are produced while power supply signal+5VRUN ,+3.3VRUN ,+1.8VRUN
One.First electric capacity C1 in the sequential control circuit, the second electric capacity C2, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5,
6th electric capacity C6, the 7th electric capacity C7, the 8th electric capacity C8, the 9th electric capacity C9 select different capacitances, to three kinds of power input letters
Number it is filtered and decouples, effectively reduces the ripple and noise of power supply signal.
With reference to Fig. 4, Fig. 5, the output switch parameter application circuit includes FPGA circuitry, bus switching circuit, solid relay
Device circuit.The wherein control signal of FPGA circuitry output relay, the control signal conversion that bus switching circuit exports FPGA
It is the level nature suitable for Control, the break-make of solid-state relay circuit realiration switching value output signal is the present invention
In typical application circuit.FPGA circuitry includes fpga chip U1, configuration chip U4, clock chip U5 in the circuit.FPGA
Chip U1 selects PLD EP2C35F672I8N, the control signal of its I/O pin GPIOn output relay.Configuration
Chip U4 selects EPCS16N, configures the EEPROM information of FPGA, and clock chip U5 selects NB3L553 clock distributors, is FPGA
The work clock of 33MHZ is provided.General line system chip U2, IN1 (3.3V level) control signal that FPGA is exported is converted to
OUT1 (5V level), it is ensured that switching value output circuit normal work.The EN signals of general line system chip dependence+1.8VRUN are carried out
Work is enabled.Solid-state relay circuit U 3 selects JGW-3M light MOS solid-state relays, the pin of chip 2 to be pulled up by the 9th resistance R9
The control signal of relay is constituted with the pin of chip 3 to+5VRUN.If the control signal JKSn of 3 pin of relay is high level
(5V), output switch parameter is off-state.With reference to Fig. 5, if the control signal JKSn of 3 pin of relay is low level, control end
Input voltage be 5V, input turn-on current is more than 5mA, and the Light-Emitting Diode V2 at Control end is turned on so that controlled
Two Opposite direction connection N-channel MOS pipe conductings.Work as LEDs ON, the U of N-channel type metal-oxide-semiconductorGSElectricity is opened more than metal-oxide-semiconductor
Pressure UT, and then cause that the drain D of metal-oxide-semiconductor and source S form conducting channel, form path between drain electrode and source electrode.Output switch parameter
It is channel status.The output signal GPIOn of FPGA circuitry is pulled to+3.3VRUN by the 8th resistance R8, by general line system core
Piece, it is ensured that 3 pin JKSn level default conditions of relay are 5V, and relay is off state.Only when FPGA sends low level control
Signal processed, relay is changed into conducting state, i.e. switching value output signal for conducting state.
If not using sequential control circuit, three kinds of power supply signals in sequential in described output switch parameter application circuit
It is inconsistent.Assuming that 3.3V power supply signals lag behind 5V power supply signals and 1.8V power supply signals, and when FPGA is initialized, fpga chip
GPIOn default configurations be low level, due to the 3.3V level for pulling up be not ready to it is ready, by after electrical level transferring chip, input
The pin JKSn of control signal 3 to relay is low level, and now switching value output signal is conducting state.And work as 3.3V power supplys letter
Number produce after, output switch parameter recover off-state.Because power supply sequential is not unified, the initial phase of the application circuit will lead
Switching value output signal is caused to produce jitter phenomenon.Assuming that 1.8V power supply signals lag behind 5V power supply signals and 3.3V power supply signals.
Then the enable signal EN of bus switching circuit is not ready to ready in the output switch parameter application circuit, causes bus switching circuit
Acquiescence output OUT1 be low level, again such that switching value output signal produces of short duration conducting state, that is, there is switching value
Jitter phenomenon.Switching value shake can cause system detectio fault alarm, and the vibration in control system loop can be caused under serious conditions.
Increase sequential control circuit, three kinds of power supply signals is basic in sequential in described output switch parameter application circuit
It is consistent.In application circuit initial phase, it is ensured that the terminal voltage that controls of relay is 0V, and On-off signal signal stabilization is
Off-state.Only when FPGA produces control signal, solid-state relay is acted accordingly.
Compared to existing power supply SECO technology, using design is simplified, power supply SECO parameter configuration is more for the present invention
Plus flexibly, there is stronger specific aim for specific design on control circuit scheme, it is with a wide range of applications.
Claims (5)
1. a kind of being disappeared based on power supply sequential trembles the switching value output circuit of control, it is characterised in that including the power supply being connected with each other
Sequential disappears and trembles control circuit and switching value output circuit；The power supply sequential disappears twitter circuit including power supply circuit and sequential control
Circuit processed, the power supply circuit provides the control signal of power supply input signal and sequential control circuit, at sequential control circuit
Reason power supply input signal, the power supply signal of optimization is exported to switching value output circuit.
2. a kind of being disappeared based on power supply sequential trembles the switching value output circuit of control according to claim 1, it is characterised in that institute
Stating power supply circuit includes signal output part a, first resistor [R1], second resistance [R2], 3rd resistor [R3], the 4th resistance
[R4], the 5th resistance [R5], the 6th resistance [R6], the 7th resistance [R7], the first triode [D1], the second triode [D2],
Three triodes [D3]；
Power supply signal input+1.8V-A is connected with the one end of first resistor [R1], the other end of first resistor [R1] respectively with
The ground level connection of one end of the 4th resistance [R4] and the 3rd triode [D3], the other end of the 4th resistance [R4] is respectively with the 5th
The emitter stage of one end of resistance [R5], one end of the 6th resistance [R6] and the 3rd triode [D3] is connected, the three or three pole
The emitter stage for managing [D3] is grounded simultaneously；Power supply signal input+5V-CPCI is connected with the one end of second resistance [R2], the second electricity
The other end for hindering [R2] is connected with the other end of the 5th resistance [R5] and the ground level of the second triode [D2] respectively；Power supply signal
Input+3.3V-CPCI is connected with the one end of 3rd resistor [R3], the other end of 3rd resistor [R3] respectively with the 6th resistance
The base stage connection of the other end of [R6] and the first triode [D1]；Power supply signal input+5V-CPCI and the 7th resistance [R7]
One end connection, the colelctor electrode of the other end of the 7th resistance [R7] respectively with the first triode [D1] is connected and signal output part
A is connected, and the emitter stage of the first triode [D1] is connected with the colelctor electrode of the second triode [D2], the transmitting of the second triode [D2]
Pole is connected with the colelctor electrode of the 3rd triode [D3].
3. a kind of being disappeared based on power supply sequential trembles the switching value output circuit of control according to claim 1, it is characterised in that institute
Stating sequential control circuit includes signal input part b, the first metal-oxide-semiconductor [Q1], the second metal-oxide-semiconductor [Q2], the 3rd metal-oxide-semiconductor [Q3], first
Electric capacity [C1], the second electric capacity [C2], the 3rd electric capacity [C3], the 4th electric capacity [C4], the 5th electric capacity [C5], the 6th electric capacity [C6],
Seven electric capacity [C7], the 8th electric capacity [C8] and the 9th electric capacity [C9]；
Signal input part b grids respectively with the first metal-oxide-semiconductor [Q1], the grid of the second metal-oxide-semiconductor [Q2] and the 3rd metal-oxide-semiconductor [Q3]
Grid connection；
Power supply signal input+5V-CPCI is connected with the source electrode of the first metal-oxide-semiconductor [Q1], first electric capacity [C1], the second electric capacity
[C2] and the 3rd electric capacity [C3] are in parallel to be simultaneously arranged in the drain electrode of the first metal-oxide-semiconductor [Q1], the positive electrode of the 3rd electric capacity [C3] and
Signal+5VRUN is connected, negative electrode ground connection；
Power supply signal input+3.3V-CPCI is connected with the source electrode of the second metal-oxide-semiconductor [Q2], the 4th electric capacity [C4], the 5th electricity
Hold [C5] and the parallel connection of the 6th electric capacity [C6] and be arranged in the drain electrode of the second metal-oxide-semiconductor [Q2], the positive electrode of the 6th electric capacity [C6]
With signal+3.3VRUN connections, negative electrode ground connection；
Power supply signal input+1.8V-A is connected with the source electrode of the 3rd metal-oxide-semiconductor [Q3], the 7th electric capacity [C7], the 8th electric capacity
[C8] and the 9th electric capacity [C9] are in parallel to be simultaneously arranged in the drain electrode of the 3rd metal-oxide-semiconductor [Q3], the positive electrode of the 9th electric capacity [C9] and
Signal+1.8VRUN is connected, negative electrode ground connection.
4. a kind of being disappeared based on power supply sequential trembles the switching value output circuit of control according to claim 1, it is characterised in that institute
Stating switching value output circuit includes the FPGA circuitry, bus driving circuits and the solid-state relay circuit that are sequentially connected；FPGA electricity
Road provides the control signal of relay, and bus driving circuits strengthen the level driver ability of control signal, by the 3.3V electricity of FPGA
Ordinary mail number is converted to 5V level signals, and solid-state relay circuit provides switching value output signal, for the load of rear end provides control
Output.
5. a kind of being disappeared based on power supply sequential trembles the switching value output circuit of control according to claim 4, it is characterised in that institute
Stating FPGA circuitry includes fpga chip [U1], configuration chip [U4] and clock chip [U5], and the bus driving circuits include
General line system chip [U2] and the 8th resistance [R8], the solid-state relay circuit include solid-state relay chip [U3], the
Nine resistance [R9], diode [V1] and fuse [F1]；
Power supply signal input+3.3VRUN by the 8th resistance [R8] respectively with the GPIOn pins of fpga chip [U1] and total
The pin EN of the pin IN1 connections of line conversion chip [U2], power supply signal input+1.8VRUN and general line system chip [U2]
Connection, the pin OUT1 of general line system chip [U2] is connected with the pin 3 [V-] of solid-state relay chip [U3], solid-state relay
The pin 1 [V0+] and pin 4 [V0-] of chip [U3] are hanging, and the pin 2 [V-] of solid-state relay chip [U3] is by the 9th electricity
Resistance [R9] is connected with power supply input signal+5VRUN；
The pin 5 [K1+] of the solid-state relay chip [U3] is connected with pin 8 [K2+], pin 7 [K2-] respectively with pin 6
[K1-], the positive pole of diode [V1] and digital switch quantity output signal anode OUTn+ are connected, the diode [V1] it is negative
Pole and pin 8 [K2+] are connected, and are connected by fuse [F1] and digital switch quantity output signal negative terminal OUTn-.
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| CN201611050607.6A CN106773905B (en) | 2016-11-24 | 2016-11-24 | A kind of disappeared based on power supply timing trembles the switching value output circuit of control |
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| CN114237092A (en) * | 2021-11-18 | 2022-03-25 | 北京卫星制造厂有限公司 | Level signal type on-off control circuit |
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| CN106773905B (en) | 2019-02-05 |
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