CN106773905B - A kind of disappeared based on power supply timing trembles the switching value output circuit of control - Google Patents
A kind of disappeared based on power supply timing trembles the switching value output circuit of control Download PDFInfo
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- CN106773905B CN106773905B CN201611050607.6A CN201611050607A CN106773905B CN 106773905 B CN106773905 B CN 106773905B CN 201611050607 A CN201611050607 A CN 201611050607A CN 106773905 B CN106773905 B CN 106773905B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
Abstract
The invention discloses a kind of to be disappeared based on power supply timing and trembles the switching value output circuit of control, including power supply timing interconnected disappears and trembles control circuit and switching value output circuit；The power supply timing twitter circuit that disappears includes power supply circuit and sequential control circuit, power supply circuit provides the control signal of power supply input signal and sequential control circuit, sequential control circuit handles power supply input signal, and the power supply signal of optimization is exported to switching value output circuit.Therefore, the present invention utilizes the high-speed switch and voltage stabilization characteristic of metal-oxide-semiconductor, it designs a kind of power supply timing and disappears and tremble control circuit, improve the input timing relationship and driving capability of power supply signal, optimize power supply signal quality, the control signal of the sequential control circuit is provided by power supply circuit itself, and multiple power sources input signal is carried out serial process, ensure that whole power output signals is managed by unified signal, it is ensured that the consistency of power supply signal timing.
Description
Technical field
The invention belongs to Digital Circuit Control field, especially a kind of disappeared based on power supply timing trembles the output switch parameter of control
Circuit.
Background technique
Output switch parameter is the analog signal of sensor sensing or digital controlled signal to be converted to on-off model, and mention
The switch for being provided as load circuit uses.Under normal conditions, switching value is realized using electromagnetism or solid-state relay.Switching value exists
It disconnects and closure two states, the usage mode of switching value output signal guarantees that switch is in a kind of steady state, that is, keep disconnected
It opens or closed state, is output loading circuit stability.
Due to control circuit design problem, traditional numerical control switch amount output signal may generate of short duration in closure
Switch from fluttering phenomenon.I.e. before on-off model is stable closed state, switch occurs primary or more in a very short period of time
Secondary intersection on-off.In most cases, for the not high control system of response time requirement or control the lower system of precision,
Influence of the switching value shake to system is smaller.But for the precision equipment in high-precision control system or system, it is required that
It controls precision and the response time is very high, it will usually be accurate to " microsecond " grade.Fault diagnosis is commonly provided in High Definition Systems to set
It is standby, if there are jitter phenomenons for switching value, it will failure diagnosis apparatus is caused to alarm.If not having fault diagnosis in system to set
Standby, then the intersection on-off of switching value will cause the unstable of load circuit, under extreme case, may cause the toning or vibration of system
It swings.
Summary of the invention
The present invention is provided a kind of disappeared based on power supply timing and trembles the switching value output circuit of control, power supply sequencing control circuit
Have the advantages that simple design, Parameter adjustable, high control precision, suitable for the complex control system of high-precision requirement, switch
The accurate control of output signal is measured, effectively realizes the smoothing processing of the on-off of on-off model, meanwhile, power supply timing of the invention
Control circuit can be widely applied for other numerical control system fields.
The technical solution for realizing the aim of the invention is as follows: a kind of disappeared based on power supply timing trembles the output switch parameter electricity of control
Road, including power supply timing interconnected disappear and tremble control circuit and switching value output circuit；The power supply timing disappears twitter circuit
Including power supply circuit and sequential control circuit, the power supply circuit provides the control of power supply input signal and sequential control circuit
Signal processed, sequential control circuit handle power supply input signal, the power supply signal of optimization are exported to switching value output circuit.
As a further improvement, the power supply circuit include signal output end, first resistor, second resistance, 3rd resistor,
4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the first triode, the second triode, third transistor；
The connection of one end of power supply signal input+1.8V-A and first resistor, the other end of first resistor is respectively with the 4th
The connection of the ground level of one end of resistance and third transistor, the other end of the 4th resistance respectively with one end of the 5th resistance, the 6th
One end of resistance and the emitter of third transistor are connected, and the emitter of the third transistor is grounded simultaneously；Power supply signal
One end of input terminal+5V-CPCI and second resistance connection, the other end of second resistance respectively with the other end of the 5th resistance and
The ground level of second triode connects；The connection of one end of power supply signal input+3.3V-CPCI and 3rd resistor, 3rd resistor
The other end is connect with the base stage of the other end of the 6th resistance and the first triode respectively；Power supply signal input+5V-CPCI with
One end of 7th resistance connects, and the other end of the 7th resistance is connect respectively with the collector of the first triode and signal output end
Connection, the emitter of the first triode are connect with the collector of the second triode, the emitter of the second triode and the three or three pole
The collector of pipe connects.
As a further improvement, the sequential control circuit includes signal input part, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor,
Three metal-oxide-semiconductors, first capacitor, the second capacitor, third capacitor, the 4th capacitor, the 5th capacitor, the 6th capacitor, the 7th capacitor, the 8th electricity
Appearance and the 9th capacitor；
Signal input part connects with the grid of the grid of the first metal-oxide-semiconductor, the grid of the second metal-oxide-semiconductor and third metal-oxide-semiconductor respectively
It connects；
Power supply signal input+5V-CPCI is connect with the source electrode of the first metal-oxide-semiconductor, the first capacitor, the second capacitor and
Third capacitor is in parallel and is arranged in the drain electrode of the first metal-oxide-semiconductor, and the positive electrode of third capacitor is connected with signal+5VRUN, negative electrode
Ground connection；
Power supply signal input+3.3V-CPCI is connect with the source electrode of the second metal-oxide-semiconductor, the 4th capacitor, the 5th capacitor with
And the 6th capacitor it is in parallel and be arranged in the drain electrode of the second metal-oxide-semiconductor, the positive electrode of the 6th capacitor connect with signal+3.3VRUN, negative
Electrode ground connection；
Power supply signal input+1.8V-A is connect with the source electrode of third metal-oxide-semiconductor, the 7th capacitor, the 8th capacitor and
9th capacitor is in parallel and is arranged in the drain electrode of third metal-oxide-semiconductor, and the positive electrode of the 9th capacitor is connected with signal+1.8VRUN, negative electricity
Pole ground connection.
As a further improvement, the switching value output circuit includes sequentially connected FPGA circuitry, bus driving circuits
And solid-state relay circuit；FPGA circuitry provides the control signal of relay, the electricity of bus driving circuits enhancing control signal
The 3.3V level signal of FPGA is converted to 5V level signal by flat driving capability, and solid-state relay circuit provides output switch parameter
Signal provides control output for the load of rear end.
As a further improvement, the FPGA circuitry includes fpga chip, configuration chip and clock chip, the bus
Driving circuit includes general line system chip and the 8th resistance, and the solid-state relay circuit includes solid-state relay chip,
Nine resistance, diode and fuse；
Power supply signal input+3.3VRUN is turned with the GPIOn pin and bus of fpga chip respectively by the 8th resistance
The pin IN1 connection of chip is changed, power supply signal input+1.8VRUN is connect with the pin EN of general line system chip, general line system
The pin OUT1 of chip is connect with the pin 3 of solid-state relay chip, and the pin 1 and pin 4 of solid-state relay chip are hanging, Gu
The pin 2 of body relay chip is connect by the 9th resistance with power supply input signal+5VRUN；
The pin 5 of the solid-state relay chip is connect with pin 8, pin 7 respectively with pin 6, diode anode with
And digital switch quantity output signal anode OUTn+ connection, cathode and pin 8 connection of the diode, and by fuse and
Digital switch quantity output signal negative terminal OUTn- connection.
Compared with prior art, the present invention its remarkable advantage are as follows: 1) compare existing power supply timing control technology, the present invention
It is designed using simplifying, power supply timing control parameter configuration is more flexible, has for specific control circuit design scheme stronger
Specific aim, be with a wide range of applications.2) existing switching value output circuit is compared, power supply sequencing control circuit effectively disappears
Except switching value because switch state caused by the minimum power supply time difference is shaken, the levels of precision of output switch parameter control is improved.3) effectively
Avoid FPGA during initialization, I/O signal level variation switch amount controls the influence of signal.So that output switch parameter
Signal smoothing improves the service life and functional reliability of relay.
Present invention is further described in detail with reference to the accompanying drawing.
Detailed description of the invention
Fig. 1 is the switching value output circuit functional block diagram of power supply timing control of the invention.
Fig. 2 is power supply circuit of the invention.
Fig. 3 is sequential control circuit figure of the invention.
Fig. 4 is output switch parameter application circuit of the invention.
Fig. 5 is schematic diagram inside solid-state relay of the invention.
Specific embodiment
In the digital circuit of cpci bus framework, power supply circuit by cpci bus power supply signal and power conversion module
It provides, the power supply signal of different voltages amplitude is needed in same functional module, the power supply timing of various power supply signals exists successive
Sequential relationship, will lead to backend application circuit operation irregularity, reduce the stability and reliability of application circuit, can be led when serious
The hyperharmonic of cause system is vibrated.
Application circuit in the present invention is answered based on the switching value output circuit of extensive programmable controller FPGA control
Electricity consumption routes FPGA circuitry, bus driving circuits, solid-state relay circuit and constitutes.Requirement of the application circuit to power supply timing compared with
Height, if there are time sequence difference relationships for power supply signal, will lead to FPGA control signal can not be dynamic with the switch of solid-state relay
Make simultaneously match, cause solid-state relay that can generate frequent switch motion, i.e., is switched during application circuit initializes
Amount output generates jitter phenomenon.The circuit is strictly controlled the generation timing sequence of power supply, and then ensures that digital output modul is believed
The consistency of number state, the mode are suitable for high-precision control system field.
In conjunction with Fig. 1 to Fig. 4, a kind of disappeared based on power supply timing of the invention trembles the switching value output circuit of control, including mutual
The power supply timing of connection, which disappears, trembles control circuit and switching value output circuit；Power supply timing disappear twitter circuit include power supply circuit and
Sequential control circuit, power supply circuit provide the control signal of power supply input signal and sequential control circuit, sequential control circuit
Power supply input signal is handled, the power supply signal of optimization is exported to switching value output circuit.
Power supply circuit include signal output end a, first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4,
5th resistance R5, the 6th resistance R6, the 7th resistance R7, the first triode D1, the second triode D2, third transistor D3；
Power supply signal input+1.8V-A is connect with one end of first resistor R1, the other end of first resistor R1 respectively with
The connection of the ground level of one end of 4th resistance R4 and third transistor D3, the other end of the 4th resistance R4 respectively with the 5th resistance R5
One end, the 6th resistance R6 one end and third transistor D3 emitter be connected, the emitter of the third transistor D3
It is grounded simultaneously；Power supply signal input+5V-CPCI is connect with one end of second resistance R2, the other end difference of second resistance R2
It is connect with the ground level of the other end of the 5th resistance R5 and the second triode D2；Power supply signal input+3.3V-CPCI and third
One end of resistance R3 connects, the other end of 3rd resistor R3 respectively with the other end of the 6th resistance R6 and the first triode D1
Base stage connection；Power supply signal input+5V-CPCI is connect with one end of the 7th resistance R7, the other end difference of the 7th resistance R7
It is connect with the collector of the first triode D1 and signal output end a connection, the emitter of the first triode D1 and the two or three pole
The collector of pipe D2 connects, and the emitter of the second triode D2 is connect with the collector of third transistor D3.
Sequential control circuit includes signal input part b, the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, third metal-oxide-semiconductor Q3, first
Capacitor C1, the second capacitor C2, third capacitor C3, the 4th capacitor C4, the 5th capacitor C5, the 6th capacitor C6, the 7th capacitor C7, the 8th
Capacitor C8 and the 9th capacitor C9；
Signal input part b respectively with the grid of the first metal-oxide-semiconductor Q1, the grid of the second metal-oxide-semiconductor Q2 and third metal-oxide-semiconductor Q3
Grid connection；
Power supply signal input+5V-CPCI is connect with the source electrode of the first metal-oxide-semiconductor Q1, the first capacitor C1, the second capacitor
C2 and third capacitor C3 is in parallel to be simultaneously arranged in the drain electrode of the first metal-oxide-semiconductor Q1, and the positive electrode and signal of third capacitor C3+
5VRUN connection, negative electrode ground connection；
Power supply signal input+3.3V-CPCI is connect with the source electrode of the second metal-oxide-semiconductor Q2, the 4th capacitor C4, the 5th capacitor C5
And the 6th capacitor C6 it is in parallel and be arranged in the drain electrode of the second metal-oxide-semiconductor Q2, the positive electrode and signal of the 6th capacitor C6+
3.3VRUN connection, negative electrode ground connection；
Power supply signal input+1.8V-A is connect with the source electrode of third metal-oxide-semiconductor Q3, the 7th capacitor C7, the 8th capacitor C8 with
And the 9th capacitor C9 it is in parallel and be arranged in the drain electrode of third metal-oxide-semiconductor Q3, the positive electrode and signal+1.8VRUN of the 9th capacitor C9
Connection, negative electrode ground connection.
Switching value output circuit includes sequentially connected FPGA circuitry, bus driving circuits and solid-state relay circuit；
FPGA circuitry provides the control signal of relay, the level driving capability of bus driving circuits enhancing control signal, by FPGA's
3.3V level signal is converted to 5V level signal, and solid-state relay circuit provides switching value output signal, mentions for the load of rear end
It is exported for control.
FPGA circuitry includes that fpga chip U1, configuration chip U4 and clock chip U5, the bus driving circuits include
General line system chip U2 and the 8th resistance R8, the solid-state relay circuit include solid-state relay chip U3, the 9th resistance
R9, diode V1 and fuse F1；
Power supply signal input+3.3VRUN by the 8th resistance R8 respectively with the GPIOn pin of fpga chip U1 and total
The pin IN1 connection of line conversion chip U2, power supply signal input+1.8VRUN are connect with the pin EN of general line system chip U2,
The pin OUT1 of general line system chip U2 is connect with the pin 3 [V-] of solid-state relay chip U3, solid-state relay chip U3's
Vacantly, the pin 2 [V-] of solid-state relay chip U3 is defeated by the 9th resistance R9 and power supply for pin 1 [V0+] and pin 4 [V0-]
Enter signal+5VRUN connection；
The pin 5 [K1+] of solid-state relay chip U3 is connect with pin 8 [K2+], pin 7 [K2-] respectively with pin 6
[K1-], the anode of diode V1 and digital switch quantity output signal anode OUTn+ connection, the cathode and pin 8 of diode V1
[K2+] connection, and connected by fuse F1 with digital switch quantity output signal negative terminal OUTn-.
Further detailed description is done to the present invention below with reference to embodiment:
Embodiment
In conjunction with Fig. 2, the power supply circuit includes three kinds of power supply signals used in circuit, including 5V-CPCI power supply letter
Number, 3.3V-CPCI power supply signal, 1.8V-A power supply signal, the circuit and sequential control circuit and output switch parameter application circuit
Connection.First resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th electricity in the circuit
It hinders R6 and three kinds of power supply signals of input is subjected to partial pressure appropriate, meet the emitter junction forward conduction of triode.In the circuit
First triode D1, the second triode D2, third transistor D3 are connected in series, and three kinds of power supply signals are used as control signal,
It is input to the base stage and transmitting interpolar of D1, D2, D3.A signaling point provides control letter for sequential control circuit in the power supply circuit
Number.When for loading power signal, a signaling point is high-impedance state.After+5V-CPCI power supply signal generates, corresponding first triode
D1 is opened, and the collector and emitter of the triode form conductive channel.At this point, a signaling point is pulled to 5V in the circuit.
If after three kinds of power supply signals generate, the collector and emitter of corresponding triode D1, D2, D3 are respectively formed conductive channel, make
It obtains a signaling point and is pulled down to GND.After the design method guarantees that three kinds of power supply signals generate, the state of the control signal a of output
Low level is become from high level.If there are a kind of power supply lag in three kinds of power supply signals, a signaling point is maintained as high level.
In conjunction with Fig. 3, the sequential control circuit, the timing that control signal and metal-oxide-semiconductor including power supply circuit output are constituted
Control circuit, including the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, third metal-oxide-semiconductor Q3.The power supply circuit is by triode by three kinds
Power supply merges into single control signal, controls the opening and closing of metal-oxide-semiconductor channel, with timing in three kinds of power supplys relatively after a kind of electricity
Source signal guarantees that metal-oxide-semiconductor is opened in the same time, unified power supply is provided for output switch parameter application circuit as clock reference
Power supply signal.The first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, third metal-oxide-semiconductor Q3 select P-channel metal-oxide-semiconductor.Three kinds of metal-oxide-semiconductors
Working principle is consistent.By taking the first metal-oxide-semiconductor Q1 as an example, a signaling point is connect with b signaling point.When control signal b is high level (5V), P
The grid voltage of the first metal-oxide-semiconductor of channel Q1 and source voltage are 5V, then the metal-oxide-semiconductor can not be connected, at this time the second metal-oxide-semiconductor Q2 and
Third metal-oxide-semiconductor Q3 can not also be connected.If after three kinds of power supply signals generate, control signal b is low level (GND), the first metal-oxide-semiconductor
The UGS of Q1 is -5V, meets the cut-in voltage UT of the metal-oxide-semiconductor, so that the drain D of metal-oxide-semiconductor and source S form conducting channel,
Access is formed between drain electrode and source electrode.At this point ,+5V-CPCI signal is converted to+5VRUN signal by metal-oxide-semiconductor, the second metal-oxide-semiconductor at this time
Q2 and third metal-oxide-semiconductor Q3 can normally.The turn-on time of the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, third metal-oxide-semiconductor Q3
It is almost the same.Therefore, the system of three kinds of power supply signal timing is generated while power supply signal+5VRUN ,+3.3VRUN ,+1.8VRUN
One.First capacitor C1 in the sequential control circuit, the second capacitor C2, third capacitor C3, the 4th capacitor C4, the 5th capacitor C5,
6th capacitor C6, the 7th capacitor C7, the 8th capacitor C8, the 9th capacitor C9 select different capacitances, believe three kinds of power inputs
It number is filtered and decouples, the ripple and noise of power supply signal is effectively reduced.
In conjunction with Fig. 4, Fig. 5, the output switch parameter application circuit includes FPGA circuitry, bus switching circuit, solid relay
Device circuit.The wherein control signal of FPGA circuitry output relay, the control signal that bus switching circuit exports FPGA are converted
For the level nature controlled suitable for relay, solid-state relay circuit realizes the on-off of switching value output signal, for the present invention
In typical application circuit.FPGA circuitry includes fpga chip U1, configuration chip U4, clock chip U5 in the circuit.FPGA
Chip U1 selects programmable logic device EP2C35F672I8N, the control signal of I/O pin GPIOn output relay.Configuration
Chip U4 selects EPCS16N, configures the EEPROM information of FPGA, and clock chip U5 selects NB3L553 clock distributor, is FPGA
The work clock of 33MHZ is provided.General line system chip U2 is converted to IN1 (3.3V level) the control signal of FPGA output
OUT1 (5V level), it is ensured that switching value output circuit works normally.The EN signal of general line system chip dependence+1.8VRUN carries out
Work is enabled.Solid-state relay circuit U 3 selects JGW-3M light MOS solid-state relay, and 2 foot of chip is pulled up by the 9th resistance R9
The control signal of relay is constituted to+5VRUN and 3 foot of chip.If the control signal JKSn of 3 feet of relay is high level
(5V), output switch parameter are off-state.In conjunction with Fig. 5, if the control signal JKSn of 3 feet of relay is low level, control terminal
Input voltage be 5V, input turn-on current is greater than 5mA, and the Light-Emitting Diode V2 of relay control terminal is connected, so that controlled
Two Opposite direction connection N-channel MOS pipe conductings.Work as LEDs ON, the U of N-channel type metal-oxide-semiconductorGSElectricity is opened greater than metal-oxide-semiconductor
Press UT, so that the drain D of metal-oxide-semiconductor and source S form conducting channel, access is formed between drain electrode and source electrode.Output switch parameter
For channel status.The output signal GPIOn of FPGA circuitry is pulled to+3.3VRUN by the 8th resistance R8, passes through general line system core
Piece guarantees that 3 foot JKSn level default conditions of relay are 5V, and relay is off state.Only when FPGA issues low level control
Signal processed, relay are changed on state, i.e. switching value output signal is on state.
If sequence control circuit when not in use, three kinds of power supply signals in timing in the output switch parameter application circuit
It is inconsistent.Assuming that 3.3V power supply signal lags behind 5V power supply signal and 1.8V power supply signal, and when FPGA initialization, fpga chip
GPIOn default configuration be low level, due to the 3.3V level of pull-up be not ready to it is ready, after electrical level transferring chip, input
3 foot JKSn of control signal to relay is low level, and switching value output signal is on state at this time.And when 3.3V power supply is believed
Number generate after, output switch parameter restore off-state.Since power supply timing is not unified, the initial phase of the application circuit will be led
Switching value output signal is caused to generate jitter phenomenon.Assuming that 1.8V power supply signal lags behind 5V power supply signal and 3.3V power supply signal.
Then the enable signal EN of bus switching circuit is not ready to ready in the output switch parameter application circuit, leads to bus switching circuit
Default output OUT1 be low level, again such that switching value output signal generates of short duration on state, i.e. generation switching value
Jitter phenomenon.Switching value shake will lead to system detection fault alarm, and the oscillation in control system circuit can be caused under serious conditions.
Increase sequential control circuit, three kinds of power supply signals is basic in timing in the output switch parameter application circuit
It is consistent.In application circuit initial phase, it is ensured that the control terminal voltage of relay is 0V, and On-off signal signal stabilization is
Off-state.Only when FPGA generates control signal, solid-state relay is acted accordingly.
Compared to existing power supply timing control technology, the present invention is using design is simplified, and power supply timing control parameter configuration is more
Add flexibly, there is stronger specific aim for specific control circuit design scheme, be with a wide range of applications.
Claims (4)
1. a kind of disappeared based on power supply timing trembles the switching value output circuit of control, which is characterized in that including power supply interconnected
Timing, which disappears, trembles control circuit and switching value output circuit；The power supply timing disappears, and to tremble control circuit include power supply circuit with timely
Sequence control circuit, the power supply circuit provide the control signal of power supply input signal and sequential control circuit, timing control electricity
Road handles power supply input signal, and the power supply signal of optimization is exported to switching value output circuit；
The power supply circuit includes signal output end a, first resistor [R1], second resistance [R2], 3rd resistor [R3], the 4th electricity
Hinder [R4], the 5th resistance [R5], the 6th resistance [R6], the 7th resistance [R7], the first triode [D1], the second triode [D2],
Third transistor [D3]；
Power supply signal input+1.8V-A is connect with the one end of first resistor [R1], the other end of first resistor [R1] respectively with
The connection of the ground level of one end of 4th resistance [R4] and third transistor [D3], the other end of the 4th resistance [R4] is respectively with the 5th
The emitter of one end of resistance [R5], one end of the 6th resistance [R6] and third transistor [D3] is connected, the three or three pole
The emitter of pipe [D3] is grounded simultaneously；Power supply signal input+5V-CPCI is connect with the one end of second resistance [R2], the second electricity
The other end of resistance [R2] is connect with the ground level of the other end of the 5th resistance [R5] and the second triode [D2] respectively；Power supply signal
Input terminal+3.3V-CPCI is connect with the one end of 3rd resistor [R3], the other end of 3rd resistor [R3] respectively with the 6th resistance
The connection of the base stage of the other end of [R6] and the first triode [D1]；Power supply signal input+5V-CPCI and the 7th resistance [R7]
One end connection, the other end of the 7th resistance [R7] is connect respectively with the collector of the first triode [D1] and signal output end
The emitter of a connection, the first triode [D1] is connect with the collector of the second triode [D2], the transmitting of the second triode [D2]
Pole is connect with the collector of third transistor [D3].
2. a kind of disappeared based on power supply timing trembles the switching value output circuit of control according to claim 1, which is characterized in that institute
Stating sequential control circuit includes signal input part b, the first metal-oxide-semiconductor [Q1], the second metal-oxide-semiconductor [Q2], third metal-oxide-semiconductor [Q3], first
Capacitor [C1], the second capacitor [C2], third capacitor [C3], the 4th capacitor [C4], the 5th capacitor [C5], the 6th capacitor [C6],
Seven capacitors [C7], the 8th capacitor [C8] and the 9th capacitor [C9]；
Signal input part b respectively with the grid of the first metal-oxide-semiconductor [Q1], the grid of the second metal-oxide-semiconductor [Q2] and third metal-oxide-semiconductor [Q3]
Grid connection；
Power supply signal input+5V-CPCI is connect with the source electrode of the first metal-oxide-semiconductor [Q1], the first capacitor [C1], the second capacitor
[C2] and third capacitor [C3] are in parallel to be simultaneously arranged in the drain electrode of the first metal-oxide-semiconductor [Q1], the positive electrode of third capacitor [C3] and
Signal+5VRUN connection, negative electrode ground connection；
Power supply signal input+3.3V-CPCI is connect with the source electrode of the second metal-oxide-semiconductor [Q2], the 4th capacitor [C4], the 5th electricity
Hold [C5] and the 6th capacitor [C6] is in parallel and setting is in the drain electrode of the second metal-oxide-semiconductor [Q2], the positive electrode of the 6th capacitor [C6]
It is connected with signal+3.3VRUN, negative electrode ground connection；
Power supply signal input+1.8V-A is connect with the source electrode of third metal-oxide-semiconductor [Q3], the 7th capacitor [C7], the 8th capacitor
[C8] and the 9th capacitor [C9] are in parallel to be simultaneously arranged in the drain electrode of third metal-oxide-semiconductor [Q3], the positive electrode of the 9th capacitor [C9] and
Signal+1.8VRUN connection, negative electrode ground connection.
3. a kind of disappeared based on power supply timing trembles the switching value output circuit of control according to claim 1, which is characterized in that institute
Stating switching value output circuit includes sequentially connected FPGA circuitry, bus driving circuits and solid-state relay circuit；FPGA electricity
Road provides the control signal of relay, the level driving capability of bus driving circuits enhancing control signal, by the 3.3V electricity of FPGA
Ordinary mail number is converted to 5V level signal, and solid-state relay circuit provides switching value output signal, provides control for the load of rear end
Output.
4. a kind of disappeared based on power supply timing trembles the switching value output circuit of control according to claim 3, which is characterized in that institute
Stating FPGA circuitry includes that fpga chip [U1], configuration chip [U4] and clock chip [U5], the bus driving circuits include
General line system chip [U2] and the 8th resistance [R8], the solid-state relay circuit include solid-state relay chip [U3],
Nine resistance [R9], diode [V1] and fuse [F1]；
Power supply signal input+3.3VRUN by the 8th resistance [R8] respectively with the GPIOn pin of fpga chip [U1] and total
The pin IN1 connection of line conversion chip [U2], the pin EN of power supply signal input+1.8VRUN and general line system chip [U2]
Connection, the pin OUT1 of general line system chip [U2] are connect with the pin 3 [V-] of solid-state relay chip [U3], solid-state relay
Vacantly, the pin 2 [V-] of solid-state relay chip [U3] passes through the 9th electricity to the pin 1 [V0+] and pin 4 [V0-] of chip [U3]
Resistance [R9] is connect with power supply input signal+5VRUN；
The model JGW-3M light MOS of the solid-state relay chip [U3], pin 5 [K1+] connect with pin 8 [K2+], draw
Foot 7 [K2-] is connect with pin 6 [K1-], the anode of diode [V1] and digital switch quantity output signal anode OUTn+ respectively,
The cathode and pin 8 [K2+] of the diode [V1] connect, and pass through fuse [F1] and digital switch quantity output signal negative terminal
OUTn- connection.
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| CN201611050607.6A CN106773905B (en) | 2016-11-24 | 2016-11-24 | A kind of disappeared based on power supply timing trembles the switching value output circuit of control |
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| CN201611050607.6A CN106773905B (en) | 2016-11-24 | 2016-11-24 | A kind of disappeared based on power supply timing trembles the switching value output circuit of control |
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| Publication Number | Publication Date |
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| CN106773905A CN106773905A (en) | 2017-05-31 |
| CN106773905B true CN106773905B (en) | 2019-02-05 |
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| CN114237092A (en) * | 2021-11-18 | 2022-03-25 | 北京卫星制造厂有限公司 | Level signal type on-off control circuit |
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| CN106773905A (en) | 2017-05-31 |
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Address after: 222000 18 Shenghu Road, Lianyungang City, Jiangsu Province Patentee after: The 716th Research Institute of China Shipbuilding Corporation Address before: 222000 18 Shenghu Road, Lianyungang City, Jiangsu Province Patentee before: 716TH RESEARCH INSTITUTE OF CHINA SHIPBUILDING INDUSTRY Corp. |