CN2655309Y - Power supply time sequence controlling circuit - Google Patents
Power supply time sequence controlling circuit Download PDFInfo
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- CN2655309Y CN2655309Y CN 03276899 CN03276899U CN2655309Y CN 2655309 Y CN2655309 Y CN 2655309Y CN 03276899 CN03276899 CN 03276899 CN 03276899 U CN03276899 U CN 03276899U CN 2655309 Y CN2655309 Y CN 2655309Y
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Abstract
The utility model provides an upper electric time series controlling circuit, comprising one or above one controlled switch circuit with a controlling end, wherein the input end of the controlled switch circuit is connected with the input power, the output end of each controlled switch circuit is connected with a circuit which needs power supply, the utility model also comprises a time series controlling chip with plural routs output ends, wherein the power input end of the time series controlling chip is connected with the input power, the output end in each rout of the time series controlling chip is connected with each controlling end of the controlled switch circuit, the utility model also comprises a power accident detecting circuit, wherein each input end is respectively connected with the output end of each controlled switch circuit, one or a plurality of output end of the power accident detecting circuit are connected with corresponding one or a plurality of controlling end of the time series controlling chip. The utility model makes the upper electric time series controlling circuit simpler and the electric time series adjustment in each rout more convenient.
Description
Technical field
The utility model relates to the field of intelligent control technology of power supply, is meant a kind of electrifying timing sequence control circuit especially.
Background technology
Power supply is the power resources of electronic product, and the electrifying startup process of electronic product is the higher stage of power-fail rate, and the q﹠r of electronic product is had considerable influence.In telecommunication system, the electronic chip that equipment veneer adopted becomes increasingly complex, and veneer also becomes increasingly complex to the demand of supply voltage.In the electrifying startup process, for the equipment that a plurality of power supply inputs are arranged, require each input power supply that strict electrifying timing sequence is arranged, if electrifying timing sequence is improper, not only can influence the reliability of veneer device and total system, even can cause device bolt-lock and veneer permanent damage on the veneer.
Fig. 1 is the schematic diagram of electrifying timing sequence control circuit.Each road input power supply Vin_1 is to the Vin_N switching device of contacting separately, as metal-oxide-semiconductor; The electrifying timing sequence control chip group provides N road control signal, and N the metal-oxide-semiconductor of Enable Pin control that is input to metal-oxide-semiconductor separately is closed successively according to certain sequential, and realization N road power supply is exported successively according to certain sequential.
At present, the electrifying timing sequence control chip group generally is made up of the electron device of a plurality of delay functions.As Fig. 1, for forming the electrifying timing sequence control chip group by N LT1422 chip.When device power, the Vin electric signal is sent to the ON port of N sheet LT1422 chip, starts N sheet LT1422 chip, and the LT1422 basis is the difference of the TIMER capacitance parameter that port connects of chip separately, control the asynchronism(-nization) that its GATE end sends control signal, thus the sequential control that realization powers on.As two capacitor C that LT1422 connect 5, C6 given among the figure.
At present, form the functional unit negligible amounts that each chip of the control chip group that powers on can be controlled, as, a LT1422 chip only supports 1 road GATE to export.If need the sequential of a plurality of circuit powers of control to power on, then need to use a plurality of chips, not only cost is higher, and hardware circuit implementation is comparatively complicated.In addition, if the time sequence parameter adjustment that powers on, the necessary capacitance-resistance parameter of adjusting corresponding chip exterior, as above routine described capacitor C 5, C6 need change hardware, and be flexibly inconvenient.
The utility model content
In view of this, the utility model provides a kind of electrifying timing sequence control circuit.Make the electrifying timing sequence control circuit more succinct, time sequence parameter is adjusted more convenient.
This electrifying timing sequence control circuit, comprise one or more contain control end by controlled switch circuit, this is linked to each other with the input power supply by the input end of controlled switch circuit, each is linked to each other by the circuit of the output terminal of controlled switch circuit with a needs power supply, also comprise: the timing controller of a multi-channel output, the power input of timing controller links to each other with the input power supply, and each road output terminal of timing controller links to each other with each the control end by controlled switch circuit.
Wherein, described timing controller can be PLD, CPLD or FPGA.
Wherein, this circuit is described to be can be the power source conversion device that contains Enable Pin by controlled switch circuit, and its input end links to each other with the input power supply, and output terminal links to each other with the circuit of a needs power supply, and Enable Pin links to each other with an output terminal of timing controller.
Wherein, the described switching device that contains Enable Pin that be can be the power source conversion device and contact with it by controlled switch circuit of this circuit, the input end of power source conversion device links to each other with the input power supply, the output terminal of switching device links to each other with the circuit of a needs power supply, and the Enable Pin of switching device links to each other with an output terminal of timing controller.
Wherein, described timing controller comprises a control end, then described circuit further comprises: the power failure detection circuit of many input ends list output terminal, its each input end links to each other with each output terminal by controlled switch circuit respectively, and the output terminal of this power failure detection circuit links to each other with the control end of timing controller.Wherein, described power failure detection circuit comprises: with by the same number of triode of controlled switch circuit and a combiner spare, the base stage of each triode with linked to each other by the output terminal of controlled switch circuit, the collector of each triode be connected to a combiner spare after reference voltage is in parallel, combiner spare output terminal links to each other with the control end of timing controller.Described combiner spare is or gate device.
Wherein, described timing controller comprise with by the same number of control end of controlled switch circuit, described circuit further comprises: the power failure detection circuit of the many output terminals of many input ends, each input end of power failure detection circuit links to each other respectively with by the output terminal of controlled switch circuit, and each output terminal links to each other with each control end of timing controller respectively.Wherein, described power failure detection circuit comprises: with by the same number of triode of controlled switch circuit, the base stage of each triode be power failure detection circuit input end with linked to each other by the output terminal of controlled switch circuit, link to each other with each control end of timing controller respectively after the collector of each triode and the reference voltage parallel connection.
Wherein, described electrifying timing sequence control circuit further comprises: the buffer circuit that boosts of multi-channel input multi-channel output, each road input end links to each other with each road output terminal of timing controller respectively, and each the road output terminal of buffer circuit that boosts is linked to each other by the input end of controlled switch circuit with each road respectively.Wherein, the described buffer circuit that boosts comprises: with by the same number of triode of controlled switch circuit, the base stage of each triode links to each other with the timing controller output terminal, is linked to each other by the input end of controlled switch circuit with each road after the collector of each triode and the reference voltage parallel connection.
By said method as can be seen, the utility model adopts a slice timing controller to realize the control of multichannel electrifying timing sequence.According to the I/O number of pin of logical device, but programming in logic is controlled the sequential of a plurality of input circuits, does not need to use a plurality of special timing controllers.And that has saved original time-delay usefulness respectively organizes capacitance-resistance, makes circuit simpler, has reduced the cost of control circuit; Come electrifying timing sequence is controlled by programming in logic, the adjustment of electrifying timing sequence parameter only can realize by revising corresponding code, and need not change other devices of control circuit, and is flexible to operation.In addition, the output of the control signal by testing circuit control timing control chip can be controlled the output of power switching devices deenergization easily, uses the equipment of this power supply with protection.
Description of drawings
Fig. 1 is the schematic diagram that the electrifying timing sequence control chip group of utilizing the LT1422 chip to form is carried out the electrifying timing sequence control circuit.
Fig. 2 is the schematic diagram of the utility model electrifying timing sequence control circuit.
Fig. 3 is the buffer circuit that boosts.
Fig. 4 is a power failure detection circuit.
Embodiment
CPLD (CPLD) can require to carry out programming in logic in advance according to the sequential of each road power supply output, realizes that N the output port V1_K1 of CPLD exports control signal to V1_KN by required sequential requirement.With the power source conversion device and with it the switching device that contains Enable Pin of polyphone be to be example by controlled switch circuit, wherein the power source conversion device is d-c transformer DC/DC_N, switching device is a metal-oxide-semiconductor, and with CPLD as timing controller, N road power supply is carried out electrifying timing sequence be controlled to be example, the utility model is elaborated.
As shown in Figure 2, CPLD of the present utility model comprises also that except the power input mouth connection power supply Vin of necessity is connected the crystal oscillator with the crystal oscillator input port N road output port V1_K1 is to V1_KN and one road control port Vcon.Wherein, N road output port is used to export control signal, and control port Vcon receives the output signal of power failure detection circuit, is used to control CPLD chip output mouth and whether can exports control signal.
As shown in Figure 2, in the utility model electrifying timing sequence control circuit, the power input mouth that device power supply (DPS) Vin connects CPLD is a chip power supply, the output port V1_K1 of the N road signal of CPLD is to V1_KN, be connected to the input end of the buffer circuit that boosts of N road input, boost the N road output port V2_K1 of buffer circuit to V2_KN, connect the Enable Pin of the switching device metal-oxide-semiconductor of N road power supply.In addition, the utility model is parallel-connected to the input port that the power failure detection circuit of one tunnel output is imported on a N road with the output port Vout_1 of N road power supply to Vout_N, and the output of power failure detection circuit inserts the control port Vcon of CPLD.
After the device power, voltage is converted to the equipment input voltage vin through power module DC/DC_0, and each road power supply will be imported power supply Vin through power transfer module DC/DC_1 separately to DC/DC_N respectively and be converted to the power supply Vin_1 of each road use to Vin_N.This moment, each metal-oxide-semiconductor Enable Pin was not received control signal as yet, so each road power supply output is in high-impedance state.Simultaneously, input power supply Vin starts CPLD, CPLD basis programming in logic in advance, and N output port V1_0 is to V1_N order output control signal.As behind time-delay X1 millisecond, CPLD output port V1_K1 exports control signal; Behind the time-delay X2 millisecond, CPLD output port V1_K2 exports control signal; Delay time successively behind the XN millisecond, CPLD output port V1_KN exports control signal.After the end that powers on, detect each road power supply output Vout_1 by power failure detection circuit and whether fault is arranged to Vout_N, if have, then the signal of CPLD power source-responsive failure detector circuit input CPLD control port Vcon responds control output signal V2_K1 to V2_KN.
The output of each road of CPLD inserts the N road input port of the buffer circuit that boosts, and each road control signal V1_0 of CPLD is amplified to V1_N.Fig. 3 for the N road boost buffer circuit figure wherein a road, the circuit that adopts triode to form is isolated and level conversion control signal.As Fig. 3, CPLD output is in parallel with the series circuit that reference voltage V33 and resistance R 1 are formed, and the resistance R b that then contacts receives triode Q1 base stage; Promptly the boost output of buffer circuit of the collector of its Q1 links to each other with the Enable Pin of metal-oxide-semiconductor, the collector of Q1 reference voltage V_mos in parallel simultaneously, and wherein the current potential of this voltage is enough to enable the metal-oxide-semiconductor conducting; The emitter grounding of Q1.In the time of CPLD control signal output high resistant, when perhaps the CPLD control signal was exported high level, V33 made the collector and emitter conducting of Q1 for the Q1 base stage provides voltage, and the current collection of Q1 is low level very, so metal-oxide-semiconductor is in closed condition; When the control signal of CPLD output was negative level, collector and the emitter-base bandgap grading of Q1 became disconnection from conducting state, and collector voltage is reference voltage V_mos, therefore controlled the closed conducting of metal-oxide-semiconductor.
Power failure detection circuit among Fig. 2, each road power output end also connects the power failure detection circuit input end, and one tunnel output of power failure detection circuit is connected in series to the enable port of timing controller.After device power finished, power failure detection circuit judged whether each road has fault, and when certain road fault, power fail detect module is controlled the output of the control signal of CPLD, disconnects the metal-oxide-semiconductor of each road or partial circuit, with protection equipment.Fig. 4 is an alignment detection circuit wherein, and input end serial resistance R is connected to the base stage of Q1, when the detected power supply that inserts input end has electric current, makes the collector and emitter conducting of Q1, and the Q1 collector is that output terminal is a low level, represents that this road power work is normal; Otherwise when input end did not have electric current, the collector and emitter of Q1 ended, and Q1 output terminal output high level is represented this road electric power disconnection fault.Each road output terminal of N alignment detection circuit by a combiner spare carry out phase or after, become one tunnel output and be connected to the CPLD control port, as this example employing or gate device.Therefore when one tunnel fault, the signal of input CPLD control end is a high level, and at this moment, CPLD output port V1_0 is to the output of V1_N output high level signal or stop control signal, to disconnect all metal-oxide-semiconductors.In addition, power failure detection circuit also can not pass through combiner spare, and keep the output of N road, and the output of N road is linked to each other with the N road input port that CPLD is provided with in addition, this N road input port of CPLD is controlled the signal of the N road output port V1_0 of CPLD to V1_N output respectively.Like this, CPLD can be according to the signal of the power failure detection circuit on each road output, through programming in logic, the output signal V1_0 on each road is controlled respectively to V1_N, realizes the metal-oxide-semiconductor on a cut-off parts power path or the whole power path.
The utility model is opened by the order of CPLD driven MOS management and control system power supply, in addition, also can only be adopted the d-c transformer DC/DC_N that contains Enable Pin by controlled switch circuit, then CPLD also can control the unlatching that enables to bring in the control power supply of DC/DC_N, be that CPLD exports control signal in proper order, be input to the electrifying timing sequence that enables to bring in each road voltage of control of each power module DC/DC, and save MOS.Principle is identical, no longer describes in detail.In addition, timing function is not only realized by CPLD, also can be realized by programmable logic device (PLD) (PLD), field programmable logic device programmable logic device (PLD) such as (FPGA); The principle that realizes is identical with effect, no longer describes in detail.
The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; all within spirit of the present utility model and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within the protection domain of the present utility model.
Claims (11)
1, a kind of electrifying timing sequence control circuit, comprise one or more contain control end by controlled switch circuit, this is linked to each other with the input power supply by the input end of controlled switch circuit, each is linked to each other by the circuit of the output terminal of controlled switch circuit with a needs power supply, it is characterized in that described electrifying timing sequence control circuit further comprises:
The timing controller of a multi-channel output, the power input of timing controller links to each other with the input power supply, and each road output terminal of timing controller links to each other with each the control end by controlled switch circuit.
2, electrifying timing sequence control circuit according to claim 1 is characterized in that, described timing controller is PLD, CPLD or FPGA.
3, electrifying timing sequence control circuit according to claim 1, it is characterized in that, described is the power source conversion device that contains Enable Pin by controlled switch circuit, its input end links to each other with the input power supply, output terminal links to each other with the circuit of a needs power supply, and Enable Pin links to each other with an output terminal of timing controller.
4, electrifying timing sequence control circuit according to claim 1, it is characterized in that, described by controlled switch circuit be the power source conversion device and with it the polyphone the switching device that contains Enable Pin, the input end of power source conversion device links to each other with the input power supply, the output terminal of switching device links to each other with the circuit of a needs power supply, and the Enable Pin of switching device links to each other with an output terminal of timing controller.
5, electrifying timing sequence control circuit according to claim 1, it is characterized in that, described timing controller comprises a control end, described circuit further comprises: the power failure detection circuit of many input ends list output terminal, its each input end links to each other with each output terminal by controlled switch circuit respectively, and the output terminal of this power failure detection circuit links to each other with the control end of timing controller.
6, electrifying timing sequence control circuit according to claim 5, it is characterized in that, described power failure detection circuit comprises: with by the same number of triode of controlled switch circuit and a combiner spare, the base stage of each triode with linked to each other by the output terminal of controlled switch circuit, the collector of each triode be connected to a combiner spare after reference voltage is in parallel, combiner spare output terminal links to each other with the control end of timing controller.
7, electrifying timing sequence control circuit according to claim 6 is characterized in that, the combiner spare in the described power failure detection circuit is or gate device.
8, electrifying timing sequence control circuit according to claim 1, it is characterized in that, described timing controller comprise with by the same number of control end of controlled switch circuit, described circuit further comprises: the power failure detection circuit of the many output terminals of many input ends, each input end of power failure detection circuit links to each other respectively with by the output terminal of controlled switch circuit, and each output terminal links to each other with each control end of timing controller respectively.
9, electrifying timing sequence control circuit according to claim 8, it is characterized in that, described power failure detection circuit comprises: with by the same number of triode of controlled switch circuit, the base stage of each triode be power failure detection circuit input end with linked to each other by the output terminal of controlled switch circuit, link to each other with each control end of timing controller respectively after the collector of each triode and the reference voltage parallel connection.
10, electrifying timing sequence control circuit according to claim 1, it is characterized in that, described electrifying timing sequence control circuit further comprises: the buffer circuit that boosts of multi-channel input multi-channel output, each road input end links to each other with each road output terminal of timing controller respectively, and each the road output terminal of buffer circuit that boosts is linked to each other by the input end of controlled switch circuit with each road respectively.
11, electrifying timing sequence control circuit according to claim 10, it is characterized in that, the described buffer circuit that boosts comprises: with by the same number of triode of controlled switch circuit, the base stage of each triode links to each other with the timing controller output terminal, is linked to each other by the input end of controlled switch circuit with each road after the collector of each triode and the reference voltage parallel connection.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03276899 CN2655309Y (en) | 2003-07-16 | 2003-07-16 | Power supply time sequence controlling circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03276899 CN2655309Y (en) | 2003-07-16 | 2003-07-16 | Power supply time sequence controlling circuit |
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| CN2655309Y true CN2655309Y (en) | 2004-11-10 |
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| CN 03276899 Expired - Lifetime CN2655309Y (en) | 2003-07-16 | 2003-07-16 | Power supply time sequence controlling circuit |
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Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007134510A1 (en) * | 2006-05-19 | 2007-11-29 | Huawei Technologies Co., Ltd. | A single-desk power supply and a method for providing a power supply |
| CN101206520B (en) * | 2006-12-22 | 2010-09-29 | 鸿富锦精密工业（深圳）有限公司 | Time sequence improving circuit |
| CN102568548A (en) * | 2010-12-31 | 2012-07-11 | 鸿富锦精密工业（深圳）有限公司 | Hard disk power supply circuit |
| CN102866725A (en) * | 2012-09-07 | 2013-01-09 | 浪潮电子信息产业股份有限公司 | Method for realizing time sequence control of system based on CPLD (Complex Programmable Logic Device) |
| WO2013060137A1 (en) * | 2011-10-24 | 2013-05-02 | 中兴通讯股份有限公司 | Apparatus for controlling power-on sequence of multiple power supplies |
| CN103514931A (en) * | 2012-06-29 | 2014-01-15 | 鸿富锦精密工业（深圳）有限公司 | Power supply circuit of hard discs |
| CN104578744A (en) * | 2013-10-25 | 2015-04-29 | 西门子公司 | Load stepped-starting circuit and corresponding leakage protector |
| CN104679210A (en) * | 2015-03-17 | 2015-06-03 | 浪潮集团有限公司 | Device and method for powering on computer on basis of CPLD controller |
| CN105446851A (en) * | 2014-09-27 | 2016-03-30 | 研祥智能科技股份有限公司 | Processor monitoring method and system and MCU (Microprogrammed Control Unit) for monitoring processor |
| WO2017036099A1 (en) * | 2015-08-31 | 2017-03-09 | 华为技术有限公司 | Switch circuit, power source system, and power supply system |
| CN106505848A (en) * | 2016-12-06 | 2017-03-15 | 华南理工大学 | The start-stop control system of great power bidirectional full-bridge DC DC changers and method |
| WO2017084447A1 (en) * | 2015-11-20 | 2017-05-26 | 上海斐讯数据通信技术有限公司 | Power-on timing sequence control circuit, control method, power supply apparatus and electronic terminal |
| CN106773905A (en) * | 2016-11-24 | 2017-05-31 | 中国船舶重工集团公司第七六研究所 | A kind of being disappeared based on power supply sequential trembles the switching value output circuit of control |
| CN107992179A (en) * | 2017-11-01 | 2018-05-04 | 湖北三江航天万峰科技发展有限公司 | A kind of power-on and power-off of multi processor platform and repositioning control device |
| CN108986758A (en) * | 2018-07-23 | 2018-12-11 | 京东方科技集团股份有限公司 | Power-on time sequence control circuit, its driving method and printed circuit board, display panel |
| CN109176523A (en) * | 2018-09-29 | 2019-01-11 | 苏州博众机器人有限公司 | A kind of control circuit, circuit board and robot |
| CN109245510A (en) * | 2018-09-19 | 2019-01-18 | 京信通信系统（中国）有限公司 | Starting current suppression circuit, method, control device and equipment |
| CN112859675A (en) * | 2021-01-04 | 2021-05-28 | 北京无线电测量研究所 | Power-up sequence control device and method, phased array antenna and radar |
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2003
- 2003-07-16 CN CN 03276899 patent/CN2655309Y/en not_active Expired - Lifetime
Cited By (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7847528B2 (en) | 2006-05-19 | 2010-12-07 | Huawei Technologies Co., Ltd. | Single-board power supply structure and method for providing power supply |
| WO2007134510A1 (en) * | 2006-05-19 | 2007-11-29 | Huawei Technologies Co., Ltd. | A single-desk power supply and a method for providing a power supply |
| CN101206520B (en) * | 2006-12-22 | 2010-09-29 | 鸿富锦精密工业（深圳）有限公司 | Time sequence improving circuit |
| CN102568548A (en) * | 2010-12-31 | 2012-07-11 | 鸿富锦精密工业（深圳）有限公司 | Hard disk power supply circuit |
| WO2013060137A1 (en) * | 2011-10-24 | 2013-05-02 | 中兴通讯股份有限公司 | Apparatus for controlling power-on sequence of multiple power supplies |
| CN103514931B (en) * | 2012-06-29 | 2017-04-12 | 赛恩倍吉科技顾问（深圳）有限公司 | Power supply circuit of hard discs |
| CN103514931A (en) * | 2012-06-29 | 2014-01-15 | 鸿富锦精密工业（深圳）有限公司 | Power supply circuit of hard discs |
| CN102866725A (en) * | 2012-09-07 | 2013-01-09 | 浪潮电子信息产业股份有限公司 | Method for realizing time sequence control of system based on CPLD (Complex Programmable Logic Device) |
| CN104578744A (en) * | 2013-10-25 | 2015-04-29 | 西门子公司 | Load stepped-starting circuit and corresponding leakage protector |
| CN104578744B (en) * | 2013-10-25 | 2017-10-03 | 西门子公司 | Load stepped starting circuit and corresponding earth leakage protective device |
| CN105446851A (en) * | 2014-09-27 | 2016-03-30 | 研祥智能科技股份有限公司 | Processor monitoring method and system and MCU (Microprogrammed Control Unit) for monitoring processor |
| CN104679210A (en) * | 2015-03-17 | 2015-06-03 | 浪潮集团有限公司 | Device and method for powering on computer on basis of CPLD controller |
| WO2017036099A1 (en) * | 2015-08-31 | 2017-03-09 | 华为技术有限公司 | Switch circuit, power source system, and power supply system |
| WO2017084447A1 (en) * | 2015-11-20 | 2017-05-26 | 上海斐讯数据通信技术有限公司 | Power-on timing sequence control circuit, control method, power supply apparatus and electronic terminal |
| CN106773905B (en) * | 2016-11-24 | 2019-02-05 | 中国船舶重工集团公司第七一六研究所 | A kind of disappeared based on power supply timing trembles the switching value output circuit of control |
| CN106773905A (en) * | 2016-11-24 | 2017-05-31 | 中国船舶重工集团公司第七六研究所 | A kind of being disappeared based on power supply sequential trembles the switching value output circuit of control |
| CN106505848B (en) * | 2016-12-06 | 2019-06-18 | 华南理工大学 | The start-stop control system and method for great power bidirectional full-bridge DC-DC converter |
| CN106505848A (en) * | 2016-12-06 | 2017-03-15 | 华南理工大学 | The start-stop control system of great power bidirectional full-bridge DC DC changers and method |
| CN107992179A (en) * | 2017-11-01 | 2018-05-04 | 湖北三江航天万峰科技发展有限公司 | A kind of power-on and power-off of multi processor platform and repositioning control device |
| CN107992179B (en) * | 2017-11-01 | 2020-08-11 | 湖北三江航天万峰科技发展有限公司 | Power-on and power-off and reset control device of multiprocessor platform |
| CN108986758A (en) * | 2018-07-23 | 2018-12-11 | 京东方科技集团股份有限公司 | Power-on time sequence control circuit, its driving method and printed circuit board, display panel |
| CN109245510A (en) * | 2018-09-19 | 2019-01-18 | 京信通信系统（中国）有限公司 | Starting current suppression circuit, method, control device and equipment |
| CN109245510B (en) * | 2018-09-19 | 2021-02-23 | 京信通信系统（中国）有限公司 | Starting current suppression circuit, starting current suppression method, control device and equipment |
| CN109176523A (en) * | 2018-09-29 | 2019-01-11 | 苏州博众机器人有限公司 | A kind of control circuit, circuit board and robot |
| CN112859675A (en) * | 2021-01-04 | 2021-05-28 | 北京无线电测量研究所 | Power-up sequence control device and method, phased array antenna and radar |
| CN112859675B (en) * | 2021-01-04 | 2021-11-30 | 北京无线电测量研究所 | Power-up sequence control device and method, phased array antenna and radar |
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Expiration termination date: 20130716 Granted publication date: 20041110 |