CN101944856B - Control circuit of switching power supply for primary side control - Google Patents
Control circuit of switching power supply for primary side control Download PDFInfo
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- CN101944856B CN101944856B CN 201010225480 CN201010225480A CN101944856B CN 101944856 B CN101944856 B CN 101944856B CN 201010225480 CN201010225480 CN 201010225480 CN 201010225480 A CN201010225480 A CN 201010225480A CN 101944856 B CN101944856 B CN 101944856B
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Abstract
The invention provides a control circuit of a switching power supply for primary side control. The control circuit comprises an error amplifier, a switching signal generating unit, a driving unit and a current comparator, wherein the error amplifier is used for maintaining an error value between a feedback voltage and a reference voltage when the current of a secondary side rectifier tube is zero and controlling the switching signal generating unit to generate a pulse width modulation (PWM) signal so as to regulate the off time of a power switching tube; a positive input end, a negative input end and an output end of the current comparator are connected with a detecting current input end, a reference current, and a current input end of a switching signal generating unit respectively; the current comparator is used for comparing a detecting current with the reference current and controlling the switching signal generating unit to generate the PWM signal so as to regulate the on time of the power switching tube; and the output end of the switching signal generating unit is connected with a base of the power switching tube through a driving unit. The control circuit does not perform sampling in fixed scheduled time so as not to cause an error due to the difference of specific systems.
Description
Technical field
The present invention relates to the switch power technology field, particularly a kind of control circuit of Switching Power Supply of former limit control.
Background technology
It is little that Switching Power Supply has a volume, and therefore the advantage that efficient height and electric current are large is widely used in the occasions such as charger for mobile phone and notebook adapter.
The former limit of the at present most of employing of the control circuit of Switching Power Supply control mode, with respect to the secondary control mode, thereby former limit control mode utilizes an auxiliary winding of transformer to reflect the control of the voltage realization power output of secondary winding.
Referring to Fig. 1, this figure is the switching power source control circuit schematic diagram of limit, prior art Central Plains control.
This switching power source control circuit comprises: controller 10a, transformer 20a, power switch pipe Q, the first divider resistance R1, the second divider resistance R2, detection resistance R 3, former limit rectifying tube D1, secondary rectifying tube D2, power supply capacitor C 1 and output capacitance C2.
Described controller 10a comprises operational amplifier 101a, sample holding unit 102a, fixed pulse generation unit 103a, switching signal generation unit 104a, driver element 105a and current comparator 106a.
Described the first divider resistance R1 and the second divider resistance R2 are used for auxiliary winding 202a is carried out dividing potential drop, and the feedback voltage Vfb that dividing potential drop is obtained is input to the positive input terminal of operational amplifier 101a, and the negative input end of operational amplifier 101a connects reference voltage V inf.
Fixed pulse generation unit 103a is used for producing sampling pulse signal at fixed time, be specifically as follows: after power switch pipe Q turn-offs, described fixed pulse generation unit 103a begins timing, when timing reaches the scheduled time, exports a sampling pulse signal.
Owing to there are differences between the different system, so can cause the range of application of this switching power source control circuit narrower with the output time of pulse signal is fixing.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of control circuit of Switching Power Supply of former limit control, can enlarge the range of application of the control circuit of the Switching Power Supply of controlling on former limit.
The invention provides a kind of control circuit of Switching Power Supply of former limit control, comprising: error amplifier, switching signal generation unit, driver element and current comparator;
The positive input terminal of described error amplifier connects the feedback voltage input, and negative input end connects reference voltage, and output connects the voltage input end of described switching signal generation unit; Described feedback voltage input is the common port on the first divider resistance and the second divider resistance; The different name end of the auxiliary winding of transformer is by the first divider resistance and the second divider resistance ground connection of successively series connection; Feedback voltage when described error amplifier is used for that secondary rectifying tube electric current is zero keeps with the error amount of reference voltage, controls described switching signal generation unit generation pwm signal, with the turn-off time of regulating power switching tube;
The positive input terminal of described current comparator connects the detection current input terminal, and negative input end connects reference current, and output connects the current input terminal of described switching signal generation unit; Described detection current input terminal is by the 3rd grounding through resistance; The different name end of the former limit winding of described transformer is power switch pipe and the 3rd grounding through resistance by connecting successively; Described current comparator is used for detecting electric current and reference current compares, and controls described switching signal generation unit and produces pwm signal, with the service time of regulating power switching tube;
The output of described switching signal generation unit connects the base stage of described power switch pipe by driver element; The output of described switching signal generation unit connects the control end of described error amplifier.
Preferably, described error amplifier comprises: first order amplifier, Postponement module, second level amplifier, feedback network, controlled output module, voltage keep electric capacity and control switch;
The positive input terminal of described first order amplifier connects described feedback voltage input, and negative input end connects the output of described feedback network, and output connects the input of described Postponement module, and output also connects the control end of described controlled output module;
The output of described Postponement module connects the input of second level amplifier; The output of described second level amplifier connects the input of described controlled output module; The output of described second level amplifier connects the first input end of described feedback network; The second input of described feedback network connects described reference voltage;
The output of described controlled output module keeps capacity earth by described voltage, simultaneously by described control switch ground connection; The control end of described control switch connects the output of described switching signal generation unit.
Preferably, described first order amplifier comprises: PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the first current source, the second current source and the 3rd current source;
Described PMOS pipe and the 2nd PMOS pipe form input to pipe, and the grid of a PMOS pipe connects described feedback voltage input; Described PMOS pipe and the source electrode of the 2nd PMOS pipe rear connection the first current source that links together, the drain electrode of a PMOS pipe is by the second current source ground connection, and the 3rd current source ground connection is passed through in the drain electrode of the 2nd PMOS pipe;
The 3rd PMOS pipe, the 4th PMOS pipe, the 5th NMOS pipe and the 6th NMOS pipe form mirror current source;
The source electrode of the 3rd PMOS pipe and the 4th PMOS pipe links together and connects builtin voltage, and grid also links together;
The drain electrode of the 3rd PMOS pipe connects the drain electrode of the 5th NMOS pipe, and the drain electrode of the 4th PMOS pipe connects the drain electrode of the 6th NMOS pipe;
The grid of the grid of the 5th NMOS pipe and the 6th NMOS pipe all connects bias voltage;
The source electrode of the 5th NMOS pipe connects the drain electrode of the 2nd PMOS pipe, and the source electrode of the 6th NMOS pipe connects the drain electrode of a PMOS pipe;
The drain electrode of the 4th PMOS pipe connects the input of described Postponement module as the output of first order amplifier.
Preferably, described Postponement module comprises delay resistance and postpones electric capacity;
One end of described delay resistance connects the output of described first order amplifier, an end of other end connection delay electric capacity, and the other end that postpones electric capacity connects the input of described second level amplifier.
Preferably, described second level amplifier comprises the 7th PMOS pipe, resistance and the 4th current source;
The grid of described the 7th PMOS pipe connects the common port of described delay resistance and described delay electric capacity, and source electrode connects described builtin voltage, and drain electrode is by described the 4th current source ground connection;
The drain electrode of described the 7th PMOS pipe is by the described resistance and the grid that is connected electric capacity and connects the 7th PMOS pipe of successively series connection;
The drain electrode of described the 7th PMOS pipe is as the output of second level amplifier.
Preferably, described feedback network comprises the 4th resistance and the 5th resistance;
One end of described the 4th resistance connects the grid of described the 2nd PMOS pipe, simultaneously by described the 5th grounding through resistance;
The other end of described the 4th resistance connects the output of described second level amplifier.
Preferably, described controlled output module comprises the 8th PMOS pipe, the 9th PMOS pipe, the tenth PMOS pipe, the 11 PMOS pipe, the 12 NMOS pipe, the 13 NMOS pipe, PNP pipe, the 2nd NPN pipe, the 3rd NPN pipe, the 4th PNP pipe;
The source electrode of described the 8th PMOS pipe connects builtin voltage, and drain electrode is by the tenth PMOS pipe and the 2nd NPN pipe ground connection of successively series connection;
The base stage of described the 2nd NPN pipe connects the output of described second level amplifier;
The base stage of described the 4th PNP pipe connects the output of described second level amplifier, and emitter is by the 12 NMOS pipe ground connection, and collector electrode connects builtin voltage;
Described the 12 NMOS pipe and the 13 NMOS pipe connect into mirror current source;
The drain electrode of described the 13 NMOS pipe connects builtin voltage by the 11 PMOS pipe and the 9th PMOS pipe of series connection successively;
The base stage of the one PNP pipe connects the emitter of the 2nd NPN pipe, and collector electrode connects builtin voltage, and emitter connects the emitter of the 3rd NPN pipe, and the base stage of the 3rd NPN pipe connects the emitter of the 4th PNP pipe, the grounded collector of the 3rd NPN pipe;
The emitter of described the 3rd NPN pipe is as the output of error amplifier, and emitter keeps capacity earth by described voltage simultaneously, by described control switch ground connection.
Preferably; also comprise protected location; the input signal of described protected location is described reference voltage, feedback voltage and pwm signal; output connects the control end of described driver element; be used for when described the first divider resistance open circuit or described the second divider resistance short circuit; the output control signal stops the driver element output pwm signal to driver element.
Preferably, described protected location comprise comparator, inverter, trailing edge Postponement module, first and door, second with and rest-set flip-flop;
The positive input terminal of described comparator connects the feedback voltage input, and negative input end connects reference voltage, output connect described first with the first input end of door;
Described pwm signal is through second input of connection described first behind the inverter with door;
Described pwm signal is through the first input end of connection described second behind the described trailing edge Postponement module with door; Described first be connected with the output of door described second with the second input of door, described second with output be connected the reset terminal of rest-set flip-flop;
The set end of described rest-set flip-flop connects power on signal, and output connects the control end of described driver element.
Compared with prior art, the present invention has the following advantages:
Switching power source control circuit provided by the invention, when the electric current vanishing in the secondary rectifying tube, the voltage of responding on the auxiliary winding is also since the violent decline of positive voltage, and error amplifier can amplify the feedback voltage of this moment and the error amount of reference voltage, and error amount is saved as the pwm signal that a voltage comes control switch signal generation unit generation power ratio control switching tube to open or turn-off as control variables in one-period.This control circuit has saved sampling hold circuit of the prior art, and the control circuit in the present embodiment is to regulate pwm signal according to the magnitude of voltage on the auxiliary winding of the moment correspondence of the electric current vanishing of secondary rectifying tube, rather than utilizes the fixing scheduled time to sample.Therefore, can not cause error because of the difference of concrete system.
Description of drawings
Fig. 1 is the switching power source control circuit schematic diagram of limit, prior art Central Plains control;
Fig. 2 is embodiment one structure chart provided by the invention;
Fig. 3 is the structure chart of the error amplifier that provides of the embodiment of the invention;
Fig. 4 is the internal circuit diagram of the present invention's error amplifier shown in Figure 3;
Fig. 5 is the oscillogram of several main voltages among the present invention;
Fig. 6 is the another example structure figure of switching power source control circuit of the former limit control that provides of the embodiment of the invention;
Fig. 7 is the internal circuit diagram of protection module provided by the invention;
Fig. 8 is the oscillogram of several main voltages corresponding to Fig. 6 embodiment of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Referring to Fig. 2, this figure is embodiment one structure chart provided by the invention.
The control circuit of the Switching Power Supply of the former limit control that present embodiment provides comprises: error amplifier 101, switching signal generation unit 104, driver element 105 and current comparator 106.
The positive input terminal of described error amplifier 101 connects the feedback voltage input, and negative input end connects reference voltage V inf, and output connects the voltage input end of described switching signal generation unit 104; Described feedback voltage input is the common port on the first divider resistance R1 and the second divider resistance R2; The different name end of the auxiliary winding 202 of transformer 20 is by the first divider resistance R1 and the second divider resistance R2 ground connection of successively series connection; Feedback voltage when described error amplifier 101 is used for that secondary rectifying tube D2 electric current is zero keeps with the error amount of reference voltage, controls described switching signal generation unit 104 generation pwm signals, with the turn-off time of regulating power switching tube Q;
The voltage at auxiliary winding 202 two ends of described transformer 20 is delivered to the voltage on the R2 positive input terminal of error amplifier 101 by the first divider resistance R1 and the second divider resistance R2 dividing potential drop as feedback voltage Vfb.
When power switch pipe Q becomes shutoff by conducting, secondary rectifying tube D2 conducting, auxiliary winding 202 induces positive voltage, and the difference between 101 pairs of feedback voltage Vfb of error amplifier and the reference voltage V inf is amplified, voltage Ve after output is amplified; When flowing through the electric current vanishing of secondary rectifying tube D2, assist this moment the voltage on the winding 202 to begin acutely to descend from positive voltage, described error amplifier 101 can maintain error amount corresponding to Vfb positive voltage rearmost point, thereby control switch signal generation unit 104, generate pwm signal, the turn-off time of regulating power switching tube Q, realize the control to transformer 20 secondary power outputs.
The positive input terminal of described current comparator 106 connects the detection current input terminal, and negative input end connects reference current Iinf, and output connects the current input terminal of described switching signal generation unit 104; Described detection current input terminal is by the 3rd resistance R 3 ground connection; The different name end of the former limit winding 201 of described transformer 20 is power switch pipe Q and the 3rd resistance R 3 ground connection by connecting successively; Described current comparator 106 is used for detecting electric current and reference current Iinf compares, and controls described switching signal generation unit 104 and produces pwm signal, with the service time of regulating power switching tube Q;
The output of described switching signal generation unit 104 connects the base stage of described power switch pipe Q by driver element 105; The output of described switching signal generation unit 104 connects the control end of described error amplifier 101.
The switching power source control circuit that present embodiment provides, when the electric current vanishing in the secondary rectifying tube, the voltage of responding on the auxiliary winding is also since the violent decline of positive voltage, and error amplifier 101 can amplify the feedback voltage of this moment and the error amount of reference voltage, and error amount is saved as the pwm signal that a voltage comes control switch signal generation unit 104 generation power ratio control switching tube Q to open or turn-off as control variables in one-period.This control circuit has saved sampling hold circuit of the prior art, and the control circuit in the present embodiment is to regulate pwm signal according to the magnitude of voltage on the auxiliary winding of the moment correspondence of the electric current vanishing of secondary rectifying tube.Rather than the magnitude of voltage on the auxiliary winding is regulated pwm signal when having electric current in the secondary rectifying tube of the prior art.Therefore, can solve since on the auxiliary winding between positive voltage and the output voltage because the problem of the error that secondary rectifying tube D2 conduction voltage drop causes.
Introduce in detail the internal structure of the error amplifier that the embodiment of the invention provides below in conjunction with Fig. 3 and Fig. 4.
At first, referring to Fig. 3, this figure is the structure chart of the error amplifier that provides of the embodiment of the invention.
Described error amplifier comprises: first order amplifier 306, Postponement module 307, second level amplifier 308, feedback network 305, controlled output module 302, voltage keep electric capacity 303 and control switch 304;
The positive input terminal of described first order amplifier 306 connects described feedback voltage Vfb input, negative input end connects the output of described feedback network 305, output connects the input of described Postponement module 307, and output also connects the control end of described controlled output module 302;
The output of described Postponement module 307 connects the input of second level amplifier 308; The output of described second level amplifier 308 connects the input of described controlled output module 302; The output of described second level amplifier 308 connects the first input end of described feedback network 305; The second input of described feedback network 305 connects described reference voltage V inf;
The output voltage of second level amplifier 308 is Vop.
The output of described controlled output module 302 keeps electric capacity 303 ground connection by described voltage, simultaneously by described control switch 304 ground connection; The control end of described control switch 304 connects the output of described switching signal generation unit.
Referring to Fig. 4, this figure is the internal circuit diagram of the present invention's error amplifier shown in Figure 3.
The below introduces respectively modules one by one.
First order amplifier 401:
Described PMOS pipe M1 and the 2nd PMOS pipe M2 form input to pipe, and the grid of PMOS pipe M1 connects described feedback voltage Vfb input; The source electrode of described PMOS pipe M1 and the 2nd PMOS pipe M2 rear connection the first current source I1 that links together, the drain electrode of PMOS pipe M1 is by the second current source I2 ground connection, and the drain electrode of the 2nd PMOS pipe M2 is by the 3rd current source I3 ground connection;
The 3rd PMOS pipe M3, the 4th PMOS pipe M4, the 5th NMOS pipe M5 and the 6th NMOS pipe M6 form mirror current source;
The source electrode of the 3rd PMOS pipe M3 and the 4th PMOS pipe M4 links together and connects builtin voltage, and grid also links together;
The drain electrode of the 3rd PMOS pipe M3 connects the drain electrode of the 5th NMOS pipe M5, and the drain electrode of the 4th PMOS pipe M4 connects the drain electrode of the 6th NMOS pipe M6;
The grid of the 5th NMOS pipe M5 all connects bias voltage V with the grid of the 6th NMOS pipe M6
B
The source electrode of the 5th NMOS pipe M5 connects the drain electrode of the 2nd PMOS pipe M2, and the source electrode of the 6th NMOS pipe M6 connects the drain electrode of PMOS pipe M1;
The drain electrode of the 4th PMOS pipe M4 connects the input of described Postponement module 403 as the output of first order amplifier 401.
Postponement module 403:
The end of described delay resistance Rd connects the output (namely connecting the drain electrode of the 4th PMOS pipe M4) of described first order amplifier 401, the end of other end connection delay capacitor C z, the other end that postpones electric capacity Cz connects the input of described second level amplifier 402.
Second level amplifier 402:
The grid of described the 7th PMOS pipe M7 connects the common port of described delay resistance Rd and described delay electric capacity Cz, and source electrode connects described builtin voltage, and drain electrode is by described the 4th current source I4 ground connection;
The drain electrode of described the 7th PMOS pipe M7 by successively series connection described resistance R z and be connected electric capacity Cz and connect the grid that the 7th PMOS manages M7;
The drain electrode of described the 7th PMOS pipe M7 is as the output of second level amplifier 402.
Feedback network 404:
One end of described the 4th resistance R 4 connects the grid of described the 2nd PMOS pipe M2, simultaneously by described the 5th resistance R 5 ground connection;
The other end of described the 4th resistance R 4 connects the output (namely connecting the drain electrode of the 7th PMOS pipe M7) of described second level amplifier 402.
Controlled output module 405:
The source electrode of described the 8th PMOS pipe M8 connects builtin voltage, and drain electrode is by the tenth PMOS pipe M10 and the 2nd NPN pipe b2 ground connection of successively series connection;
The base stage of described the 2nd NPN pipe b2 connects the output end vo p of described second level amplifier 402;
The base stage of described the 4th PNP pipe b4 connects the output of described second level amplifier 402, and emitter is by the 12 NMOS pipe M12 ground connection, and collector electrode connects builtin voltage;
Described the 12 NMOS pipe M12 and the 13 NMOS pipe M13 connect into mirror current source; The drain electrode of described the 13 NMOS pipe M13 connects builtin voltage by the 11 PMOS pipe M11 and the 9th PMOS pipe M9 of series connection successively;
The base stage of the one PNP pipe b1 connects the emitter of the 2nd NPN pipe b2, and collector electrode connects builtin voltage, and emitter connects the emitter of the 3rd NPN pipe b3, and the base stage of the 3rd NPN pipe b3 connects the emitter of the 4th PNP pipe b4, the grounded collector of the 3rd NPN pipe b3;
The emitter of described the 3rd NPN pipe b3 is as the output Ve of error amplifier, and emitter keeps electric capacity 406 ground connection by described voltage simultaneously, by described control switch 407 ground connection.
Describe the operation principle of error amplifier in detail below in conjunction with Fig. 5.
When feedback voltage Vfb is timing because the existence of feedback network 305, the output voltage V op of second level amplifier 308 be feedback voltage Vfb on the occasion of with the error value of magnification of reference voltage V inf; Wherein, multiplication factor is determined by the feedback factor of feedback network 305.
When the electric current among the secondary rectifying tube D2 is zero, feedback voltage Vfb begins by on the occasion of violent decline, this moment is because the existence of delay cell 307, the output voltage V op of second level amplifier 308 still can reflect feedback voltage Vfb on the occasion of with the error value of magnification of reference voltage V inf.And the output voltage V of first order amplifier 306 changes rapidly state, uprised by low, control described controlled output module 302 its charging and discharging currents is disappeared, keep on the electric capacity 303 thereby error value of magnification corresponding to critical point at a time when the feedback voltage Vfb decline is deposited with voltage, i.e. voltage Ve.
The switch periods of power switch pipe Q is comprised of the Tonp among Fig. 5, Tons and Toff three parts.
Wherein, wherein the duration of Tonp is determined by current comparator among Fig. 2 106, and when the electric current in the former limit inductance 201 during greater than reference current Iinf, pwm signal output electronegative potential, Cout exports electronegative potential, switch-off power switching tube Q.
The duration of Tons is determined by the electric current among the secondary rectifying tube D2, and when not having electric current to pass through among the D2, Tons finishes, and feedback voltage Vfb begins by on the occasion of violent decline.When the positive input terminal of the first order amplifier 306 in the error amplifier 101 detects Vfb and acutely descends, output V changes rapidly state, rise to supply voltage from the current signal of a simulation, thereby make the controlled output level module 302 forfeiture current capacities in the described error amplifier 101, voltage keeps the voltage Ve on the electric capacity 303 to be held, and the output voltage V op of second level amplifier 308 begins slowly to descend at this moment.
The duration of Toff is relatively determined by triangular signal Vm and Ve, Vm is the internal signal that described switching signal generation unit 104 produces, as shown in Figure 5, when finishing, Tons begins to rise with certain slope from a voltage, when rising to Ve, PWM exports high potential, opens power switch pipe Q, Ve is set to zero potential, and one-period finishes.
The 3rd PMOS pipe M3, the 4th PMOS pipe M4, the 5th NMOS pipe M5 and the 6th NMOS pipe M6 form the output stage of first order amplifier.Wherein, the 4th PMOS pipe M4 connects output voltage V with the drain electrode of the 6th NMOS pipe M6.
Because the feedback effect that first order amplifier 401, second level amplifier 402, delay cell 403 and feedback network 404 form, when Vfb the Tons stage be on the occasion of the time, the voltage that the 2nd PMOS manages the M2 gate input equals Vfb.The output voltage V of first order amplifier 401 is connected to the grid of the 7th PMOS pipe M7, thereby makes the electric current that equals current source I4 by the source-drain current of the 7th PMOS pipe M7.The output voltage of first order amplifier 401 connects the 8th PMOS pipe M8 and the 9th PMOS pipe M9 of controlled output level module 405 simultaneously, thereby makes the output voltage V e of controlled output level module 405 equal input voltage Vop.
When Vfb acutely descends, the output voltage V of first order amplifier 401 acutely rises to supply voltage, thereby make the 8th PMOS pipe M8 and the 9th PMOS pipe M9 blocking-up electric current, and the grid voltage Vd of the 7th PMOS pipe M7 is because the delayed action that postpones resistance Rd and postpone electric capacity Cz it's one period time of delay makes past Vop and just descends, thus the value of Vop when making the output voltage V e of controlled output level module 405 be breakover point.
The tenth PMOS pipe M10 and the 11 PMOS pipe M11 are depletion type PMOS pipe in the controlled output level module 405, and it is in order to play the effect of restriction branch current that grid and source electrode link together.The one PNP pipe b1, the 2nd NPN pipe b2, the 3rd NPN pipe b3 and the 4th PNP pipe b4 form the output stage of Class AB class, when the source-drain current of the 8th PMOS pipe M8 and the 9th PMOS pipe M9 is zero, the ability vanishing that goes out electric current and draw electric current of the output stage of Class AB class, thus voltage keeps the voltage on the electric capacity 406 to remain unchanged.
The embodiment of the invention also provides a kind of control circuit of Switching Power Supply of former limit control, and referring to Fig. 6, this figure is another example structure figure provided by the invention.
The difference of the embodiment that present embodiment and Fig. 2 provide is to have increased protected location 107; the effect of this protected location 107 is to prevent that output voltage is uncontrolled when the first divider resistance 108 open circuits or 109 short circuit of the second divider resistance, thereby causes output capacitance C2 voltage rising aircraft bombing.
The input signal of protected location 107 is described reference voltage V inf, feedback voltage Vfb and pwm signal; output connects the control end of described driver element 105; be used for when described the first divider resistance 108 open circuits or described the second divider resistance 109 short circuit; the output control signal stops driver element 105 output pwm signals to driver element 105.
If the first divider resistance 108 open circuit or 109 short circuits of the second divider resistance, feedback voltage Vfb identically vanishing so, control circuit will be judged system works in under-voltage condition, therefore will control pwm signal output maximum duty cycle, thereby cause output voltage to raise and aircraft bombing.The effect of described protection module 107 arranges for this situation just; if the first divider resistance 108 open circuit or 109 short circuits of the second divider resistance; described protection module 107 is with the output protection signal, thereby prevention driver element 105 output pwm signals are to power switch pipe Q.
The physical circuit figure of the described protected location that the embodiment of the invention also provides is referring to Fig. 7.
Protected location comprises comparator 702, inverter 706, trailing edge Postponement module 701, first and door 705, second and 703 and rest-set flip-flop 704;
The positive input terminal of described comparator 702 connects feedback voltage Vfb, and negative input end connects reference voltage V inf, output connect described first with the first input end of door 705;
Described pwm signal is through second input of connection described first behind the inverter 706 with door 705;
Described pwm signal is through the first input end of connection described second behind the described trailing edge Postponement module 701 with door 703; Described first be connected with door 705 output described second with the second input of door 703, described second is connected the reset terminal R of rest-set flip-flop 704 with 703 output;
The set end S of described rest-set flip-flop 704 connects power on signal, and output connects the control end of described driver element 105.
The operation principle of this protected location is described below in conjunction with the oscillogram of each signal among Fig. 8.
Wherein, first represents with A with door 705 output signal, and second represents with B with the output signal of door 703.
In the normal cycle, when pwm signal was high potential, Vfb was negative potential, and this moment second, the output signal B with door 703 was electronegative potential, first with the output signal A of door 705 be electronegative potential, the guard signal of at this moment rest-set flip-flop 704 outputs is electronegative potential.When pwm signal was electronegative potential, this moment, Vfb was high potential, comparator 702 output electronegative potentials, first with the output signal A of door 705 be electronegative potential, the R end of rest-set flip-flop 704 also be electronegative potential, so rest-set flip-flop 704 guard signal or the electronegative potential exported.
When system in open-circuit condition lower time; when pwm signal is high potential, first with door 705 output signal A be electronegative potential, second with the output signal B of door 703 be electronegative potential; guard signal (if guard signal is high potential, then control chip is not opened power switch pipe Q) is electronegative potential.When pwm signal is electronegative potential; owing to can't see the positive voltage of Vfb; comparator 702 output high potentials; this moment first, the output signal A with door 705 was high potential; second with door 703 output signal B also be high potential; guard signal is set to high potential, thereby stops the again generation of pwm signal.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Although the present invention discloses as above with preferred embodiment, yet is not to limit the present invention.Any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (9)
1. the control circuit of the Switching Power Supply of a former limit control is characterized in that, comprising: error amplifier, switching signal generation unit, driver element and current comparator;
The positive input terminal of described error amplifier connects the feedback voltage input, and negative input end connects reference voltage, and output connects the voltage input end of described switching signal generation unit; Described feedback voltage input is the common port on the first divider resistance and the second divider resistance; The different name end of the auxiliary winding of transformer is by the first divider resistance and the second divider resistance ground connection of successively series connection; Feedback voltage when described error amplifier is used for that secondary rectifying tube electric current is zero keeps with the error amount of reference voltage, controls described switching signal generation unit generation pwm signal, with the turn-off time of regulating power switching tube;
The positive input terminal of described current comparator connects the detection current input terminal, and negative input end connects reference current, and output connects the current input terminal of described switching signal generation unit; Described detection current input terminal is by the 3rd grounding through resistance; The different name end of the former limit winding of described transformer is power switch pipe and the 3rd grounding through resistance by connecting successively; Described current comparator is used for detecting electric current and reference current compares, and controls described switching signal generation unit and produces pwm signal, with the service time of regulating power switching tube;
The output of described switching signal generation unit connects the base stage of described power switch pipe by driver element; The output of described switching signal generation unit connects the control end of described error amplifier.
2. control circuit according to claim 1 is characterized in that, described error amplifier comprises: first order amplifier, Postponement module, second level amplifier, feedback network, controlled output module, voltage keep electric capacity and control switch;
The positive input terminal of described first order amplifier connects described feedback voltage input, and negative input end connects the output of described feedback network, and output connects the input of described Postponement module, and output also connects the control end of described controlled output module;
The output of described Postponement module connects the input of second level amplifier; The output of described second level amplifier connects the input of described controlled output module; The output of described second level amplifier connects the first input end of described feedback network; The second input of described feedback network connects described reference voltage;
The output of described controlled output module keeps capacity earth by described voltage, simultaneously by described control switch ground connection; The control end of described control switch connects the output of described switching signal generation unit.
3. control circuit according to claim 2, it is characterized in that described first order amplifier comprises: PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the first current source, the second current source and the 3rd current source;
Described PMOS pipe and the 2nd PMOS pipe form input to pipe, and the grid of a PMOS pipe connects described feedback voltage input; Described PMOS pipe and the source electrode of the 2nd PMOS pipe rear connection the first current source that links together, the drain electrode of a PMOS pipe is by the second current source ground connection, and the 3rd current source ground connection is passed through in the drain electrode of the 2nd PMOS pipe;
The 3rd PMOS pipe, the 4th PMOS pipe, the 5th NMOS pipe and the 6th NMOS pipe form mirror current source;
The source electrode of the 3rd PMOS pipe and the 4th PMOS pipe links together and connects builtin voltage, and grid also links together;
The drain electrode of the 3rd PMOS pipe connects the drain electrode of the 5th NMOS pipe, and the drain electrode of the 4th PMOS pipe connects the drain electrode of the 6th NMOS pipe;
The grid of the grid of the 5th NMOS pipe and the 6th NMOS pipe all connects bias voltage;
The source electrode of the 5th NMOS pipe connects the drain electrode of the 2nd PMOS pipe, and the source electrode of the 6th NMOS pipe connects the drain electrode of a PMOS pipe;
The drain electrode of the 4th PMOS pipe connects the input of described Postponement module as the output of first order amplifier.
4. according to claim 2 or 3 described control circuits, it is characterized in that described Postponement module comprises and postpones resistance and postpone electric capacity;
One end of described delay resistance connects the output of described first order amplifier, an end of other end connection delay electric capacity, and the other end that postpones electric capacity connects the input of described second level amplifier.
5. control circuit according to claim 4 is characterized in that, described second level amplifier comprises the 7th PMOS pipe, resistance R z and the 4th current source;
The grid of described the 7th PMOS pipe connects the common port of described delay resistance and described delay electric capacity, and source electrode connects builtin voltage, and drain electrode is by described the 4th current source ground connection;
The drain electrode of described the 7th PMOS pipe is by the described resistance R z and the grid that is connected electric capacity and connects the 7th PMOS pipe of successively series connection;
The drain electrode of described the 7th PMOS pipe is as the output of second level amplifier.
6. control circuit according to claim 3 is characterized in that, described feedback network comprises the 4th resistance and the 5th resistance;
One end of described the 4th resistance connects the grid of described the 2nd PMOS pipe, simultaneously by described the 5th grounding through resistance;
The other end of described the 4th resistance connects the output of described second level amplifier.
7. control circuit according to claim 3, it is characterized in that described controlled output module comprises the 8th PMOS pipe, the 9th PMOS pipe, the tenth PMOS pipe, the 11 PMOS pipe, the 12 NMOS pipe, the 13 NMOS pipe, PNP pipe, the 2nd NPN pipe, the 3rd NPN pipe and the 4th PNP pipe;
The source electrode of described the 8th PMOS pipe connects builtin voltage, and drain electrode is by the tenth PMOS pipe and the 2nd NPN pipe ground connection of successively series connection;
The base stage of described the 2nd NPN pipe connects the output of described second level amplifier;
The base stage of described the 4th PNP pipe connects the output of described second level amplifier, and emitter is by the 12 NMOS pipe ground connection, and collector electrode connects builtin voltage;
Described the 12 NMOS pipe and the 13 NMOS pipe connect into mirror current source;
The drain electrode of described the 13 NMOS pipe connects builtin voltage by the 11 PMOS pipe and the 9th PMOS pipe of series connection successively;
The base stage of the one PNP pipe connects the emitter of the 2nd NPN pipe, and collector electrode connects builtin voltage, and emitter connects the emitter of the 3rd NPN pipe, and the base stage of the 3rd NPN pipe connects the emitter of the 4th PNP pipe, the grounded collector of the 3rd NPN pipe;
The emitter of described the 3rd NPN pipe is as the output of error amplifier, and emitter keeps capacity earth by described voltage simultaneously, by described control switch ground connection.
8. control circuit according to claim 1; it is characterized in that; also comprise protected location; the input signal of described protected location is described reference voltage, feedback voltage and pwm signal; the output of described protected location connects the control end of described driver element; be used for when described the first divider resistance open circuit or described the second divider resistance short circuit, the output control signal stops the driver element output pwm signal to driver element.
9. control circuit according to claim 8 is characterized in that, described protected location comprise comparator A, inverter, trailing edge Postponement module, first and door, second with and rest-set flip-flop;
The positive input terminal of described comparator A connects the feedback voltage input, and negative input end connects reference voltage, output connect described first with the first input end of door;
Described pwm signal is through second input of connection described first behind the inverter with door;
Described pwm signal is through the first input end of connection described second behind the described trailing edge Postponement module with door; Described first be connected with the output of door described second with the second input of door, described second with output be connected the reset terminal of rest-set flip-flop;
The set end of described rest-set flip-flop connects power on signal, and output connects the control end of described driver element.
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| CN 201010225480 CN101944856B (en) | 2010-07-13 | 2010-07-13 | Control circuit of switching power supply for primary side control |
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| CN 201010225480 CN101944856B (en) | 2010-07-13 | 2010-07-13 | Control circuit of switching power supply for primary side control |
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| CN101944856A CN101944856A (en) | 2011-01-12 |
| CN101944856B true CN101944856B (en) | 2013-01-23 |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102364858B (en) * | 2011-02-01 | 2012-10-24 | 杭州士兰微电子股份有限公司 | Constant-current switching power supply controller capable of controlling through primary side and method |
| CN102368667B (en) * | 2011-03-25 | 2013-10-16 | 杭州士兰微电子股份有限公司 | Offline type AC-DC (Alternating Current-Direct Current) control circuit and converting circuit comprising same |
| CN102291896A (en) * | 2011-09-07 | 2011-12-21 | 上海晶丰明源半导体有限公司 | Light emitting diode (LED) constant current control circuit with input voltage sampling and compensation function |
| CN104582174B (en) * | 2014-12-31 | 2017-08-25 | 无锡华润矽科微电子有限公司 | The LED drive circuit and its driving method protected with sampling resistor |
| CN104467118B (en) * | 2014-12-31 | 2017-08-08 | 展讯通信（上海）有限公司 | Charging method, device, charger, charging equipment and charging system |
| CN110098750B (en) * | 2019-01-23 | 2020-12-08 | 上海权策微电子技术有限公司 | Current delay compensation structure for primary side control |
| CN116667683B (en) * | 2023-08-01 | 2023-10-24 | 苏州瑞铬优电子科技有限公司 | Primary side switch control circuit based on tap transformer |
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| CN101171740A (en) * | 2005-05-09 | 2008-04-30 | 阿莱戈微系统公司 | Capacitor charging methods and apparatus |
| CN101471600A (en) * | 2007-11-29 | 2009-07-01 | 意法半导体股份有限公司 | Isolated voltage converter with feedback on the primary winding, and corresponding method for controlling the output voltage |
| CN201435677Y (en) * | 2009-06-19 | 2010-03-31 | Bcd半导体制造有限公司 | Flyback switch power supply |
| CN101764522A (en) * | 2008-12-22 | 2010-06-30 | 电力集成公司 | Flyback power supply with forced primary regulation |
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| ITTO20070862A1 (en) * | 2007-11-29 | 2009-05-30 | St Microelectronics Srl | VOLTAGE ISOLATED CONVERTER WITH FEEDBACK TO THE PRIMARY AND PASSIVE SNUBBER NETWORK, AND RELATIVE CONTROL METHOD |
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|---|---|---|---|---|
| CN101171740A (en) * | 2005-05-09 | 2008-04-30 | 阿莱戈微系统公司 | Capacitor charging methods and apparatus |
| CN101471600A (en) * | 2007-11-29 | 2009-07-01 | 意法半导体股份有限公司 | Isolated voltage converter with feedback on the primary winding, and corresponding method for controlling the output voltage |
| CN101764522A (en) * | 2008-12-22 | 2010-06-30 | 电力集成公司 | Flyback power supply with forced primary regulation |
| CN201435677Y (en) * | 2009-06-19 | 2010-03-31 | Bcd半导体制造有限公司 | Flyback switch power supply |
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Effective date of registration: 20210203 Address after: No. 1600, Zixing Road, Minhang District, Shanghai 200241 Patentee after: BCD (SHANGHAI) MICRO-ELECTRONICS Ltd. Address before: 200241 no.800, Yishan Road, Xuhui District, Shanghai Patentee before: BCD Semiconductor Manufacturing Ltd. |
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