CN114237092A - Level signal type on-off control circuit - Google Patents
Level signal type on-off control circuit Download PDFInfo
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- CN114237092A CN114237092A CN202111368734.1A CN202111368734A CN114237092A CN 114237092 A CN114237092 A CN 114237092A CN 202111368734 A CN202111368734 A CN 202111368734A CN 114237092 A CN114237092 A CN 114237092A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
Abstract
The invention relates to a level signal type on-off control circuit in the technical field of power supply, comprising: the power-on timing control circuit comprises a power-on timing control unit (101) and a switch unit (102), wherein the power-on timing control unit (101) is used for generating a level signal for controlling the on action or the off action of the switch unit (102); the switch unit (102) is used for receiving the level signal output by the power-on sequence control unit (101) and executing a turn-on action or a turn-off action according to the level signal so as to supply power to a load. The invention overcomes the defects of complex structure, easy misoperation and incapability of realizing the power-on time sequence control function of the existing switch circuit, realizes the self-adaptive power-on time sequence control function of two paths of power supplies which are not in common, and has the characteristics of small volume, strong anti-interference capability and high switch reliability.
Description
Technical Field
The invention relates to the technical field of power supplies, in particular to a level signal type on-off control circuit.
Background
With the increasing demand of space missions, the types of satellite-borne electric equipment are increasing, but the safety and reliability of the satellite are decreasing with the increase of the electric equipment. In order to ensure that the function, the performance and the safety and the reliability of the whole satellite are not influenced when a certain electric device breaks down, new requirements are provided for the switch controllability and the power-on time sequence of each electric device.
The on-board on-off instruction circuit is required to be an isolated control circuit, and most of the on-board on-off instruction circuit is a pulse instruction circuit. Some electrical equipment need use level signal type switching on and shutting down instruction circuit, when adopting comparator design switching on and shutting down instruction circuit, if do not design anti-interference function, the comparator receives single particle influence in the space environment, produces the corresponding function interrupt of electrical equipment that the malfunction caused easily. Even equipment damage can happen to the electric equipment with the time sequence requirement.
Under the condition that the number of on-board electronic devices is continuously increased, in order to reduce the power consumption of the whole satellite, when one electronic device is turned off, other electronic devices which are in cascade connection with the electronic device need to be turned off in time. When the whole satellite remote control signal resource is limited, the on-off control of each device can not be realized through a remote control instruction, the independent power utilization time sequence control and the on-off function control are required to be formed among a plurality of devices, and particularly, the effective power utilization time sequence control is required to be realized under the condition that multiple paths of output are not in common.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a level signal type on-off control circuit, which solves the problems that the conventional on-off instruction circuit cannot realize a power-on time sequence control function and is easily influenced by single particles in a space environment to generate misoperation so as to interrupt electronic equipment.
In order to achieve the purpose, the technical scheme of the invention is as follows:
the invention provides a level signal type on-off control circuit, comprising: a power-on timing control unit and a switching unit,
the power-on time sequence control unit is used for outputting a level signal to the switch unit and controlling the switching-on action or the switching-off action of the switch unit;
and the switch unit is used for receiving the level signal output by the power-on time sequence control unit and executing and completing a switching-on action or a switching-off action according to the level signal so as to realize power supply to a load. .
According to an aspect of the present invention, the power-on timing control unit includes: a first power-on level positive line, a first power-on level return line, a photoelectric coupler, an isolating diode, a first filter resistor, a first bleeder resistor, a first filter capacitor and a second bleeder resistor,
the anode of the isolation diode is connected with the leading power-on level positive line, and the cathode of the isolation diode is connected with the first end of the first filter resistor;
the second end of the first filter resistor is connected with the first end of the first bleeder resistor, the first end of the first filter capacitor and the first end of the photoelectric coupler,
the second end of the first bleeder resistor is connected with the second end of the first filter capacitor, the second end of the photoelectric coupler and the leading power-on level loop wire;
the first end of the second bleeder resistor is connected with the third end of the photoelectric coupler, and the second end of the second bleeder resistor is connected with the fifth end of the photoelectric coupler;
the optoelectronic coupler also includes a fourth end.
According to an aspect of the present invention, the level signal output from the power-on timing control unit is transmitted to the switching unit through the fourth and fifth terminals of the photo coupler,
and the fourth end and the fifth end of the photoelectric coupler are respectively a first output end and a second output end of the power-on time sequence control unit.
According to an aspect of the present invention, the switching unit includes: a positive line of a lagging power-on level, a loop of the lagging power-on level, a triode, a field effect tube, a first divider resistor, a second divider resistor, a third divider resistor, a fourth divider resistor, a fifth divider resistor, a sixth divider resistor, a seventh divider resistor, a second filter capacitor, a third filter capacitor, a vibration-proof resistor and a diode,
a first end of the first voltage-dividing resistor is connected with the hysteresis power-up level positive line, a first end of the second voltage-dividing resistor and a first end of the fifth voltage-dividing resistor, and a second end of the first voltage-dividing resistor is connected with a second end of the second voltage-dividing resistor, a first end of the third voltage-dividing resistor and a first output end of the power-up time sequence control unit;
a first end of the third voltage dividing resistor is connected with a second output end of the power-on time sequence control unit, and a second end of the third voltage dividing resistor is connected with a first end of the fourth voltage dividing resistor and a first end of the second filter resistor;
the second end of the fourth voltage-dividing resistor is connected with the second output end of the power-on time sequence control unit and the emitter of the triode;
the second end of the second filter resistor is connected with the first end of the second filter capacitor and the base electrode of the triode;
the second end of the second filter capacitor is connected with the hysteresis power-on level loop wire;
a collector of the triode is connected with the second end of the fifth voltage-dividing resistor, the first end of the sixth voltage-dividing resistor and the cathode of the diode;
the anode of the diode is connected with the hysteresis power-on level loop;
the second end of the sixth voltage-dividing resistor is connected with the first end of the seventh voltage-dividing resistor, the first end of the anti-oscillation resistor and the first end of the third filter capacitor;
the second end of the seventh divider resistor is connected with the hysteresis power-on level loop;
the second end of the second filter capacitor is connected with the hysteresis power-on level loop wire;
the second end of the oscillation-proof resistor is connected with the drain electrode of the field effect transistor;
and the grid electrode of the field effect transistor is connected with the hysteresis power-on level loop wire, and the source electrode of the field effect transistor is the output end of the switch unit.
According to one aspect of the invention, when the circuit is in the initial state, the switch unit is in the off state by inputting the high level through the positive line of the lagging power-on level, the triode is conducted, and the field effect tube is turned off.
According to an aspect of the present invention, when a high level is input through a leading power-on level positive line and a level signal is not input through a lagging power-on level positive line, a photocoupler of the power-on timing control unit is turned on, a triode of the switching unit is turned off, and a field effect transistor is turned on, so that the switching unit is turned on.
According to an aspect of the present invention, when a low level is inputted through a leading power-on level positive line, a photocoupler of the power-on timing control unit is turned off, a triode of the switching unit is turned on, and a field effect transistor is turned off, so that the switching unit is turned off.
Has the advantages that:
according to the scheme of the invention, the power-on time sequence control circuit and the level signal type instruction switching circuit are formed by the photoelectric coupler, the triode, the MOS tube and the peripheral circuits thereof, the level signal which is powered on first in the time sequence requirement is used as the control signal of the lagging power-on level, the self-adaptive power-on time sequence control function of two paths of power supplies which are not in common is realized, the power-on and power-off control is carried out without the remote control instruction of the whole satellite, and the problem of insufficient remote control resources under the condition that the electric equipment of the whole satellite, particularly the load equipment, is greatly increased can be solved.
According to one scheme of the invention, by adopting a complicated circuit structure of a photoelectric coupler and a triode to replace a relay or a voltage comparator for design, the defects that the reduction of the switching frequency of the relay is insufficient when an instruction frequently works under the condition of long-term work and the voltage comparator is easy to overturn and is unstable due to single particles under the condition of space environment irradiation are overcome, and the invention has the characteristics of high reliability and small size.
According to one scheme of the invention, when the on-off control function is realized by using the photoelectric coupler and the triode as core devices in the prior art, the state of the output end of the photoelectric coupler is used for carrying out state control on the base electrode of the triode, and because the output end of the photoelectric coupler is also a triode in nature, when the output end of the photoelectric coupler is in a low resistance state, the base electrode of the triode of the control circuit cannot be clamped to an effective low level, and the triode has the possibility of being conducted by mistake, so that the on-off function is unreliable. The invention designs a circuit for skillfully improving the reliability of the startup and shutdown function, namely, the output end of a photoelectric coupler is connected to the base of a control triode after voltage division is set, so that the base level of the triode is lower when the output end of the photoelectric coupler is low, the triode cannot be switched on, and the reliability of the startup function is improved.
Drawings
Fig. 1 is a schematic diagram showing a unit composition of a level signaling type on/off control circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram showing a specific configuration of a level signaling type switching control circuit according to an embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
The present invention is described in detail below with reference to the drawings and the specific embodiments, which are not repeated herein, but the embodiments of the present invention are not limited to the following embodiments.
Fig. 1 schematically shows a unit composition diagram of a level signal type switching control circuit according to the present embodiment. As shown in fig. 1, the level signaling type switching control circuit of the present embodiment mainly includes a power-on timing control unit 101 and a switching unit 102. The power-on timing sequence control unit 101 outputs a high level signal or a low level signal, and transmits the high level signal or the low level signal to the switch unit 102, so as to control the switch unit 102 to complete a turn-on action or a turn-off action. The switch unit 102 completes a corresponding turn-on action or turn-off action by receiving the level signal instruction output by the power-on timing sequence control unit 101, and supplies power to a load connected thereto. The novel control circuit is designed to be compatible with the power-on time sequence control unit 101 and the switch unit 102, can overcome the technical defect that the power-on time sequence control function cannot be realized by the conventional power-on and power-off circuit, simultaneously realizes the autonomous power-on time sequence control and the power-on and power-off function control of a plurality of onboard electric devices, and further realizes the power-on and power-off control function of the onboard electric devices through remote control instructions so as to adapt to the space environment with limited resources.
Fig. 2 is a schematic diagram showing a specific configuration of the level signal type switching control circuit according to the present embodiment. As shown in fig. 2, the power-on timing control unit 101 in the level signaling type switching control circuit specifically includes: the circuit comprises a leading power-up level positive line (or called a control level signal positive line), a leading power-up level return line (or called a control level signal return line), a photoelectric coupler U1, an isolation diode D1, a first filter resistor R7, a first bleeder resistor R8, a first filter capacitor C3 and a second bleeder resistor R9. The photocoupler U1 includes a first terminal 1, a third terminal 4, a second terminal 6, a fourth terminal 3, and a fifth terminal 5. The first end 1 and the second end 6 are respectively the anode and the cathode of a photodiode in the photoelectric coupler U1, and the third end 4, the fourth end 3 and the fifth end 5 are respectively the base (B pole), the emitter (E pole) and the collector (C pole) of a triode at the secondary side of the photoelectric coupler U1. Meanwhile, the fourth terminal 3 and the fifth terminal 5 of the photocoupler U1 are the first output terminal and the second output terminal of the power-on timing control unit 101, respectively.
The anode of the isolation diode D1 is connected to the first positive line of the power-on level, and the cathode of the isolation diode D1 is connected to the first end of the first filter resistor R7. The second end of the first filter resistor R7 is connected to the first end of the first bleeder resistor R8, the first end of the first filter capacitor C3, and the first end 1 of the photocoupler U1. A second end of the first bleeder resistor R8 is connected to a second end of the first filter capacitor C3, a second end 6 of the optocoupler U1, and the leading upper power level loop. The first end of the second bleeder resistor R9 is connected with the third end 4 of the photocoupler U1, and the second end of the second bleeder resistor R9 is connected with the fifth end 5 of the photocoupler U1.
The switch unit 102 in the level signal type on/off control circuit specifically includes: the power-on circuit comprises a hysteresis power-on level positive line (or called an input positive line), a hysteresis power-on level loop line (or called an input loop line), a triode Q1, a field effect transistor M1(MOS transistor), a first voltage-dividing resistor R1, a second voltage-dividing resistor R2, a third voltage-dividing resistor R10, a fourth voltage-dividing resistor R12, a fifth voltage-dividing resistor R3, a sixth voltage-dividing resistor R4, a seventh voltage-dividing resistor R6, a second filter resistor R11, a second filter capacitor C1, a third filter capacitor C2, an anti-oscillation resistor R5 and a diode Z1.
A first end of the first voltage-dividing resistor R1 is connected to the positive line of the delayed power-up level, a first end of the second voltage-dividing resistor R2 and a first end of the fifth voltage-dividing resistor R3, and a second end of the first voltage-dividing resistor R1 is connected to a second end of the second voltage-dividing resistor R2, a first end of the third voltage-dividing resistor R10 and a first output end of the power-up timing control unit 101. A first terminal of the third voltage dividing resistor R10 is connected to the second output terminal of the power-on timing control unit 101, and a second terminal of the third voltage dividing resistor R10 is connected to both a first terminal of the fourth voltage dividing resistor R12 and a first terminal of the first filter resistor R11. A second terminal of the fourth voltage-dividing resistor R12 is connected to the second output terminal of the power-on timing control unit 101 and an emitter (E-pole) of the transistor Q1. The second terminal of the second filter resistor R11 is connected to the first terminal of the second filter capacitor C1 and the base (B-pole) of the transistor Q1. A second terminal of the second filter capacitor C1 is connected to the hysteresis power-up level loop. A collector (C-pole) of the transistor Q1 is connected to the second terminal of the fifth voltage-dividing resistor R3, the first terminal of the sixth voltage-dividing resistor R4, and the cathode of the diode Z1. The anode of diode Z1 is connected to the hysteresis upper power level loop. The second end of the sixth voltage-dividing resistor R4 is connected to the first end of the seventh voltage-dividing resistor R6, the first end of the oscillation-preventing resistor R5, and the first end of the third filter capacitor C2. A second terminal of the seventh voltage dividing resistor R6 is connected to the hysteresis power-up level loop. A second terminal of the third filter capacitor C2 is connected to the hysteresis power-up level loop. The second end of the oscillation preventing resistor R5 is connected to the drain (D pole) of the fet M1. The gate (G pole) of the FET M1 is connected to the hysteresis up level loop, and the source (S pole) of the FET M1 is the output of the switch unit 102.
In the circuit shown in fig. 2 of the present embodiment, the hysteresis power-on level positive line of the switch unit 102 is connected to the base of the transistor Q1 through the filter circuit formed by the second filter resistor R11 and the second filter capacitor C1 after passing through the first voltage-dividing resistor R1, the second voltage-dividing resistor R2, the third voltage-dividing resistor R10 and the fourth voltage-dividing resistor R12, so as to control the transistor Q1 to be turned on or off under the action of the control signal of the level command of the power-on timing control unit. Meanwhile, the positive line of the lagging power-on level passes through the fifth voltage-dividing resistor R3, the sixth voltage-dividing resistor R4 and the seventh voltage-dividing resistor R6, passes through the third filter capacitor C2 and the oscillation-preventing resistor R5, and is connected to the gate of the fet M1, so as to control the fet M1 to be turned on or off, that is, to control whether the lagging power-on level is normally output. Here, the fet M1 is a switch of the switching unit 102, connects a load and supplies power to the load. The third filter capacitor C2 has a filtering function, so that the field effect transistor M1 is charged slowly, starting vibration is prevented, and the field effect transistor M1 can be protected. The function of the oscillation-proof resistor R5 can avoid voltage oscillation and current surge. In addition, the diode Z1 can prevent the gate voltage of the fet M1 from being too high, and can perform a voltage stabilizing function, thereby protecting the fet M1 from being damaged.
The power-on timing control unit 101 inputs a level signal through a leading power-on level positive line, the level signal passes through an isolation diode D1, the isolation diode is connected to the anode of a light emitting diode of a photoelectric coupler U1 after passing through a first filter resistor R7, a first bleeder resistor R8 and a first filter capacitor C3, the collector of a triode on the secondary side of the photoelectric coupler U1 is connected to the base of a triode Q1 after passing through a third voltage-dividing resistor R10 and a fourth voltage-dividing resistor R12, and the base of the triode Q1 is connected to a filter circuit formed by a second filter resistor R11 and a second filter capacitor C1, and the on or off of the triode Q1 is controlled. The isolation diode D1 is used to prevent the positive and negative electrodes at the input terminal of the power-on timing control unit 101 from being connected in reverse. The circuit formed by the first filter resistor R7, the first bleeder resistor R8 and the first filter capacitor C3 can filter out interference spike signals generated in the process of electrifying the leading electrifying level positive line, so as to avoid misconduction of the triode Q1, and further avoid misoperation of the switch unit 102. The filter circuit formed by the second filter resistor R11 and the second filter capacitor C1 can filter the level control signal or the unintentional interference signal in the level command output by the power-on timing control unit 101 for the switch unit 102, thereby improving the reliability of the switch unit 102 for receiving the control signal. In addition, two ends of the second bleeder resistor R9 are respectively connected to the base and the emitter of the triode on the secondary side of the photocoupler U1, so that the photocoupler U1 can be prevented from being damaged by static electricity, and the effect of protecting the photocoupler U1 is achieved.
When the circuit is in an initial state, in the process of establishing a voltage signal of a positive line of a lagging power-on level, that is, the switch unit 102 inputs a high level through the positive line of the lagging power-on level, passes through the voltage division circuit consisting of the first voltage division resistor R1 to the fourth voltage division resistor R12, then passes through the filter circuit and is connected to the base electrode of the triode Q1, and the voltage division resistor, the filter resistor and the filter capacitor are respectively provided with reasonable resistance values and capacitance values, so that the triode Q1 is conducted earlier than the field effect transistor M1. Since the collector of the transistor Q1 is connected to the gate of the fet M1, the first conduction of the transistor Q1 lowers the gate level of the fet M1, so that the fet M1 is turned off, i.e., the switching unit 102 is in the off state.
When the power-on timing control unit 101 inputs a high level through the leading power-on level positive line and does not input a level signal through the lagging power-on level positive line, a current passes through the light emitting diode side of the photoelectric coupler U1, so that a PN junction between the collector and the emitter of the triode on the secondary side of the photoelectric coupler U1 is conducted, the collector of the triode of the photoelectric coupler U1 is at a low level, and the level is a voltage drop of the PN junction. Then, the base voltage of the transistor Q1 is at a lower level by the third voltage dividing resistor R10 and the fourth voltage dividing resistor R12, so that the transistor Q1 cannot be turned on. At this time, the gate of the switching fet M1 is kept at a high level under the voltage dividing action of the positive line of the delayed power-on level, the switching fet M1 is turned on, and the delayed power-on level of the switch unit 102 is normally output, which provides a reliable power-on effect.
When the low level is input through the leading power-on level positive line, no current passes through the light emitting diode side of the photoelectric coupler U1 of the power-on timing control unit 101, so that the PN junction between the collector and the emitter of the triode on the secondary side of the photoelectric coupler U1 cannot be conducted, the collector of the triode of the photoelectric coupler U1 is in a high-resistance state, and under the action of the lagging power-on level positive line, the base voltage of the triode Q1 is in a high level, so that the conduction between the collector and the emitter of the triode Q1 is ensured, at this time, the gate level of the switching field effect transistor M1 is pulled down, the switching field effect transistor M1 cannot be conducted, and the lagging power-on level of the switching unit 102 has no output, so that the shutdown effect is achieved.
In summary, the level signal type switching control circuit of the present embodiment adopts a structural design composed of the photoelectric coupler U1 and its peripheral circuit, the triode Q1 and its peripheral circuit, and the driving peripheral circuit of the MOS transistor, and performs the selection of the types of the components of the peripheral circuits and the reasonable setting of the resistance-capacitance parameters, so as to realize the level signal type switching control function and the power-on timing control function, and has the characteristics of small volume, strong anti-interference capability, and high switching reliability. The comparator or relay structure of the existing switching circuit is replaced by the photoelectric coupler U1 and the triode Q1, so that the defects that the existing switching circuit is complex in structure, easy to malfunction and incapable of realizing the power-on time sequence control function are overcome.
(1) Realizing level instruction on-off function
The level control signal is connected to the input end of a photoelectric coupler U1, the output end of the photoelectric coupler U1 is connected with the B pole of a triode Q1, the C pole of the triode Q1 is connected to the driving G pole of an MOS (metal oxide semiconductor) tube, a main functional circuit is formed, and on-off control of the level signal is achieved.
The initial state: the input positive line is connected to the end B of the triode Q1 through a divider resistor, the electrode C of the triode Q1 is connected to the electrode G of the MOS tube, when an input bus gradually rises, the triode Q1 is preferentially switched on compared with the MOS tube through reasonable voltage division setting, the driving voltage of the MOS tube is reduced, at the moment, the MOS tube is in a turn-off state, a power link is in an open circuit state, and the power link is in a turn-off state.
And (3) starting up control: when the high level of the level control signal comes, the output end of the photoelectric coupler U1 is switched on at the moment to pull the B pole of the triode Q1 low, so that the triode Q1 is in a turn-off state, the CE of the triode Q1 is in a high-resistance state at the moment, the G pole level of the MOS tube is in a high level after the input positive line is subjected to voltage division, the MOS tube is switched on, and the load is started to normally work.
Shutdown control: when the level control signal is at a low level, the output end of the photoelectric coupler U1 is in a high-impedance state, that is, the B electrode of the triode Q1 is at a high potential, the CE of the triode Q1 is turned on, the G electrode of the MOS transistor is pulled down to a zero potential, the MOS transistor cannot be turned on, the power link is in an open-circuit state, and the load is shut down.
(2) Realizing power-on time sequence control function
When the load power-on sequence has requirements, the output level signal which is powered on preferentially is connected to the input end of the photoelectric coupler U1 to control whether the power-on output level lags or not, and due to the design of the photoelectric coupler U1, the power-on sequence control under the condition that two output power sources are not grounded can be realized.
When the high level is established by the level signal which requires the first power-on, the output end of the photoelectric coupler U1 is at the low level, the B pole of the triode Q1 in the time sequence control circuit of the later power-on level is pulled down, the C pole of the triode Q1 presents a high resistance state, the driving G pole of the MOS tube is at the high level, the MOS tube is switched on, and the high level is output after the power-on level is delayed.
When the level signal which is firstly electrified is converted into low level, the output end of the photoelectric coupler U1 is at high level, the B electrode of the triode Q1 is at high level, the triode Q1 is switched on, the C electrode is at low resistance state, the MOS tube drives the G electrode to be at low level, the MOS tube is switched off, and the level which is electrified later is not output.
The above description is only one embodiment of the present invention, and is not intended to limit the present invention, and it is apparent to those skilled in the art that various modifications and variations can be made in the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A level signaling type on/off control circuit, comprising: a power-on timing control unit (101) and a switch unit (102),
the power-on sequence control unit (101) is used for generating a level signal for controlling the on action or the off action of the switch unit (102);
the switch unit (102) is used for receiving the level signal output by the power-on sequence control unit (101) and executing a turn-on action or a turn-off action according to the level signal so as to supply power to a load.
2. The level signaling type switching control circuit according to claim 1, wherein the power-on timing control unit (101) comprises: a first power-on level positive line, a first power-on level return line, a photoelectric coupler (U1), an isolation diode (D1), a first filter resistor (R7), a first bleeder resistor (R8), a first filter capacitor (C3) and a second bleeder resistor (R9),
the anode of the isolation diode (D1) is connected with the leading power-on level positive line, and the cathode of the isolation diode (D1) is connected with the first end of the first filter resistor (R7);
the second end of the first filter resistor (R7) is connected with the first end of the first bleeder resistor (R8), the first end of the first filter capacitor (C3) and the first end (1) of the photoelectric coupler (U1),
a second terminal of the first bleeder resistor (R8) is connected to a second terminal of the first filter capacitor (C3), a second terminal (6) of the optocoupler (U1), and the leading power-up loop;
the first end of the second bleeder resistor (R9) is connected with the third end (4) of the photoelectric coupler (U1), and the second end is connected with the fifth end (5) of the photoelectric coupler (U1);
the photocoupler (U1) further includes a fourth end (3).
3. The level signaling type switching control circuit according to claim 2, wherein the level signal outputted from the power-on timing control unit (101) is transmitted to the switching unit (102) through the fourth terminal (3) and the fifth terminal (5) of the photocoupler (U1),
the fourth end (3) and the fifth end (5) of the photoelectric coupler (U1) are respectively a first output end and a second output end of the power-on sequence control unit (101).
4. The level signaling type switching power on/off control circuit according to claim 1, wherein said switching unit (102) comprises: a positive line of a hysteresis power-on level, a loop of the hysteresis power-on level, a triode (Q1), a field effect transistor (M1), a first voltage-dividing resistor (R1), a second voltage-dividing resistor (R2), a third voltage-dividing resistor (R10), a fourth voltage-dividing resistor (R12), a fifth voltage-dividing resistor (R3), a sixth voltage-dividing resistor (R4), a seventh voltage-dividing resistor (R6), a second filter resistor (R11), a second filter capacitor (C1), a third filter capacitor (C2), an anti-oscillation resistor (R5) and a diode (Z1),
a first end of the first voltage-dividing resistor (R1) is connected with the hysteresis power-up level positive line, a first end of the second voltage-dividing resistor (R2) and a first end of the fifth voltage-dividing resistor (R3), and a second end is connected with a second end of the second voltage-dividing resistor (R2), a first end of the third voltage-dividing resistor (R10) and a first output end of the power-up timing control unit (101);
a first end of the third voltage dividing resistor (R10) is connected with a second output end of the power-on sequence control unit (101), and a second end of the third voltage dividing resistor (R10) is connected with a first end of the fourth voltage dividing resistor (R12) and a first end of the second filter resistor (R11);
a second end of the fourth voltage-dividing resistor (R12) is connected with a second output end of the power-on sequence control unit (101) and an emitter of the triode (Q1);
the second end of the second filter resistor (R11) is connected with the first end of the second filter capacitor (C1) and the base electrode of the triode (Q1);
a second terminal of the second filter capacitor (C1) is connected to the hysteresis power-up level return line;
a collector of the triode (Q1) is connected with the second end of the fifth voltage-dividing resistor (R3), the first end of the sixth voltage-dividing resistor (R4) and the cathode of the diode (Z1);
the anode of the diode (Z1) is connected to the hysteresis upper power level loop;
a second end of the sixth voltage-dividing resistor (R4) is connected with a first end of the seventh voltage-dividing resistor (R6), a first end of the oscillation-preventing resistor (R5) and a first end of the third filter capacitor (C2);
a second end of the seventh voltage dividing resistor (R6) is connected to the hysteresis power-up level loop;
a second terminal of the third filter capacitor (C2) is connected to the hysteresis power-up level return line;
the second end of the oscillation-proof resistor (R5) is connected with the drain electrode of the field-effect transistor (M1);
the gate of the field effect transistor (M1) is connected to the hysteresis power-up level loop, and the source of the field effect transistor (M1) is the output of the switch unit (102).
5. The level signaling switching control circuit according to any one of claims 1 to 4, wherein when the circuit is in an initial state, the transistor (Q1) is turned on and the FET (M1) is turned off by a hysteresis power-up level positive line input high level, so that the switching unit (102) is in an off state.
6. The level signaling type on/off control circuit according to any one of claims 1 to 4, wherein when a high level is inputted through a leading power-up level positive line and a level signal is not inputted through a lagging power-up level positive line, the photocoupler (U1) of the power-up timing control unit (101) is turned on, the transistor (Q1) of the switching unit (102) is turned off, and the field effect transistor (M1) is turned on, so that the switching unit (102) is turned on.
7. The level signaling type on/off control circuit according to any one of claims 1 to 4, wherein when a low level is inputted through a leading power-up level positive line, the photocoupler (U1) of the power-up timing control unit (101) is turned off, the transistor (Q1) of the switching unit (102) is turned on, and the field effect transistor (M1) is turned off, so that the switching unit (102) is turned off.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111368734.1A CN114237092A (en) | 2021-11-18 | 2021-11-18 | Level signal type on-off control circuit |
| PCT/CN2022/115611 WO2023087840A1 (en) | 2021-11-18 | 2022-08-29 | Level signal-type startup and shutdown control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111368734.1A CN114237092A (en) | 2021-11-18 | 2021-11-18 | Level signal type on-off control circuit |
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| Publication Number | Publication Date |
|---|---|
| CN114237092A true CN114237092A (en) | 2022-03-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111368734.1A Pending CN114237092A (en) | 2021-11-18 | 2021-11-18 | Level signal type on-off control circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN114237092A (en) |
| WO (1) | WO2023087840A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023087840A1 (en) * | 2021-11-18 | 2023-05-25 | 北京卫星制造厂有限公司 | Level signal-type startup and shutdown control circuit |
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| WO2023087840A1 (en) | 2023-05-25 |
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