CN201248033Y

CN201248033Y - Sequence control circuit and television set with the circuit

Info

Publication number: CN201248033Y
Application number: CNU200820027228XU
Authority: CN
Inventors: 洪胜峰; 陈杰
Original assignee: Qingdao Hisense Electronics Co Ltd
Current assignee: Qingdao Hisense Electronics Co Ltd
Priority date: 2008-08-25
Filing date: 2008-08-25
Publication date: 2009-05-27
Anticipated expiration: 2018-08-25

Abstract

The utility model discloses a sequential control circuit and a TV with the sequential control circuit. The sequential control circuit comprises N switching circuits, N storage capacitors, and N sequential signal output ends, and the N is a natural number, wherein one end of a switching channel of the Nth switching circuit is connected with a DC supply, and the other end is connected with the anode of the Nth storage capacitor on the one hand, is connected with the Nth sequential signal output end and is connected with the control end of the next switching circuit on the other hand, and the control end of the first switching circuit receives main control signals. The utility model realizes the sequential assurance function by using a simple hardware circuit structure, overcomes the defects of easy disturbed property and low reliability of the prior software program method, and can effectively ensure the accuracy of the sequence of the control signals for the special conditions of software failure or sudden power-fail, and the like, thereby ensuring that a rear end system can not be damaged by the error action to cause the stability and the reliability of the integral operation to be improved.

Description

Sequential control circuit and have the television set of described circuit

Technical field

The utility model belongs to the power circuit technical field, specifically, relates to a kind ofly to guarantee that multiple power supplies powers on, the sequencing of power down and the control circuit in the time interval and television set with this sequential control circuit.

Background technology

In existing system for TV set, generally all comprise power panel, signal plate, logic card and display screen.Wherein, the powersupply system on the power panel can be exported polytype power supply, to realize the power supply to signal plate, logic card, display screen.Specifically, 15V, A5V, the 12V power supply of power panel output is the signal plate power supply, the power supply of M5V is the logic card power supply, and the power supply of VS (for the X of display screen, the power supply of Y drive plate), VA (for the addressing circuit plate power supply of display screen) is the display screen power supply.In the television set actual moving process, requirement according to display screen, wait until that the M5V power supply is that logic card supplies power to steady operation and could allow VS, the VA power supply be display screen power supply after a period of time, such as 1.2 seconds～5 seconds, the needed concrete time is according to the difference of display screen and different, otherwise the phenomenon that may occur burning screen or damage components and parts.

For example: when needs realize that sequential shown in Figure 1 requires, the most frequently used method is at first to use circuit structure shown in Figure 2 to carry out hardware to guarantee at present, and then the method that adopts software programming to power on blanking time Ton and power down Toff blanking time carry out software control, successively and blanking time promptly, to prevent causing equipment malfunction work or destroyed because of the sequential entanglement by programming decision sequential.

Among Fig. 1, Fig. 2, RL_ON, VS_ON are the two path control signal of CPU to power panel output, and its high-low level state is by software control; Wherein, the work schedule of RL_ON control 15V, A5V, 12V, M5V power supply, the work schedule of VS_ON control VS, VA power supply.When television set interchange start powers on the standby startup, need send high level RL_ON and VS_ON control signal respectively to power panel according to Ton time requirement usually, power on successively with control follow-up signal plate, logic card and display screen; At ac dump with when entering holding state, then need respectively two control signals be become low level according to Toff time requirement, control the power down successively of follow-up signal plate, logic card and display screen with this.

But, above-mentioned software control method control chip (such as the CPU among Fig. 2) be interfered or impaired situation under will lose efficacy.That is to say that if control chip has damaged, then electrifying timing sequence will entanglement, this certainly will will cause display screen cisco unity malfunction even damage.

The utility model content

The utility model carries out the low problem of control reliability in order to solve the existing software program method that adopts to the power supply electrifying sequential, a kind of technology of the power supply electrifying sequential being controlled by the hardware circuit realization is provided, when special circumstances such as software failure, power down suddenly take place, can guarantee the correctness of control signal sequential effectively, guarantee that back-end system does not cause damage because of misoperation.

For solving the problems of the technologies described above, the utility model is achieved by the following technical solutions:

A kind of sequential control circuit comprises N path switching circuit, N road storage capacitor and N road clock signal output, and N is a natural number; Wherein, switch ways one end of N path switching circuit connects DC power supply, the other end connects the positive pole of N road storage capacitor on the one hand, and be connected with N road clock signal output, connect the control end of back one path switching circuit on the other hand, the control end of first via switching circuit then receives main control signal.

For the waveform of timing control signal to output carries out shaping, in described sequential control circuit, also include N road comparator, wherein, the positive pole of N road storage capacitor connects wherein one road input of N road comparator, another road input of described comparator connects reference voltage, and output connects N road clock signal output.

Further, the positive pole of described N road storage capacitor connects the in-phase input end of N road comparator, and the inverting input of described N road comparator connects the dividing potential drop node of bleeder circuit, exports described reference voltage by the dividing potential drop node of bleeder circuit.

Further again, in described N path switching circuit, include a NPN type triode respectively, wherein, the collector electrode of the NPN type triode in the N path switching circuit connects described DC power supply, emitter connects N road storage capacitor, and links to each other with the base stage of the NPN type triode of back in one path switching circuit; The base stage of the NPN type triode in the first via switching circuit then receives described main control signal.

Preferably, described N equals 2.In order to realize sequential requirement shown in Figure 1, described main control signal connects first via clock signal output through first switching diode, and the positive pole of described first via storage capacitor directly connects or passes through first via comparator connection first via clock signal output through the second switch diode; Described the second road clock signal output is through pull down resistor ground connection.

Further again, the anodal one side of described the second road storage capacitor is through the bleed off grounding through resistance, the negative electrode that connects the 3rd switching diode on the other hand, the anode of described the 3rd switching diode directly connects or connects the second road clock signal output by the second road comparator.

Based on above-mentioned sequential control circuit structure, the utility model provides a kind of television set with this sequential control circuit again, described sequential control circuit is connected between the controller and power panel of television set, described controller only need be exported one road main control signal, can obtain the different control signal of multichannel sequential by described sequential control circuit, export in the power panel with output time and control the multiple-way supply power supply of its generation, and then satisfy the follow-up signal plate, logic card and display screen power on to power supply, the different requirements in the sequencing of power-off sequential and the time interval, and then make that each operational module in the television set can operate as normal.

Compared with prior art, advantage of the present utility model and good effect are: the simple hardware circuit of the utility model utilization has been realized the sequential assurance function, overcome the defective that existing software program method is subject to disturb, reliability is low, for the correctness that when special circumstances such as software failure or power down suddenly take place, can both guarantee the control signal sequential effectively, thereby guaranteed that back-end system can not make the stability and the reliability of complete machine operation be improved because of misoperation damages.

After reading the detailed description of the utility model execution mode in conjunction with the accompanying drawings, other characteristics of the present utility model and advantage will become clearer.

Description of drawings

Fig. 1 is the oscillogram of the required timing control signal of power panel in the television set;

Fig. 2 is the theory diagram of the hardware circuit in the existing television set;

Fig. 3 is a kind of television set hardware circuit principle block diagram of the utility model for realizing that waveform shown in Figure 1 proposes;

Fig. 4 is the circuit theory diagrams of wherein a kind of embodiment of sequential control circuit among Fig. 3;

Fig. 5 is the portion waveshape figure by the timing control signal of sequential control circuit output shown in Figure 4;

Fig. 6 is the circuit theory diagrams of another embodiment of sequential control circuit among Fig. 3.

Embodiment

Below in conjunction with accompanying drawing embodiment of the present utility model is described in detail.

The utility model is write the design that software program comes the desired multichannel timing control signal of output system by abandoning existing the employing in controller, and adopt the method that hardware is set up sequential control circuit to generate described timing control signal, and then fundamentally avoided software program method to be subject to disturb losing efficacy and, effectively promoted the stability and the reliability of system's operation the adverse effect that the system module circuit causes.

In order to satisfy the output requirement of multichannel timing control signal, in described sequential control circuit, be provided with N path switching circuit, N road storage capacitor and N road clock signal output, wherein, N is a natural number, and concrete numerical value can equal the number of the required timing control signal of system.The switch ways of N path switching circuit is connected between the positive pole of DC power supply and N road storage capacitor, utilize the control end of first via switching circuit to receive the main control signal that controller is exported, the control end of follow-up switching circuit then connects the positive pole of last road storage capacitor.After device power-up, main control signal control first via switching circuit conducting by controller output, and then DC power supply is charged to first via storage capacitor, when the cathode voltage of first via storage capacitor rises to the conducting voltage of the second path switching circuit control end, control the second path switching circuit conducting, and then charge to the second road storage capacitor by DC power supply; When the cathode voltage of the second road storage capacitor rises to the conducting voltage of Third Road switching circuit control end, then make the controlled conducting of Third Road switching circuit, to realize the charging of DC power supply, by that analogy to the Third Road storage capacitor.Like this, by N road clock signal output is connected with the positive pole of N road storage capacitor, can export the timing control signal that N road electrifying timing sequence lags behind successively by N road clock signal output, to satisfy control requirement to the subsequent module circuit.

Be example with the TV set circuit below, specifically set forth the composition structure of described sequential control circuit.

Embodiment one, for its required two-way timing control signal is provided to the TV set power plate, present embodiment has designed a sequential control circuit between the CPU of television set and power panel, as shown in Figure 3, described sequential control circuit receives the main control signal P_CTRL of CPU output, and then generation two-way timing control signal RL_ON, VS_ON export power panel to, the output timing of the multiple-way supply power supply that generates with the control power panel satisfies follow-up signal plate, logic card and display screen to the sequencing of multiple-way supply power supply electrifying and power down and the different requirements in the time interval.

Fig. 4 is wherein a kind of composition structure of described sequential control circuit, comprises double switch circuit and two-way storage capacitor C1, C2.In the present embodiment, the double switch circuit can specifically adopt two-way NPN type triode Q1, Q2 to realize.Wherein, the base stage of first via NPN type triode Q1 connects CPU by current-limiting resistance R2, receive the main control signal P_CTRL of its output, collector electrode connects DC power supply VCC by the current-limiting resistance R1 of series connection, emitter is on the one hand through first via storage capacitor C1 ground connection, the anode that connects second switch diode D2 on the other hand, and then the negative electrode by second switch diode D2 connects first via timing control signal output, output timing control signal RL_ON.For the rising edge that makes described timing control signal RL_ON vertical, between first via timing control signal output and CPU, be connected with the first switching diode D1, when the main control signal P_CTRL of CPU output is high level, can make timing control signal RL_ON moment rise to high level state.

In order to control second path switching circuit time-delay conducting, the base stage of the second road NPN type triode Q2 is connected to the positive pole of first via storage capacitor C1 by current-limiting resistance R3, its collector electrode connects DC power supply VCC by the current-limiting resistance R4 of series connection, emitter connects the positive pole of the second road storage capacitor C2 on the one hand through the 3rd switching diode D3, the minus earth of the second road storage capacitor C2, connect the second road timing control signal output on the other hand, output timing control signal VS_ON.For the trailing edge that makes described timing control signal VS_ON vertical, between the second road timing control signal output and ground, be connected with pull down resistor R5, the second road NPN type triode Q2 by the time, current potential moment of timing control signal VS_ON can be pulled down to ground.At this moment, the timely bleed off over the ground of the bleed off resistance R 6 that the electric charge among the second road storage capacitor C2 can be by being connected in parallel on its two ends.

Elaborate the concrete course of work of above-mentioned sequential control circuit below: when television system powers on, the main control signal P_CTRL of CPU output becomes high level by low level, through and control the first switching diode D1 forward conduction, will be set to high level by the RL_ON timing control signal of first timing control signal output output.At this moment, though triode Q1 enters the saturation conduction state, because the existence of first via storage capacitor C1, the anode voltage of second switch diode D2 can not suddenly change, and therefore, second switch diode D2 is cut off.

When first via storage capacitor C1 charges to the conducting voltage of triode Q2 by 0V, the controlled conducting of triode Q2, the second road storage capacitor C2 enters charged state.The rising gradually of going up voltage along with the second road storage capacitor C2, the also corresponding raising of level of the timing control signal VS_ON by the output of the second timing control signal output, until rising to high level, i.e. the second road storage capacitor C2 charging finishes.When having realized powering on thus, the rising delay of timing control signal VS_ON is after RL_ON.Its blanking time Ton of powering on can determine by the parameter value of regulating current-limiting resistance R1, first via storage capacitor C1, current-limiting resistance R4, the second road storage capacitor C2.

As the main control signal P_CTRL of CPU output during by high step-down, because first via storage capacitor C1 is in and is full of electricity condition, so second switch diode D2 conducting, the first switching diode D1 ends simultaneously.At this moment, timing control signal RL_ON can continue to remain on high level state because of the slow discharge of first via storage capacitor C1, finishes just to become low level up to discharge.Meanwhile, the base voltage of triode Q2 can reduce along with the discharge of first via storage capacitor C1, and Q2 enters cut-off state up to triode.After triode Q2 ends, the anode voltage of the 3rd switching diode D3 is put low because of the existence of pull down resistor R5, its cathode voltage then is in higher level owing to the second road storage capacitor C2 has been full of electricity, therefore, the 3rd switching diode D3 oppositely ends, the current potential of timing control signal VS_ON is pulled down to ground by pull down resistor R5, and the electric charge among the second road storage capacitor C2 is by the timely over the ground bleed off of bleed off resistance R 6.Wherein, power down Toff blanking time can regulate by the capacitance that changes first via storage capacitor C1.

When system's sudden power, the main control signal P_CTRL of CPU output is by high step-down, and simultaneously, DC power supply VCC is also with very fast disappearance, the sequential of timing control signal RL_ON and VS_ON will keep with above-described consistent, thereby the output timing when guaranteeing power down can entanglement.

Consider that this sequential control circuit produces the delay principle by capacitor charge and discharge and realizes that because the late effect of electric capacity, the last electrical waveform of the power down of timing control signal RL_ON and VS_ON will be as shown in Figure 5.

Therefore, if when the receiving terminal of power panel has strict demand to the rising edge of the timing control signal of input and trailing edge, then this waveform will not satisfy the needs of rear end input.At this moment, can on the two-way timing control signal output of this circuit, further connect comparator again and come the timing control signal RL_ON of its output and the waveform of VS_ON are put in order, as shown in Figure 6.

Two-way timing control signal output is connected with the in-phase input end of two-way analog comparator U1A, U1B respectively, the inverting input of two-way analog comparator U1A, U1B connects reference voltage, and output is exported required timing control signal RL_ON and VS_ON respectively.Described reference voltage can provide by bleeder circuit, and as shown in Figure 6, the resistance pressure-dividing network output that can adopt two divider resistance R7, R8 to form provides.Described resistance pressure-dividing network one end connects DC power supply VCC, other end ground connection, and its dividing potential drop node connects the inverting input of two-way analog comparator U1A, U1B, is determined the size of described reference voltage by the ratio of divider resistance R7, R8.Like this, timing control signal RL_ON and the VS_ON by two-way analog comparator U1A, U1B output can reach waveform state shown in Figure 1.

The utility model has been realized the sequential assurance function by adopting above-mentioned simple circuit configuration; guaranteed that the power-on time of television display screen is later than the power-on time of signal plate and logic card all the time; the power down time of display screen is then all the time early than power down time of signal plate and logic card; so just fundamentally avoided burning the generation of screen or the inner components and parts phenomenon of damage display screen; remedied the existing many disadvantages of software program method; whenever can both guarantee the correctness of control signal sequential, make back-end system be able to effective protection.

Certainly, above-mentioned sequential control circuit also can be applied to except that television set other and require in the electric equipment of timing control signal, switching circuit wherein also can adopt other components and parts with on-off action or integrated chip to realize that the utility model does not specifically limit this.

Should be understood that; the above only is a kind of preferred implementation of the present utility model; for those skilled in the art; under the prerequisite that does not break away from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection range of the present utility model.

Claims

1, a kind of sequential control circuit is characterized in that: comprise N path switching circuit, N road storage capacitor and N road clock signal output, N is a natural number; Wherein, switch ways one end of N path switching circuit connects DC power supply, the other end connects the positive pole of N road storage capacitor on the one hand, and be connected with N road clock signal output, connect the control end of back one path switching circuit on the other hand, the control end of first via switching circuit then receives main control signal.

2, sequential control circuit according to claim 1, it is characterized in that: in described sequential control circuit, also comprise N road comparator, wherein, the positive pole of N road storage capacitor connects wherein one road input of N road comparator, another road input of described comparator connects reference voltage, and output connects N road clock signal output.

3, sequential control circuit according to claim 2, it is characterized in that: the positive pole of described N road storage capacitor connects the in-phase input end of N road comparator, the inverting input of described N road comparator connects the dividing potential drop node of bleeder circuit, exports described reference voltage by the dividing potential drop node of bleeder circuit.

4, sequential control circuit according to claim 1, it is characterized in that: in described N path switching circuit, include a NPN type triode respectively, wherein, the collector electrode of the NPN type triode in the N path switching circuit connects described DC power supply, emitter connects N road storage capacitor, and links to each other with the base stage of the NPN type triode of back in one path switching circuit; The base stage of the NPN type triode in the first via switching circuit then receives described main control signal.

5, according to each described sequential control circuit in the claim 1 to 4, it is characterized in that: described N equals 2; Wherein, described main control signal connects first via clock signal output through first switching diode, and the positive pole of described first via storage capacitor directly connects or passes through first via comparator connection first via clock signal output through the second switch diode; Described the second road clock signal output is through pull down resistor ground connection.

6, sequential control circuit according to claim 5, it is characterized in that: the anodal one side of described the second road storage capacitor is through the bleed off grounding through resistance, the negative electrode that connects the 3rd switching diode on the other hand, the anode of described the 3rd switching diode directly connects or connects the second road clock signal output by the second road comparator.

7, a kind of television set comprises controller and power panel, it is characterized in that: be connected with sequential control circuit between described controller and power panel; Comprise N path switching circuit, N road storage capacitor and the N road clock signal output that is connected with described power panel in described sequential control circuit, N is a natural number; Wherein, switch ways one end of N path switching circuit connects DC power supply, the other end connects the positive pole of N road storage capacitor on the one hand, and be connected with N road clock signal output, export N road timing control signal to power panel, the control end that connects back one path switching circuit on the other hand, the control end of first via switching circuit then receive the main control signal of described controller output.

8, television set according to claim 7, it is characterized in that: in described sequential control circuit, also comprise N road comparator, wherein, the positive pole of N road storage capacitor connects wherein one road input of N road comparator, another road input of described comparator connects reference voltage, and output connects N road clock signal output.

9, television set according to claim 7, it is characterized in that: in described N path switching circuit, include a NPN type triode respectively, wherein, the collector electrode of the NPN type triode in the N path switching circuit connects described DC power supply, emitter connects N road storage capacitor, and links to each other with the base stage of the NPN type triode of back in one path switching circuit; The base stage of the NPN type triode in the first via switching circuit then receives the main control signal of described controller output.

10, according to each described television set in the claim 7 to 9, it is characterized in that: described N equals 2; Wherein, the main control signal output of described controller connects first via clock signal output through first switching diode, and the positive pole of described first via storage capacitor directly connects or passes through first via comparator connection first via clock signal output through the second switch diode; The anodal one side of described the second road storage capacitor connects the second road clock signal output through the direct connection of the 3rd switching diode or by the second road comparator on the other hand through the bleed off grounding through resistance; Described the second road clock signal output is through pull down resistor ground connection.