CN111211602A - Super capacitor charge-discharge module, charge-discharge method and power terminal - Google Patents
Super capacitor charge-discharge module, charge-discharge method and power terminal Download PDFInfo
- Publication number
- CN111211602A CN111211602A CN202010147524.9A CN202010147524A CN111211602A CN 111211602 A CN111211602 A CN 111211602A CN 202010147524 A CN202010147524 A CN 202010147524A CN 111211602 A CN111211602 A CN 111211602A
- Authority
- CN
- China
- Prior art keywords
- charging
- circuit
- super capacitor
- discharge
- power failure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/007—Regulation of charging or discharging current or voltage
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
- H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Stand-By Power Supply Arrangements (AREA)
Abstract
The invention relates to a super capacitor charge-discharge module, a charge-discharge method and a power terminal. A super capacitor charge-discharge module comprises: the charging circuit, the super capacitor bank, the discharging circuit and the power failure detection circuit are connected in series; the charging circuit and the discharging circuit are respectively connected with the super capacitor bank; the charging circuit is connected with a charging power supply and charges the super capacitor bank; the power failure detection circuit is respectively connected with the charging power supply and the discharging circuit. Compared with the prior art, the super capacitor charge-discharge module, the charge-discharge method and the power terminal provided by the invention have the following advantages: 1. after the conversion of the boost chip, the level of the power supply output process is constant, and the condition of linear voltage drop does not exist; 2. the boost chip is based on the control of the power failure signal of the power failure detection circuit, and can realize that the farad capacitor module is only charged without boosting and discharging when normally powered on based on the module, and the system automatically starts boosting and outputting after power failure without software participation.
Description
Technical Field
The invention relates to the field of electricity, in particular to a super capacitor charge-discharge module, a charge-discharge method and a power terminal.
Background
The conventional super capacitor standby power scheme in the field of distribution networks adopts linear charging and discharging after high-capacity farad capacitor series, parallel and parallel combination, and also adopts a mode of outputting the farad capacitor series, parallel and parallel combination through a boost chip. The first linear discharging mode has the problems that voltage is unstable in the discharging process and is in a linear descending trend, the discharging voltage interval of the farad capacitor module is limited due to the limitation of the working voltage threshold value of a power chip of a rear-stage system, the capacity utilization rate of the single farad capacitor is low, and the actual occupied space of the whole module is large. In the second mode, the risk of untimely control due to uncontrolled boosting process or application software intervention, program disorder and out of control exists. The boosting chip output mode has the problems that the boosting chip works abnormally due to the fact that the leakage current of the anti-reverse-filling diode in the rear-stage circuit exceeds the allowable value of the boosting chip under a specific working condition (such as high temperature of 75 ℃), so that a farad capacitor cannot be charged normally, a front-end current limiting resistor is always in the maximum overcurrent state, and finally a printed board is burnt out, blacked and the like.
The patent document with the patent number ZL201710673780.X discloses a power failure reporting implementation method and circuit for power consumption information acquisition equipment, and the power failure detection method is characterized in that a communication module detects power supply voltage of an ammeter and a zero-crossing signal of a power grid to judge a power failure state; the circuit scheme comprises a charging circuit, a farad capacitor, a booster circuit and a power failure detection and control circuit. The charging circuit is connected with an input voltage VDD; the output of the charging circuit is connected with a farad capacitor; the input of the booster circuit is connected with a farad capacitor; and the power failure detection and control circuit is respectively connected with the charging circuit and a 4-pin EN of U1 of the booster circuit. The invention provides a power failure reporting circuit which is applicable to a communication module and has the advantages of simple circuit structure, low cost, high reliability and complete functions. However, the power failure detection is mainly to report the power failure information of the terminal, and thus the power supply output of the super capacitor is not controlled, so that the above problem still exists.
Therefore, the existing super capacitor charging and discharging technology has defects and needs to be improved.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a super capacitor charge-discharge module, a charge-discharge method, and a power terminal, which can solve the technical problems mentioned in the background art.
In order to achieve the purpose, the invention adopts the following technical scheme:
a super capacitor charge-discharge module comprises: the charging circuit, the super capacitor bank, the discharging circuit and the power failure detection circuit are connected in series; the charging circuit and the discharging circuit are respectively connected with the super capacitor bank; the charging circuit is connected with a charging power supply and charges the super capacitor bank; the power failure detection circuit is respectively connected with the charging power supply and the discharging circuit.
Preferably, the super capacitor charge-discharge module, the power down detection circuit includes: a power failure detection chip and an inverse logic switch; the input end of the power failure detection chip is connected with the charging power supply, the output end of the power failure detection chip is connected with the inverse logic switch, and the inverse logic switch is connected with the discharging circuit.
Preferably, the discharge circuit of the super capacitor charge-discharge module comprises a discharge inductor and a boost chip; the boosting chip is connected with the discharge end of the super capacitor bank through the discharge inductor; the output end of the detection switch is connected with the enabling end of the boosting chip after being inverted in logic; the boost chip supplies power to the outside.
Preferably, in the super capacitor charge-discharge module, the inverse logic switch is an NPN triode, a base of the NPN triode is connected to the output end of the power-down detection chip, and a collector of the NPN triode is connected to the enable end of the boost chip.
Preferably, in the super capacitor charge and discharge module, the type of the boost chip is TPS61089 or SGM 6610.
In the preferable super capacitor charge-discharge module, the power failure detection chip is R3111H421A-T1-F in model number.
Preferably, the charging circuit of the super capacitor charging and discharging module comprises a charging switch, a charging voltage stabilizer and a charging isolator; one end of the charging isolator is connected with a charging power supply, and the other end of the charging isolator is connected with the charging switch; one end of the charging voltage stabilizer is connected with the super capacitor bank, and the other end of the charging voltage stabilizer is connected with the charging switch; and the charging switch is respectively connected with the charging end of the super capacitor bank.
Preferably, the super capacitor charging and discharging module is configured such that the super capacitor bank includes a plurality of farad capacitors; the plurality of farad capacitors are arranged in series or in parallel or in series-parallel.
A super capacitor charging and discharging method applying the super capacitor charging and discharging module is characterized by comprising the following steps:
the power failure detection circuit detects whether a charging voltage exists in a charging power supply in real time, if yes, the power failure detection circuit sends a voltage storage signal to the discharge circuit, and the discharge circuit does not supply power to the outside; if not, the power failure detection circuit sends a power failure signal to the discharge circuit, and the discharge circuit supplies power to the outside.
The power terminal is provided with the super capacitor charge-discharge module as a backup power supply, and the power failure detection circuit is also connected with the working voltage of a terminal system.
Compared with the prior art, the super capacitor charge-discharge module, the charge-discharge method and the power terminal provided by the invention have the following advantages:
1. after the conversion of the boost chip, the level of the power supply output process is constant, and the condition of linear voltage drop does not exist;
2. the boost chip is based on the control of a power failure signal of the power failure detection circuit, and can realize that the farad capacitor module is only charged without boosting and discharging when normal power is available based on the module, and the boost output is automatically started after the system is powered down without software participation;
3. the situation that the boost chip works abnormally due to excessive leakage current of a subsequent circuit, the farad capacitor module cannot be fully charged, and a printed board is burnt out due to overheating of a front-end current limiting resistor is avoided under a specific working environment (such as high temperature of 75 ℃) after the boost chip is enabled and controlled.
Drawings
Fig. 1 is a block diagram of the structure of the super capacitor charge-discharge module provided by the invention;
FIG. 2 is a circuit diagram of a power down detection circuit provided by the present invention;
fig. 3 is a voltage output state diagram of the middle super capacitor charge-discharge module in the discharge phase according to the present invention;
fig. 4 is a circuit diagram of the super capacitor charge-discharge module provided by the invention.
Detailed Description
In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Example 1
Referring to fig. 1-3 together, in fig. 2 and 4, the same designations in the various circuit diagrams as connected together at connections are conventional representations of the connections of circuit diagrams in the art. The invention provides a super capacitor charge-discharge module, comprising: the charging circuit 1, the super capacitor group 2, the discharging circuit 3 and the power failure detection circuit 4; the charging circuit 1 and the discharging circuit 3 are respectively connected with the super capacitor bank 2; the charging circuit 1 is connected with a charging power supply and charges the super capacitor bank 2; the power failure detection circuit 4 is respectively connected with the charging power supply and the discharging circuit 3.
As a preferred scheme, in this embodiment, the charging circuit 1 includes a charging switch, a charging regulator, and a charging isolator; one end of the charging isolator is connected with a charging power supply, and the other end of the charging isolator is connected with the charging switch; one end of the charging voltage stabilizer is connected with the super capacitor group 2, and the other end of the charging voltage stabilizer is connected with the charging switch; and the charging switch is respectively connected with the charging end of the super capacitor group 2. Specifically, referring to fig. 4, the charge switch is preferably an NPN transistor V1; the charging voltage stabilizer is preferably a voltage stabilizing diode V2 with the model of AZ 431; the charge isolator is preferably an isolation diode V3.
Preferably, in this embodiment, the discharge circuit 3 includes a discharge inductor L1 and a boost chip U1; the boosting chip U1 is connected with the discharge end of the super capacitor bank 2 through the discharge inductor L1; the boost chip U1 supplies power to the outside through the VOUT end. Specifically, the preferable model of the boost chip U1 is TPS61089 or SGM 6610.
Specifically, in this embodiment, a super capacitor group 2 formed by two farad capacitors connected in series is taken as an example to describe in detail, as shown in fig. 4, the working principle of the super capacitor charge-discharge module provided by the present invention is briefly described as follows: VIN is a charging level, that is, VIN is connected to the charging power supply to supply power to the charging circuit 1, and is usually 5V, 12V, and the like; VOUT is the external output level of the discharge circuit 3, which is usually 12V, 9.5V, etc. CTRL of the EN terminal of the boost chip U1 is an enable pin control signal of the boost chip U1 (the control signal is expressed by high and low of a level and is used conventionally by the boost chip U1). In a specific implementation, the boost chip is used in a conventional manner in the art, that is, according to the manual description, when the control signal is 0, the boost chip U1 is disabled, and when the control signal at CTRL is pulled high (less than 7V), the boost chip U1 is enabled, and normal operation is started.
As shown in fig. 3, it is assumed that at time 0, the super capacitor bank 2 is already in a fully charged state, at time t0, the power down moment is the power down moment, and 0 to t0 are the system power on situation, at which time the boost chip U1 cannot normally operate and has no output. When the system power failure occurs at the time of t0, the boost chip U1 is enabled to start normal operation at the time, t 0-t 1 are the normal operation output time of the boost chip, and when the time is more than t1, the voltage of the super capacitor U1 is lower than the minimum allowable operating voltage of the boost chip U1, the boost chip U1 cannot normally operate any more, and the output is zero. The beneficial effect of this is shown in fig. 3, which ensures that the output voltage of the super capacitor group 2 is kept constant in the whole discharging process, and simultaneously improves the utilization rate of the voltage capacity space of the individual farad capacitor in the super capacitor group 2.
As a preferable solution, in this embodiment, the power failure detection circuit 4 includes: a power-down detection chip V8 and an inverse logic switch V7; the input end of the power failure detection chip V8 is connected with the charging power supply, the output end of the power failure detection chip V8 is connected with the inverse logic switch V7, the inverse logic switch V7 is connected with the discharging circuit 3, and the output end of the inverse logic switch V7 is connected with the enabling end of the boosting chip U1 after being inverted in logic. Preferably, the power down detection chip V8 has a model of R3111H 421A.
Preferably, in this embodiment, the inverse logic switch V7 is an NPN transistor, a base of the NPN transistor is connected to the power-down detection chip, and a collector of the NPN transistor is connected to the voltage boost chip. The inverse logic connection is used for unconventional use of the triode, under the normal condition, an output signal of the triode is output by an emitter, but the emitter of the triode is grounded, a collector serves as an output signal position, and the inverse logic output of the signal can be realized, namely, a high level is input from a base, the collector outputs a low level, and a low level is input from the base, and the collector outputs a high level.
By combining the power failure detection circuit 4 shown in fig. 2 to perform inverse logic, it can be realized that when the system is powered, that is, when VIN has power access, the power failure detection circuit 4 outputs a low level signal to the EN pin of the boost chip U1 through the output terminal CTRL, the boost chip U1 is disabled, the boost chip U1 does not work, and the super capacitor bank is only charged and is not discharged. When a system is powered off, namely when VIN does not have power access, the power failure detection circuit 4 outputs a high level signal to an EN pin of the boost chip U1 through an output terminal CTRL, the boost chip U1 is enabled to start normal operation, at this time, the super capacitor bank 2 starts to supply power to the outside, and power supply voltage is boosted by the boost chip U1 and then is normally output. The logic circuit formed by the power failure detection chip and the discrete devices plays a key role, and can realize automatic seamless switching of power failure. Meanwhile, referring to fig. 2 again, after the super capacitor charging and discharging module is connected to the power terminal, the power failure detection circuit 4 is further connected to the power terminal system voltage through the VSys connection line in fig. 2, so that the detection accuracy of whether the charging voltage exists can be improved. Correspondingly, the power failure detection circuit 4 may also be connected to a processor in the power terminal through a CAP _ CTRL connection line in fig. 2, and is configured to receive a control signal sent by the processor, and directly control whether the boost chip U1 is enabled or not through the CTRL connection line, which is a case where there is a certain delay and instability in a software control manner of an upper computer processor after the power failure detection circuit 4 is deactivated, so that a common method of the present invention is to implement detection through the structure of the power failure detection circuit 4 and drive whether the boost chip U1 is enabled or not.
Preferably, in this embodiment, the super capacitor bank 2 includes a plurality of farad capacitors; the plurality of farad capacitors are arranged in series or in parallel or in series-parallel. It should be noted that the installation manner of the plurality of farad capacitors in series or in parallel or in series-parallel is a common installation manner in the art, and the present invention is not limited in particular. The series-parallel connection comprises two installation modes of series connection and parallel connection, and is a known technology in the field.
Example 2
The application also provides a power terminal, which is provided with the super capacitor charge-discharge module as a backup power source in the embodiment 1, and the power failure detection circuit 4 is also connected with the working voltage of a terminal system.
When the super capacitor charging and discharging module is connected to the power terminal, the working schematic diagram of the power failure detection circuit 4 is as follows: referring to fig. 2 and 4 together, the power down detection chip V8 is a device with an open drain output, VIN is the level for charging the farad capacitor in fig. 4, VSys is the system operating voltage of the power terminal, which is usually 3.3V, 1.8V, etc.; POW _ DOWN is a signal point connected to a processor of an electric power terminal, and is used to send power DOWN information to the electric power terminal. When the power terminal system is powered on, the power failure detection circuit 4 is high in POW _ DOWN level, CTRL is low in level after inverted logic of the triode V7, the power failure detection circuit is used for controlling an enabling pin of the boost chip U1 in the power failure detection circuit 4, and normal operation of the system is realized when the boost chip is not enabled under the condition of power; when a system working voltage VSys or a charging voltage VIN is powered DOWN, if VIN is lower than a certain voltage, the output of the power failure detection chip V8 is a low level, so that POW _ DOWN is a low level, a processor of the power terminal receives low level information and starts to perform data backup or fault reporting work, and at the same time, CTRL is a high level after the power failure moment is inverted through a triode V7, so that an enabling pin of a boosting chip U1 in FIG. 4 is controlled, the boosting chip is enabled at the power failure moment, normal work is started, and the processor of the power terminal is ensured to complete the data backup or fault reporting work. Wherein CAP _ CTRL is an introduced software control signal (i.e., a control signal directly output by a processor of the power terminal), and is compatible with application software control.
It should be understood that equivalents and modifications of the technical solution and inventive concept thereof may occur to those skilled in the art, and all such modifications and alterations should fall within the scope of the appended claims.
Claims (10)
1. A super capacitor charge-discharge module is characterized by comprising: the charging circuit, the super capacitor bank, the discharging circuit and the power failure detection circuit are connected in series; the charging circuit and the discharging circuit are respectively connected with the super capacitor bank; the charging circuit is connected with a charging power supply and charges the super capacitor bank; the power failure detection circuit is respectively connected with the charging power supply and the discharging circuit.
2. The supercapacitor charge-discharge module according to claim 1, wherein the power-down detection circuit comprises: a power failure detection chip and an inverse logic switch; the input end of the power failure detection chip is connected with the charging power supply, the output end of the power failure detection chip is connected with the inverse logic switch, and the inverse logic switch is connected with the discharging circuit.
3. The supercapacitor charge-discharge module according to claim 2, wherein the discharge circuit comprises a discharge inductor and a boost chip; the boosting chip is connected with the discharge end of the super capacitor bank through the discharge inductor; the output end of the detection switch is connected with the enabling end of the boosting chip after being inverted in logic; the boost chip supplies power to the outside.
4. The supercapacitor charge-discharge module according to claim 3, wherein the inverse logic switch is an NPN triode, a base of the NPN triode is connected with the power-down detection chip, and a collector of the NPN triode is connected with the boost chip.
5. The super capacitor charge-discharge module as claimed in claim 3, wherein the type of the boost chip is TPS61089 or SGM 6610.
6. The super capacitor charge-discharge module as claimed in claim 3, wherein the power down detection chip is of a type R3111H 421A-T1-F.
7. The supercapacitor charge-discharge module according to claim 1, wherein the charging circuit comprises a charging switch, a charging regulator, a charging isolator; one end of the charging isolator is connected with a charging power supply, and the other end of the charging isolator is connected with the charging switch; one end of the charging voltage stabilizer is connected with the super capacitor bank, and the other end of the charging voltage stabilizer is connected with the charging switch; and the charging switch is respectively connected with the charging end of the super capacitor bank.
8. The supercapacitor charge-discharge module according to claim 1, wherein the supercapacitor group comprises a plurality of farad capacitors; the plurality of farad capacitors are arranged in series or in parallel or in series-parallel.
9. A super capacitor charging and discharging method applying the super capacitor charging and discharging module as claimed in any one of claims 1 to 8, characterized by comprising the steps of:
the power failure detection circuit detects whether a charging voltage exists in a charging power supply in real time, if yes, the power failure detection circuit sends a voltage storage signal to the discharge circuit, and the discharge circuit does not supply power to the outside; if not, the power failure detection circuit sends a power failure signal to the discharge circuit, and the discharge circuit supplies power to the outside.
10. An electric terminal, characterized in that, the super capacitor charge-discharge module of any one of claims 1-8 is used as a backup power supply, and the power failure detection circuit is also connected with the working voltage of a terminal system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010147524.9A CN111211602A (en) | 2020-03-05 | 2020-03-05 | Super capacitor charge-discharge module, charge-discharge method and power terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010147524.9A CN111211602A (en) | 2020-03-05 | 2020-03-05 | Super capacitor charge-discharge module, charge-discharge method and power terminal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111211602A true CN111211602A (en) | 2020-05-29 |
Family
ID=70786264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010147524.9A Pending CN111211602A (en) | 2020-03-05 | 2020-03-05 | Super capacitor charge-discharge module, charge-discharge method and power terminal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111211602A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111786552A (en) * | 2020-07-15 | 2020-10-16 | 河南许继仪表有限公司 | Super capacitor-based booster circuit |
| CN112583074A (en) * | 2020-12-11 | 2021-03-30 | 南方电网科学研究院有限责任公司 | Charging and discharging circuit of super capacitor |
| CN113629849A (en) * | 2021-07-30 | 2021-11-09 | 科大智能电气技术有限公司 | Alternating current power supply and backup power supply system of energy controller and use method |
| CN113922484A (en) * | 2021-07-26 | 2022-01-11 | 浙江利尔达物联网技术有限公司 | System and method for reporting power failure of Wi-SUN network |
-
2020
- 2020-03-05 CN CN202010147524.9A patent/CN111211602A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111786552A (en) * | 2020-07-15 | 2020-10-16 | 河南许继仪表有限公司 | Super capacitor-based booster circuit |
| CN112583074A (en) * | 2020-12-11 | 2021-03-30 | 南方电网科学研究院有限责任公司 | Charging and discharging circuit of super capacitor |
| CN113922484A (en) * | 2021-07-26 | 2022-01-11 | 浙江利尔达物联网技术有限公司 | System and method for reporting power failure of Wi-SUN network |
| CN113629849A (en) * | 2021-07-30 | 2021-11-09 | 科大智能电气技术有限公司 | Alternating current power supply and backup power supply system of energy controller and use method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111211602A (en) | Super capacitor charge-discharge module, charge-discharge method and power terminal | |
| US8090988B2 (en) | Saving information to flash memory during power failure | |
| US8713332B2 (en) | System and method of supplying an electrical system with direct current | |
| CN104935072A (en) | Switch control method and apparatus for reserve power supply | |
| CN103744803A (en) | Power supply component and storage system | |
| CN104767270A (en) | Mobile charging source with load detection function | |
| CN114336815A (en) | Multi-port charging control method | |
| CN101442215A (en) | Power feeding device, power supply method using the device and electronic equipment | |
| US8704404B2 (en) | Electrical assembly and method for supplying without interruption an installation with alternating current | |
| CN103973087A (en) | Power-down holding circuit | |
| RU2613179C2 (en) | Method for power supply and power supply with usb interface for load time-division multiple access system | |
| CN211981525U (en) | Super capacitor charge-discharge module and power terminal | |
| CN210111645U (en) | Power supply device capable of realizing rapid discharge | |
| JP2002315228A (en) | Power supply apparatus | |
| CN210246387U (en) | Power supply switching circuit and electronic equipment | |
| CN218675973U (en) | Output power supply circuit and electronic equipment that intelligence was switched | |
| CN103746444A (en) | Dual-power bus cold standby power supply architecture and method | |
| CN111525542B (en) | Power supply method for safely storing data of intelligent electric energy meter | |
| CN112531832A (en) | Charging path management circuit and device | |
| CN113687706B (en) | Device and method for automatically adjusting whether NCSI is opened or not | |
| CN220273333U (en) | Charging activation circuit and battery system | |
| CN217115707U (en) | Super capacitor charging and discharging circuit | |
| CN115811121B (en) | Farad capacitor backup power management circuit for power distribution terminal | |
| CN210490828U (en) | BMC delay power-off circuit | |
| CN214429312U (en) | STB hard disk protection device based on lithium cell |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |