US20140016381A1

US20140016381A1 - Current detecting circuit, controlling circuit and power conversion circuit

Info

Publication number: US20140016381A1
Application number: US14/028,019
Authority: US
Inventors: Jianning Sun
Original assignee: Sunsun Lighting China Co Ltd
Current assignee: Sunsun Lighting China Co Ltd
Priority date: 2011-03-15
Filing date: 2013-09-16
Publication date: 2014-01-16
Also published as: JP2014508501A; CN103477233B; EP2594948A1; US20140016384A1; EP2594948A4; CN103477233A; WO2012122701A1; US8963515B2

Abstract

The present invention provides a current detection circuit, a controlling circuit using the current detection circuit and a power conversion circuit using the controlling circuit, the current detection circuit comprises a sample keeping circuit, a rising edge detection circuit, a falling edge detection circuit, a sequential controlling circuit, a synchronous detection circuit and a lowpass filter. The inventive current detection circuit for the power conversion circuit obtains signals of the output current by detecting loop current of the master switch and processing the loop current.

Description

BACKGROUND OF THE INVENTION

1. Technical Field
The present invention relates to circuit technology, and more particularly, to a current detection circuit, a controlling circuit and a power conversion circuit.
2. Description of Related Art
A power conversion circuit, such as an AC-DC conversion circuit, can be used to convert AC to DC to provide electricity to relative devices. However, a power conversion circuit in the prior art generally doesn't possess the function of detecting output current thereof.

BRIEF SUMMARY OF THE INVENTION

The object of the present invention is to provide a current detection circuit for a power conversion circuit in order to detect output current thereof, the current detection circuit has the advantages of high reliable, simple structure and low cost.
The present invention adopts the following technical solutions to solve the technical problem: a current detection circuit for a power conversion circuit, wherein the current detection circuit includes a sample keeping circuit, a rising edge detection circuit, a falling edge detection circuit, a sequential controlling circuit, a synchronous detection circuit and a lowpass filter, a first end of the sample keeping circuit is connected to a third of the drive controlling transistor S2, a second end of the sample keeping circuit is connected to a first end of the sequential controlling circuit, a third end of the sample keeping circuit is connected to a first end of the synchronous detection circuit, a first end of the rising edge detection circuit is connected to a second end of a master switch S1, a second end of the rising edge detection circuit is connected to a second end of the sequential controlling circuit, a first end of the falling edge detection circuit is connected to a second end of the master switch S1, a second end of the falling edge detection circuit is connected to a third end of the sequential controlling circuit, a fourth end of the sequential controlling circuit is connected to a second end of the synchronous detection circuit, a third end of the synchronous detection circuit is connected to is a first end of the lowpass filter, and a second end of the lowpass filter is an output end of the current detection circuit.
Another object of the embodiment of the present invention is to provide a controlling circuit using the above-mentioned current detection circuit.
Another object of the embodiment of the present invention is to provide a power conversion circuit using the above-mentioned controlling circuit, the power conversion circuit further includes:
a filter circuit 12 connected to an external AC, wherein the filter circuit is used to filter the noise in the AC,
a rectification circuit 13 connected to the filter circuit and used for converting AC to DC, and
a single stage power conversion circuit 14 comprising a capacitor Cl, an inductor or switching transformer L, a diode D1, a capacitor C2, a master switch S1, a drive controlling transistor S2, a resistor R2, a controlling circuit and an auxiliary power supply circuit, a first end of the capacitor C1 is connected to both of the rectification circuit and a cathode of a DC load, a second of the capacitor C1 is grounded, a first end of the inductor or switching transformer L is connected to a cathode of the DC load, a second end of the inductor or switching transformer L is connected to an anode of a diode D1, a cathode of the diode D1 is connected to an anode of the DC load, the capacitor C2 is connected between the anode and cathode of the DC load, a first end of the master switch Si is connected to the cathode of the DC load by the auxiliary power supply circuit, a first end of the master switch S1 is connected to the anode of the diode D1, a first end of the drive controlling transistor S2 is connected to the controlling circuit, a second end of the drive controlling transistor S2 is connected to a third end of the master switch S1, a third end of the drive controlling transistor S2 is grounded by the resistor R2 and connected to the controlling circuit, the controlling circuit is further connected to a second end of the master switch S1, the single stage power conversion circuit is used to adjust a power factor and obtain signals of output current by detecting loop current of the master switch and processing the loop current.
The inventive current detection circuit of the power conversion circuit obtains the signals of the output current by detecting loop current of the master switch and processing the loop current.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a circuit diagram of a power conversion circuit using the current detection circuit according to the present invention;

FIG. 2 is a schematic circuit diagram of a controlling circuit using the current detection circuit in FIG. 1 according to the present invention;

FIG. 3 is a circuit diagram of the current detection circuit according to a first preferable embodiment;

FIG. 4 is a circuit diagram of the current detection circuit according to a second preferable embodiment;

FIG. 5 is a schematic waveform view of each node in FIG. 1 and FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

In order to make clearer the objects, technical solutions and advantages of the invention, the present invention will be explained below in detail with reference to the accompanying drawings and embodiments. It is to be understood that the following description of the embodiments is merely to explain the present invention and is no way intended to limit the invention.
The current detection circuit for a power conversion circuit provided by the embodiments of the present invention can be used to detect output current of the power conversion circuit, and the current detection circuit has the advantages of high reliable and simple structure.
Referring to FIG. 1, the inventive power conversion circuit includes a filter circuit 12, a rectification circuit 13 and a single stage power conversion circuit 14.
The filter circuit 12 is connected to a live wire L and a null line N of an external AC.
The rectification circuit 13 is connected to the external AC by the filter circuit 12.
The single stage power conversion circuit 14 is connected between a positive output end of the rectification circuit 13 and a DC load 15. A node between the positive output end of the rectification circuit 13 and the DC load 15 can be referred as “C”.
The filter circuit 12 can use a filter circuit well known and the rectification circuit 13 can use a bridge rectifier circuit, which doesn't be repeated here.
The single stage power conversion circuit 14 includes a capacitor C1, an inductor or switching transformer L, a diode D1, a capacitor C2, a master switch S1, a drive controlling transistor S2, a resistor R2, a controlling circuit 16 and an auxiliary power supply circuit 17.
A first end of the capacitor C1 is connected to both of the rectification circuit 13 and a cathode of the DC load 15, a second end of the capacitor C1 is grounded, a first end of the inductor or switching transformer L is connected to a cathode of the DC load 15, the second end of the inductor or switching transformer L is connected to an anode of the diode D1, a cathode of the diode D1 is connected to an anode of the DC load 15, the capacitor C2 is connected between the anode and cathode of the DC load 15, a first end of the master switch S1 is connected to the cathode of the DC load 15 by the auxiliary power supply circuit 17, a second end of the master switch S1 is connected to the anode of the diode D1, a first end of the drive controlling transistor S2 is connected to a first end H of the controlling circuit 16, a second end of the drive controlling transistor S2 is connected to a third end of the master switch S1, a third end of the drive controlling transistor S2 is grounded by a resistor R2 and also connected to a second end U of the controlling circuit 16, and a third end D of the controlling circuit 16 is connected to a second end of the master switch S1.
Both of the master switch Si and the drive controlling transistor S2 are N-channel field effect transistors. A node between a drain of the master switch S1 and the anode of the diode D1 can be referred as D, a node between a grid of the master switch S1 and the auxiliary power supply circuit 17 can be referred as E, and a node between a drain of the drive controlling transistor S2 and a source of the master switch S1 can be referred as F.
Referring to FIG. 2, the controlling circuit 16 includes a valley detection circuit 161, a current detection circuit 162, an error amplifier Err amp, a PWM controller U1 and a drive controlling circuit 163, the input end U of the current detection circuit 162 is connected to a third end of the drive controlling transistor S2, the input end D of the current detection circuit 162 is connected to a second end of the master switch S1, an output end of the current detection circuit 162 is connected to an input end of the error amplifier Err_amp, an output end of the error amplifier is connected to the PWM controller U1, the PWM controller U1 is connected to a first end of the drive controlling circuit 163, a second end of the drive controlling circuit 163 is connected to an output end of the valley detection circuit 161, a third end of the drive controlling circuit 163 is connected to a first end of the drive controlling transistor S2, and an input end of the valley detection circuit 161 is connected to a second end of the master switch S1.
The auxiliary power supply circuit 17 includes a diode D2, a resistor R1, a capacitor C6 and a voltage regulator Z2, an anode of the diode D2 is connected to the a cathode of the DC load 15, a cathode of the diode D2 is grounded through the resistor R1 and the capacitor C6 in turn, a node between the resistor R1 and the capacitor C6 is connected to the first end of the master switch S1, an anode of the voltage regulator Z2 is grounded, and a cathode of the voltage regulator Z2 is connected to the first end of the master switch S1.
The working process of the inventive power conversion circuit is described as follows.
The filter circuit 12 is used to filter noise in the AC, the rectification circuit 13 is used for AC-DC conversion, and the single stage power conversion circuit 14 is used to adjust a power factor of the power conversion circuit and detect the output current thereof. The auxiliary power supply circuit 17 in the single stage power conversion circuit 14 is used to provide an auxiliary power supply, the controlling circuit 16 is used to detect current output to the DC load 15 and adjust an average value of the current output to the DC load 15 to be equal to a predefined value defined by the DC load 15, thereby, the current output to the DC load 15 is kept constant.
When a node E of an input controlling end of the master switch S1 is powered on, the node E is clamped at fixing electrical level, the switching on and off of the master switch S1 is mainly controlled by the drive controlling transistor S2. During the switching on of the master switch S1, the current of the inductor L rises, when the master switch S1 is switched off, due to the stray capacitance of the master switch S1 and the diode D1, the voltage of a node D of an upper end of the master switch S1 rises from zero (zero voltage turn-off), when the electric potential of the node D exceeds the electric potential of a node K of the DC load 15, the diode D1 is switched on, the current of the inductor L is output to the DC load 15 through the diode D1, the current of the inductor L drops from a peak value, when the current of the inductor L drops to zero, due to the resonance between the stray capacitance of the master switch Si and the diode D1 and the inductor L, the electric potential of the upper node D of the master switch S1 begins to drop, the voltage of the upper node D of the master switch S1 will arrives at a valley value after a period of time.
The valley detection circuit 161 is used to control switching on time of the single stage power conversion circuit 14, the voltage of the end D is detected, when a value of the voltage is equal to a valley value, the detected result is sent to the drive controlling circuit 163 and the master switch S1 is driven to switch on by the drive controlling circuit 163 and the drive controlling transistor S2, zero voltage turn-on is realized, therefore, switching loss of the valley detection circuit 161 is low. In the working process of the power conversion circuit, if switching on duration of the master switch S1 is increased, working current of the inductor L and current of the output load 15 are increased, if switching on duration of the master switch S1 is decreased, the working current of the inductor L and the current of the output load 15 are decreased.
FIG. 2 also can be referred at the same time, the controlling circuit 16 and the single stage power conversion circuit 14 are connected by three ends D, U and H. With regard to the controlling circuit 16, the ends D, U are output ends of the controlling circuit 16, based on information of the ends D, U, controlling signals are generated at the end H by the controlling circuit 16, and then the controlling signals are used to control the drive controlling transistor S2 so as to control working process of the single stage power conversion circuit 14. The controlling circuit 16 needs to obtain current information of the output load 15 to control a switch circuit, therefore, better power efficiency and power factor can be obtained.
In the present, the power conversion circuit filters the noise in the AC by the filter circuit 12, an AC-DC conversion is performed by the rectification circuit 13, and the single stage power conversion 14 detects the current output to the DC load and adjusts the power factor.
Furthermore, the power conversion circuit in the present invention also includes a fuse F1. The fuse F1 is connected between the live wire L and the filter circuit 12, when the current flowing through the fuse F1 is excessive, the fuse F1 is blown to protect the power conversion circuit.
Referring to FIG. 2 again, furthermore, the current detection circuit 162 includes a sample keeping circuit 1, a rising edge detection circuit 2, a falling edge detection circuit 3, a sequential controlling circuit 4, a synchronous detection circuit 5 and a lowpass filter 6.
A first end S11 of the sample keeping circuit 1 is connected to the end U, a second end S12 of the sample keeping circuit 1 is connected to a first end S41 of the sequential controlling circuit 4, and a third end S13 of the sample keeping circuit 1 is connected to a first end S51 of the synchronous detection circuit 5.
A first end S21 of the rising edge detection circuit 2 is connected to the node D, and a second end S22 of the rising edge detection circuit 2 is connected to a second S42 of the sequential controlling circuit 4.
A first end S31 of the falling edge detection circuit 3 is connected to the node D, and a second end S32 of the falling edge detection circuit 3 is connected to a third end S43 of the sequential controlling circuit 4.
A fourth end S44 of the sequential controlling circuit 4 is connected to a second end S52 of the synchronous detection circuit 5.
A third end S53 of the synchronous detection circuit 5 is connected to a first end S61 of the lowpass filter 6, a second end S62 of the lowpass filter 6 is connected to an input end of the error amplifier Err_amp.
The controlling circuit 16 detects current of the sample resistor R2 by the current detection circuit 162, signals of the detected current are processed to obtain an average value of the current output to the DC load 15, then the average value is input to the drive controlling circuit 163 and used to compare with a predefined value, based on the comparison whether the switching on time of the master switch S1 is increased or decreased is determined, which can make the output current be equal to the predefined value. Whatever the DC load or an input voltage fluctuates, the drive controlling circuit 163 can dynamically adjust switching on and off durations of the master switch S1 so as to obtain the output current desired by the DC load 15.
Referring to FIG. 3, as a preferable embodiment, the sample keeping circuit 1 of the current detection circuit 162 includes a N-channel field effect transistor N1, an inverter INV1, a capacitor C3, an amplifier A1, resistors R3 and R4. A drain of the N-channel field effect transistor N1 is connected to the node U, a grid of the N-channel field effect transistor N1 is connected to an input end of the inverter INV1, a source of the N-channel field effect transistor N1 is grounded by the capacitor C3. The input end of the inverter INV1 is connected to a controlling end CTL. A noninverting input end of the amplifier A1 is connected to the source of the N-channel field effect transistor N1, an inverting input end of the amplifier A1 is grounded by the resistor R3, an output end of the amplifier A1 is connected to the inverting input end thereof by the resistor R4. During the switching on time of the master switch S1, the current sample keeping circuit 1 keeps on sampling, and outputs a signal proportional to the input current thereof, after the master switch S1 is switched off, the sample keeping circuit 1 maintains sampling.
The rising edge detection circuit 2 includes an amplifier A2, resistors R5 and R6. One end of the resistor R5 is connected to the node D, the other end of the resistor R5 is grounded by the resistor R6. A noninverting input of the amplifier A2 is connected to a node between the resistors R5 and R6, an inverting input of the amplifier A2 is connected to a reference voltage end VREF2. When the rising edge detection circuit 2 detects that the voltage of the upper end of the master switch S1 rises to a predefined value, the rising edge detection circuit 2 triggers a latch circuit to control the synchronous detection circuit 5 to output signals from the current sample keeping circuit 1 to the lowpass filter 6.
The falling edge detection circuit 3 includes an amplifier A3, an inverter INV2, a N-channel field effect transistor N2, a capacitor C4, clamping. zeners Z1-Z4, resistors R7 and R8. One end of the resistor R7 is connected to the node D, the other end is grounded by the resistor R8. One end of the capacitor C4 is connected to a node between the resistors R7 and R8, the other end is connected to a noninverting input of the amplifier A3. An inverting input of the amplifier A3 is connected to a reference voltage end VREF1, an output end of the amplifier A3 is connected to an input end of the inverter INV2. Both of a grid and drain of the N-channel field effect transistor N2 are connected to the noninverting input of the amplifier A3, a source of the N-channel field effect transistor N2 is grounded. A cathode of the clamping zener Z1 is connected to a node between resistors R7 and R8, an anode of the clamping zener Z1 is grounded by the clamping zener Z2-Z4 in turn. When the falling edge detection circuit 3 detects that a falling edge of the voltage of the upper end of the master switch Si, the falling edge detection circuit 3 unlocks a latch and shutdowns the synchronous detection circuit 5, so that the input signals of the lowpass filter 6 change to zero.
The sequential controlling circuit 4 includes D-flip flops DF1 and DF2. A clock signal end CK of the D-flip flop DF1 is connected to an output of the inverter INV2 in the falling edge detection circuit 3, a reset end R of the D-flip flop DF1 is connected to an output of the inverter INV1 in the sample keeping circuit 1, a signal input end D of the D-flip flop DF1 is connected to a power supply VDD, an output end Q of the D-flip flop DF1 is connected to a reset end R of the D-flip flop DF2, a noninvertering output end QB of the D-flip flop DF1 is not used. A clock signal end CK of the D-flip flop DF2 is connected to an output end of the amplifier A2, a signal input end D of the D-flip flop DF2 is connected to the power supply VDD, an output end Q of the D-flip flop DF2 is not used.
The synchronous detection circuit 5 includes an inverter INV3, N-channel field effect transistors N3 and N4. An input end of the inverter INV3 is connected to an inverting output end QB of the D-flip flop DF2 in the sequential controlling circuit 4, an output end of the inverter INV3 is connected to a grid of the N-channel field effect transistor N3. A drain of the N-channel field effect transistor N3 is connected to an output end of the amplifier A1 in the sample keeping circuit 1, a source of the N-channel field effect transistor N3 is connected to a drain of the N-channel field effect transistor N4. A grid of the N-channel field effect transistor N4 is connected to an input end of the inverter INV3, a source of the N-channel field effect transistor N4 is grounded.
The lowpass filter 6 includes a resistor R9 and a capacitor C5. One end of the resistor R9 is connected to a drain of the N-channel field effect transistor N4 in the synchronous detection circuit 5, the other end is grounded by the capacitor C5 and also connected to an input end of the error amplifier, the lowpass filter 6 filters an input signal thereof and outputs a signal directly proportional to an average value of the output current of the DC load 15.
FIG. 5 can be referred at the same time, the current waveform of the inductor L is referred as I_L, the current waveform of the diode D1 is referred as I_D1, the voltage waveform of the node D is referred as V_D, the waveform of the output signal of the sample keeping circuit 1 is referred as S_H_out, the waveform of the output signal of the synchronous detection circuit 5 is referred as Syn_out, the signal waveform of the output end Q of the D-flip flop DF1 is referred as DF1_Q, the signal waveform of the inverting output end QB of the D-flip flop DF2 is referred as DF2_QB.
As shown in FIG. 5, the average value I_avr of the current output to the DC load 15 is equal to the average value of the I_D1, namely, equal to the value of multiplying a duty cycle by the value of dividing a peak value of the I_D1 by 2. According to practical application, just a signal proportional to I_avr is needed. Next will describes how the current detection circuit 162 obtains the signal.
When the master switch S1 is switched on, the signal of the end U is input to the sample keeping circuit 1. During the switching on of the master switch S1, the sample keeping circuit 1 keeps on sampling, output signals S_H_out are used to track the current I_L of the inductor L, the synchronous detection circuit 5 is switched off, the output signals of the synchronous detection circuit 5 are low level.
When the switching on duration of the master switch S1 is ended, the voltage V_F of the node F rises, the master switch S1 is switched off, the electric potential V_D of the end D rises, when the electric potential of the node D approximates the electric potential of the node C, the current I_L of the inductor L discharge to the DC load 15 through the diode D1. The rising edge detection circuit 2 acts and outputs action signals to the sequential controlling circuit 4, then the sample keeping circuit 1 is controlled to maintain sampling by the sequential controlling circuit 4, the sample keeping circuit 1 maintains a voltage proportional to a peak current of the inductor L, the peak current of the inductor L is equal to a peak current of the diode D1, therefore, the output S_H_out of the sample keeping circuit 1 is proportional to a peak value of the current I_D1 of the diode D1.
Before the current I_L of the inductor L drops to zero, since the sample keeping circuit 1 maintains sampling, the signal remains the same all the time. The synchronous detection circuit 5 is switched on, the output S_H_out of the sample keeping circuit 1 is output to the lowpass filter 6 through the synchronous detection circuit 5. As the current I_L of the inductor L discharges to the DC load 15 through the diode D1, the current I_L of the inductor L gradually drops.
When the current I_L of the inductor L drops to zero, the electric potential of the node D begins to drop, when the signal indicating that the electric potential of the node D begins to drop is detected by the falling edge detection circuit 3, the falling edge detection circuit 3 acts and outputs action signals to the sequential controlling circuit 4, the sequential controlling circuit 4 switches off the synchronous detection circuit 5 to make the input signal of the lowpass filter 6 being zero. In the switching on duration, the average value of the input signals output to the lowpass filter 6 is directly proportional to the average value of the output current, namely, a signal output by the lowpass filter is directly proportional to the average value of the output current I_avr.
The current signals output by the lowpass filter 6 and an internal reference value defined by the lowpass filter 6 are sent to the error amplifier Err_amp, if the average value of the output current is greater than the internal reference value, the output of the error amplifier Err_amp controls the switching on duration of the master switch S1 to gradually decrease by the PWM controller U1, if the average value of the output current is smaller than the internal reference value, the output of the error amplifier Err_amp controls the switching on duration of the master switch 51 to gradually increase by the PWM controller U1. At last, the average value of the output current is equal to the internal reference value, and the output current is constant.
After the switching off duration of the master switch S1 is ended, the master switch S1 is switched on again, the circuit enters the next circle.
When the V_F is low level, the master switch S1 is switched on, the end D2_QB of the D-flip flop DF2 outputs high level. Signals of the current sample resistor R2 are output to the field effect transistor N1 of the sample keeping circuit 1. A timing sequence of the signal applied on the grid of the field effect transistor N1 is synchronous with the driving signal of the master switch S1. When the master switch S1 is switched on, the controlling end CTL of the master switch S1 is high level (being inverting to the V_F), the sample keeping circuit 1 keeps on sampling, the output of the D1_Q of the D-flip flop DF1 of the sequential controlling circuit 4 is high level, the output of the D2_QB of the D-flip flop DF2 is high level, the field effect transistor N4 of the synchronous detection circuit 5 is grounded, the field effect transistor N3 of the synchronous detection circuit 5 is switched off, and the output of the synchronous detection circuit 5 is zero.
When the switching on duration of the master switch S1 is ended, the master switch S1 is switched off, the electrical level of the controlling end CTL of the master switch S1 changes to low level, the sample keeping circuit 1 maintains the sampling, the D-flip flop DF1 is reset, the output of the D1_Q of the D-flip flop DF1 is low level, and a reset status of the D-flip flop DF2 is terminated. As the master switch S1 is switched off, the electric potential V_D of the upper end D rises, when the electric potential V_D approaches the electric potential of the node C, the rising edge detection circuit 2 acts, the output of the A2 amplifier becomes higher, and then triggers the output of the D2_QB of the D-flip flop DF2 to become lower, thereby switching on the field effect transistor N3 of the synchronous detection circuit 5 and switching off the field effect transistor N4 of the synchronous detection circuit 5, the output signal of the sample keeping circuit 1 is output to the, input end of the low filter circuit 6. At this moment, the current I_L of the inductor L discharges to the DC load 15, the current gradually drops.
Referring to FIG. 4 again, as an inventive preferable embodiment, the N-channel field effect transistor N1 in the falling edge detection circuit 3 of the current detection circuit 162 can be replaced by a diode D3. An anode of the diode D3 is connected to the noninverting input end of the amplifier A1, a cathode of the diode D3 is grounded.
In the present invention, the power conversion circuit filters the nose in the AC by the filter circuit 12, the rectification circuit 13 is used for AC-DC conversion, the single stage power conversion 14 is used for adjusting the power factor and adjusting the average value of the output current to be equal to the predefined value, therefore, the constant current output is obtained.
The present invention has been further detailed in the above descriptions with reference to the preferred embodiments; however, it shall not be construed that implementations of the present invention are only limited to these descriptions. Many simple deductions or replacements may further be made by those of ordinary skill in the art without departing from the conception of the present invention, and all of the deductions or replacements shall be considered to be covered within the protection scope of the present invention.

Claims

1. A current detection circuit for a power conversion circuit, wherein the current detection circuit comprises a sample keeping circuit, a rising edge detection circuit, a falling edge detection circuit, a sequential controlling circuit, a synchronous detection circuit and a lowpass filter, a first end of the sample keeping circuit is connected to a third of the drive controlling transistor S2, a second end of the sample keeping circuit is connected to a first end of the sequential controlling circuit, a third end of the sample keeping circuit is connected to a first end of the synchronous detection circuit, a first end of the rising edge detection circuit is connected to a second end of a master switch S1, a second end of the rising edge detection circuit is connected to a second end of the sequential controlling circuit, a first end of the falling edge detection circuit is connected to a second end of the master switch Si, a second end of the falling edge detection circuit is connected to a third end of the sequential controlling circuit, a fourth end of the sequential controlling circuit is connected to a second end of the synchronous detection circuit, a third end of the synchronous detection circuit is connected to is a first end of the lowpass filter, and a second end of the lowpass filter is an output end of the current detection circuit.

2. The current detection circuit for the power conversion circuit of claim 1, wherein the sample keeping circuit comprises a field effect transistor N1, an inverter INV1, a capacitor C3, an amplifier A1, resistors R3 and R4, a drain of the field effect transistor N1 is used as a first end of the sample keeping circuit, a grid of the field effect transistor N1 is connected to an input end of the inverter INV1, a source of the field effect transistor N1 is grounded by the capacitor C3, signals of the input end of the inverter INV1 and controlling signals of a first end of the drive controlling transistor S2 have the same phase, an output end of the inverter INV1 is used as a second end of the sample keeping circuit, a noninverting input end of the amplifier A1 is connected to a source of the field effect transistor N1, an inverting input of the amplifier A1 is grounded by the resistor R3, an output end of the amplifier A1 is connected to the inverting input end by the resistor R4 and used as a third end of the sample keeping circuit, the sample keeping circuit keeps on sampling during the switching on of the master switch S1, a signal output by the sample keeping circuit is proportional with input current signals thereof, when the master switch S1 is switched off, the sample keeping circuit maintains sampling.

3. The current detection circuit for the power conversion circuit of claim 1, wherein the rising edge detection circuit comprises an amplifier A2, resistors R5 and R6, a first end of the resistor R5 is used as a first end of the rising edge detection circuit, a second end of the rising edge detection circuit is grounded by the resistor R6, a noninverting input end of the amplifier A2 is connected to a node between the resistors R5 and R6, an inverting input end of the amplifier A2 is connected to a reference voltage end, an output end of the amplifier A2 is used as a second end of the rising edge detection circuit connected to a second end of the sequential controlling circuit, when the rising edge detection circuit detects that the voltage of the upper end of the master switch Si rises to a predefined value, a latch circuit is triggered by the rising edge detection circuit to control synchronous detection circuit in order to output signals from the current synchronous detection circuit to a low-pass filter circuit.

4. The current detection circuit for the power conversion circuit of claim 1, wherein the falling edge detection circuit comprises an amplifier A3, an inverter INV2, a field effect transistor N2, a capacitor C4, clamping zeners Z1-Z4, resistors R7 and R8, a first end of the resistor R7 is used as a first end of the falling edge detection circuit, a second end of the resistor R7 is grounded by the resistor R8, a first end of the capacitor C4 is connected to a node between the resistors R7 and R8, a second end of the capacitor C4 is connected to a noninverting input end of the amplifier A3, an inverting input end of the amplifier A3 is connected to a reference voltage end, an output end of the amplifier A3 is connected to an input end of the inverter INV2, an output end of the inverter INV2 is used as a second of the falling edge detection circuit, both of a grid and drain of the field effect transistor N2 are connected to a noninverting input end of the amplifier A3, a source of the field effect transistor N2 is grounded, a cathode of the clamping zener Z1 is connected to a node between the resistors R7 and R8, an anode of the clamping zener Z1 is grounded by the clamping zeners Z2, Z3 and Z4 in turn, when a falling edge of the voltage of the upper end of the master switch Si is detected by the falling edge detection circuit, a latch is released, the synchronous detection circuit is switched off, thus input signals of the low-pass filter circuit are zero.

5. The current detection circuit for the power conversion circuit of claim 1, wherein the sequential controlling circuit comprises D-flip flops DF1 and DF2, a reset end of the D-flip flop DF1 is used as a first end of the sequential controlling circuit connected to a second end of the sample keeping circuit, a clock signal end of the D-flip flop DF1 is used as a third end of the sequential controlling circuit connected to a second end of the falling edge detection circuit, a signal input end of the D-flip flop DF1 is connected to a power supply, an output end of the D-flip flop DF1 is connected to a reset end of the D-flip flop DF2, an inverting output end of the D-flip flop DF1 is not used, a clock signal end of the D-flip flop DF2 is used as a second end of the sequential controlling circuit connected to a second end of the rising edge detection circuit, a signal input end of the D-flip flop DF2 is connected to a power supply, an output end is not used, an inverting output end the D-flip flop DF2 is used as a fourth end of the sequential controlling circuit connected to a second end of the synchronous detection circuit.

6. The current detection circuit for the power conversion circuit of claim 1, wherein the synchronous detection circuit comprises an inverter INV3, field effect transistors N3 and N4, a drain of the field effect transistor N3 is used as a first end of the synchronous detection circuit connected to a third end of the sample keeping circuit, a source of the field effect transistor N3 is connected to a drain of the field effect transistor N4, a grid of the field effect transistor N3 is connected to an output end of the inverter INV3, an input end of the inverter INV3 is used as a second end of the synchronous detection circuit connected to a fourth end of the sequential controlling circuit, a grid of the field effect transistor N4 is connected to an input end of the inverter INV3, a source of the field effect transistor N4 is grounded, and the drain of the field effect transistor N4 also is used as a third end of the synchronous detection circuit connected to a first end of the lowpass filter.

7. The current detection circuit for the power conversion circuit of claim 1, wherein a first end of the lowpass filter is connected to a third end of the synchronous detection circuit, a second end of the lowpass filter is connected to an input end of the error amplifier, after the lowpass filter filters input signals thereof, the lowpass filter outputs a signal directly proportional to an average value of output current of the DC load 15.

8. A controlling circuit using the current detection circuit for the power conversion circuit of claim 1, wherein the controlling circuit further comprises a valley detection circuit, an error amplifier, a PWM controller and a drive controlling circuit, the end U of the current detection circuit is connected to a third end of the drive controlling transistor S2, the end D of the current detection circuit is connected to a second end of the master switch S1, the output end of the current detection circuit is the second end of the lowpass filter and connected to an input end of the error amplifier, an output end of the error amplifier is connected to the PWM controller, the PWM controller is connected to the drive controlling circuit, the drive controlling circuit is further connected to an output end of the valley detection circuit, and an input end of the valley detection circuit is connected to a second end of the master switch S1.

9. A power conversion circuit using the controlling circuit of claim 8, wherein the power conversion circuit comprises:

a filter circuit 12 connected to an external AC, wherein the filter circuit is used to filter the noise in the AC,

a rectification circuit 13 connected to the filter circuit and used for converting AC to DC, and

a single stage power conversion circuit 14 comprising a capacitor C1, an inductor or switching transformer L, a diode D1, a capacitor C2, a master switch S1, a drive controlling transistor S2, a resistor R2, a controlling circuit and an auxiliary power supply circuit, a first end of the capacitor C1 is connected to both of the rectification circuit and a cathode of a DC load, a second of the capacitor C1 is grounded, a first end of the inductor or switching transformer L is connected to a cathode of the DC load, a second end of the inductor or switching transformer L is connected to an anode of a diode D1, a cathode of the diode D1 is connected to an anode of the DC load, the capacitor C2 is connected between the anode and cathode of the DC load, a first end of the master switch Si is connected to the cathode of the DC load by the auxiliary power supply circuit, a first end of the master switch S1 is connected to the anode of the diode D1, a first end of the drive controlling transistor S2 is connected to the controlling circuit, a second end of the drive controlling transistor S2 is connected to a third end of the master switch S1, a third end of the drive controlling transistor S2 is grounded by the resistor R2 and connected to the controlling circuit, the controlling circuit is further connected to a second end of the master switch S1, the single stage power conversion circuit is used to adjust a power factor and obtain signals of output current by detecting loop current of the master switch and processing the loop current.

10. The power conversion circuit of claim 9, wherein the auxiliary power supply circuit comprises a diode D2, a resistor R1, a capacitor C6 and a voltage regulator Z2, an anode of the diode D2 is connected to a cathode of the DC load, a cathode of the diode D2 is grounded by the resistor R1 and capacitor C6 in turn, a node between the resistor R1 and capacitor C6 is connected to a first end of the master switch S1, an anode of the voltage regulator Z2 is grounded, and a cathode of the voltage regulator Z2 is connected to a first end of the master switch S1.