CN110854961B - Power-on impact current suppression circuit - Google Patents
Power-on impact current suppression circuit Download PDFInfo
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- CN110854961B CN110854961B CN201911192444.9A CN201911192444A CN110854961B CN 110854961 B CN110854961 B CN 110854961B CN 201911192444 A CN201911192444 A CN 201911192444A CN 110854961 B CN110854961 B CN 110854961B
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- resistor
- field effect
- capacitor
- effect tube
- voltage
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
- H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices
Abstract
The invention discloses a power-on impact current suppression circuit which comprises a delay circuit and a main switch circuit, wherein the delay circuit comprises resistors R3, R5 and R6, a voltage stabilizing diode VE2, a capacitor C2 and a field effect tube V2, and the main switch circuit comprises a capacitor C1, resistors R1, R2, R4 and R7, a voltage stabilizing diode VE1 and a field effect tube V1. The invention can flexibly adjust the conduction time of the main switch circuit by simply changing the resistor R3 and the capacitor C2 according to actual requirements. The design is flexible, the suitability is wide, and the devices used are all common resistors, capacitors, voltage stabilizing diodes, MOS tubes and the like, so that the method has the advantages of convenience in purchase, short production period, low cost and the like, and has wide application prospects.
Description
Technical Field
The invention relates to a power-on impact current suppression circuit, and belongs to the technical field of avionics.
Background
The invention belongs to the technical field of avionics, an airborne power supply system is required to simultaneously supply power to a plurality of airborne electronic devices, and whether the power supply system can reliably and stably work directly determines whether an aircraft is reliable in operation. Generally, an onboard power supply system requires that the influence on the power supply system is reduced as much as possible in the working process of onboard electric equipment, and at the moment of electrifying the onboard electric equipment, the impact current caused by capacitor charging usually reaches dozens of amperes or even hundreds of amperes, is more than ten times of the normal working current of the onboard electric equipment, and easily causes the fluctuation of onboard voltage. Therefore, generally, the on-board electronic product must have a power-on inrush current suppression circuit to suppress the power-on inrush current within a specified range, so as to reduce the influence on the power supply system and ensure the reliable operation of the power supply system.
The common impact current suppression circuit for the direct-current power supply has two implementation methods, namely, the power-on impact current is suppressed in a grading manner, a control circuit is complex, and a multistage switching circuit is arranged in a main loop of the power supply, so that the loss in the power supply transmission process can be increased. Secondly, a mode that a current-limiting resistor is connected with a power switch in parallel is adopted, the power switch is controlled in a time-delay mode, before the power switch is conducted, a capacitor is charged through the current-limiting resistor, the voltage difference between an input power supply and the interior of an electronic product is reduced, the power switch is conducted again, and the impact current is reduced. The circuit is only suitable for the electric equipment without the power switch control function. If the circuit is adopted by the electric equipment with the switch control function, if a power supply is loaded to the input end of the electric equipment, but a user does not open the switch of the electronic product at the moment, the current-limiting resistor can charge the capacitor all the time, when the voltage on the capacitor reaches the working voltage of the power supply conversion circuit of the electric equipment, the electric equipment can start to work, because the current-limiting resistor cannot provide current enough for normal work of the used equipment, the voltage on the capacitor can drop below the working voltage of the power supply conversion circuit of the electric equipment, the work of the power supply conversion circuit of the electric equipment stops working, the current-limiting resistor continues to charge the capacitor, so that the voltage on the capacitor reaches the working voltage of the power supply conversion circuit of the electric equipment again, and the electric equipment can start to work again. Such repeated starting and stopping operations may affect the reliability of the electric equipment.
Disclosure of Invention
The invention aims to solve the defects of the prior art, and provides a power-on impact current suppression circuit aiming at the problems that the existing impact current suppression circuit is complex in control circuit, large in power transmission loss and limited in use.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a power-on surge current suppression circuit comprises a delay circuit and a main switch circuit,
wherein the delay circuit comprises resistors R3, R5 and R6, a voltage stabilizing diode VE2, a capacitor C2 and a field effect tube V2, the main switch circuit comprises a capacitor C1, resistors R1, R2, R4 and R7, a voltage stabilizing diode VE1 and a field effect tube V1,
when the switching signals ON/OFF1 and ON/OFF2 are disconnected, the field effect tube V2 in the delay circuit is cut OFF, the field effect tube V1 in the main switching circuit is cut OFF, and no electric energy enters the electric equipment;
when the switching signals ON/OFF1 and ON/OFF2 are switched ON, the capacitor C2 is charged through the resistor R3, the voltage ON the capacitor C2 slowly rises, when the voltage ON the capacitor C2 reaches the lower limit of the opening voltage of the field effect transistor V2, the field effect transistor V2 starts to be conducted,
in the process that the field effect tube V2 in the delay circuit is slowly conducted, the resistors R1, R4 and R7 form a loop to GND, current starts to flow through, voltage drop is generated on the resistor R1, as the conduction degree of the field effect tube V2 in the delay circuit is deepened, the current flowing through the resistors R1, R4 and R7 to GND is gradually increased,
when the voltage drop generated on the resistor R1 reaches the lower limit of the starting voltage of the field effect tube V1, the field effect tube V1 starts to be conducted, current starts to flow through the field effect tube V1, the capacitor at the input end of the electric equipment is charged,
along with the deepening of the conduction degree of the field effect tube V1 in the main switch circuit, the charging current provided for the capacitor C1 through the field effect tube V1 is slowly increased until the charging is completed.
The invention has the following beneficial effects:
1. the time of the main switch circuit can be flexibly adjusted by changing the simple resistor R3 and the capacitor C2 according to actual requirements.
2. The design is flexible, the suitability is wide, and the devices used are all common resistors, capacitors, voltage stabilizing diodes, MOS tubes and the like, so that the method has the advantages of convenience in purchase, short production period, low cost and the like, and has wide application prospects.
Drawings
Fig. 1 is a circuit diagram of a power-on surge current suppression circuit of the present invention.
Detailed Description
The invention provides a power-on impact current suppression circuit. The technical solution of the present invention is described in detail below with reference to the accompanying drawings so that it can be more easily understood and appreciated.
As shown in fig. 1, the rush current suppression circuit includes a delay circuit and a main switching circuit. The delay circuit is composed of resistors R3, R5 and R6, a voltage stabilizing diode VE2, a capacitor C2 and a field effect tube V2. The main switch circuit is composed of a capacitor C1, resistors R1, R2, R4 and R7, a voltage stabilizing diode VE1 and a field effect tube V1.
When the switching signals (ON/OFF 1 and ON/OFF 2) are not switched ON, the field effect tube V2 in the delay circuit is cut OFF, the field effect tube V1 in the main switching circuit is cut OFF, and no electric energy enters the electric equipment.
When the switching signals (ON/OFF 1 and ON/OFF 2) are switched ON, the capacitor C2 is charged through the resistor R3, the voltage ON the capacitor C2 slowly rises, and when the voltage ON the capacitor C2 reaches the lower limit of the opening voltage of the field effect transistor V2, the field effect transistor V2 starts to be conducted.
In the process that a field effect tube V2 in the delay circuit is slowly conducted, resistors R1, R4 and R7 form a loop for GND, current starts to flow through, and voltage drop is generated on the resistor R1. As the conduction degree of the field effect transistor V2 in the delay circuit is increased (the voltage drop is decreased), the current flowing through the resistors R1, R4, and R7 to GND is gradually increased, and when the voltage drop generated on the resistor R1 reaches the lower limit of the turn-on voltage of the field effect transistor V1, the field effect transistor V1 starts to be turned on, and a current starts to flow through the field effect transistor V1, so as to start to charge the capacitor at the input terminal of the power consumption device.
Along with the deepening of the conduction degree (the reduction of the voltage drop) of the field effect tube V1 in the main switch circuit, the charging current provided for the capacitor through the field effect tube V1 is slowly increased until the charging is completed. When the field effect transistor V1 is completely conducted, the conduction resistance of the field effect transistor V1 is very small, and the transmission dissipation of the main power supply is very small.
In addition, in the circuit design process, the conduction time of the main switch circuit can be flexibly adjusted through simple change of the resistor R3 and the capacitor C2 according to actual requirements.
Through the above description, it can be found that the power-on impact current suppression circuit of the invention can flexibly adjust the conduction time of the main switch circuit through simple modification of the resistor R3 and the capacitor C2 according to actual requirements. The design is flexible, the suitability is wide, and the devices used are all common resistors, capacitors, voltage stabilizing diodes, MOS tubes and the like, so that the method has the advantages of convenience in purchase, short production period, low cost and the like, and has wide application prospects.
While the technical solutions of the present invention have been fully described above, it should be noted that the embodiments of the present invention are not limited by the above description, and all technical solutions formed by equivalent or equivalent changes in structure, method, or function according to the spirit of the present invention by those skilled in the art are within the scope of the present invention.
Claims (1)
1. A power-on surge current suppression circuit, characterized by:
comprises a delay circuit and a main switch circuit,
wherein the delay circuit comprises a resistor R3, a resistor R5, a resistor R6, a voltage stabilizing diode VE2, a capacitor C2 and a field effect tube V2, the main switch circuit comprises a capacitor C1, a resistor R2, a resistor R4, a resistor R7, a voltage stabilizing diode VE1 and a field effect tube V1,
one end of the resistor R3 is connected with a power supply, the other end of the resistor R3 is connected with the ON/OFF1, one end of the capacitor C2 is grounded, the other end of the capacitor C2 is connected with the ON/OFF2, the voltage stabilizing diode VE2, the resistor R6 and the field effect tube V2 are connected in parallel with two ends of the capacitor C2, a resistor R5 and a resistor R7 are respectively arranged ON a connecting path of the field effect tube V2 and the capacitor C2, the resistor R7 is grounded,
the resistor R1 and the resistor R4 are connected in series and then connected between the drain electrode of the field effect tube V2 and the positive power line, the capacitor C1 and the voltage stabilizing diode VE1 are connected in parallel at two ends of the resistor R1, the grid electrode of the field effect tube V1 is connected in series with the resistor R2 and then connected in parallel at two ends of the resistor R1, the source electrode of the field effect tube V1 is connected with the positive power line,
when the switching signals ON/OFF1 and ON/OFF2 are disconnected, the field effect tube V2 in the delay circuit is cut OFF, the field effect tube V1 in the main switching circuit is cut OFF, and no electric energy enters the electric equipment;
when the switching signals ON/OFF1 and ON/OFF2 are switched ON, the capacitor C2 is charged through the resistor R3, the voltage ON the capacitor C2 slowly rises, when the voltage ON the capacitor C2 reaches the lower limit of the opening voltage of the field effect transistor V2, the field effect transistor V2 starts to be conducted,
in the process that the field effect tube V2 in the delay circuit is slowly conducted, the resistors R1, R4 and R7 form a loop to GND, current starts to flow through, voltage drop is generated on the resistor R1, as the conduction degree of the field effect tube V2 in the delay circuit is deepened, the current flowing through the resistor R1, the resistor R4 and the resistor R7 to GND is gradually increased,
when the voltage drop generated on the resistor R1 reaches the lower limit of the starting voltage of the field effect tube V1, the field effect tube V1 starts to be conducted, current starts to flow through the field effect tube V1, the capacitor at the input end of the electric equipment is charged,
along with the deepening of the conduction degree of the field effect tube V1 in the main switch circuit, the charging current provided for the capacitor C1 through the field effect tube V1 is slowly increased until the charging is completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911192444.9A CN110854961B (en) | 2019-11-28 | 2019-11-28 | Power-on impact current suppression circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911192444.9A CN110854961B (en) | 2019-11-28 | 2019-11-28 | Power-on impact current suppression circuit |
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| Publication Number | Publication Date |
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| CN110854961A CN110854961A (en) | 2020-02-28 |
| CN110854961B true CN110854961B (en) | 2022-10-21 |
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| CN201911192444.9A Active CN110854961B (en) | 2019-11-28 | 2019-11-28 | Power-on impact current suppression circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116231607B (en) * | 2023-02-20 | 2023-12-05 | 北京中捷时代航空科技有限公司 | Transient current suppression circuit |
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| CN100342647C (en) * | 2004-03-23 | 2007-10-10 | 华为技术有限公司 | Circuit for positive power source inputting load electrifying slow starting |
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