CN106772405B - A kind of TDC laser distance measurement method based on FPGA - Google Patents
A kind of TDC laser distance measurement method based on FPGA Download PDFInfo
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- CN106772405B CN106772405B CN201510829584.8A CN201510829584A CN106772405B CN 106772405 B CN106772405 B CN 106772405B CN 201510829584 A CN201510829584 A CN 201510829584A CN 106772405 B CN106772405 B CN 106772405B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
- G01S17/02—Systems using the reflection of electromagnetic waves other than radio waves
- G01S17/06—Systems determining position data of a target
- G01S17/08—Systems determining position data of a target for measuring distance only
Abstract
The present invention proposes a kind of TDC laser distance measurement method based on FPGA, is completed jointly by FPGA and TDC；Wherein, TDC is used to calculate the time difference between commencing signal and pick-off signal；The TDC time difference is converted to range information for providing pulse signal by FPGA；Pulse signal is used for the commencing signal for driving laser emitter and carrying out time difference measurements as triggering TDC；The TDC is TDC-GP2.The present invention improves measurement accuracy, enhances data stability and can obtain range information in real time.
Description
Technical field
The invention belongs to laser or infrared isopulse ranging technology fields, and in particular to a kind of TDC laser based on FPGA
Distance measuring method can be applied to the anticollision of laser radar automobile intelligent, remotely sensed image etc..
Background technique
Laser ranging system is to calculate distance from the time between returning is emitted to by measurement laser.In such as Fig. 1
Shown in pulse type laser ranging ranging, time difference measurement becomes the factor for influencing entire measurement accuracy most critical.One
As complete time difference measurement there are two types of Basic Ways: first is that using programmable gate array, such as FPGA or CPLD, oneself programming are opened
Hair, second is that the general TDC chip of commodity in use.
Advantage using programmable gate array oneself programming time difference measurement is: can be completed at the same time the time on a single chip
Measurement, control and the subsequent processing for reading logic and measurement result, cost performance with higher, but exist and be difficult to overcome power supply
The influence of voltage and environmental temperature fluctuation is difficult to keep multi-channel measurement work consistency and the low disadvantage of measurement accuracy.
In contrast, general TDC chip can preferably solve disadvantages mentioned above.TDC chip measurement accuracy with higher,
Such as 1 kilometer of distance is measured, resolution requirement 1cm, then the resolution ratio of time interval measurement then requires up to 67ps, wherein
Time-to-digital converter chip TDC single measurement resolution ratio is 65ps.In addition, TDC chip power-consumption is low, integrated level is high, and measurement is flexible
Property it is high, perfect in shape and function, user are not required to it is to be understood that the inside of TDC chip realizes that time difference measurement can be realized in details.But it utilizes
General TDC chip realizes that time difference measurement also deposits control interface complexity again, needs that single-chip microcontroller or fpga logic is cooperated just to be able to achieve core
The disadvantages of configuration of piece and the reading of measurement result.
Summary of the invention
The present invention proposes a kind of TDC laser distance measurement method based on FPGA, improves measurement accuracy, enhances data stabilization
Property simultaneously can obtain range information in real time.
In order to solve the above technical problem, the present invention provides a kind of TDC laser distance measurement method based on FPGA, by FPGA and
TDC is completed jointly；Wherein, TDC is used to calculate the time difference between commencing signal and pick-off signal；FPGA is for providing pulse letter
Number, and the TDC time difference is converted into range information；Pulse signal is for driving laser emitter and carrying out as triggering TDC
The commencing signal of time difference measurements；The TDC is TDC-GP2.
Further, TDC is configured and controlled to TDC by FPGA and carries out time difference measurements.
Further, the pulse signal triggers TDC while driving laser transmitter projects laser；Photodetector one
Denier receives reflected impulse, and FGPA will turn off the channel STOP that signal inputs to TDC.
Further, target echo signal is introduced into FPGA, and FPGA gives TDC after echo-signal is converted to digital signal.
Further, the builtin voltage that the pin voltage Vio of TDC and power source voltage Vcc are all made of FPGA is powered, and Vio >
Vcc-0.5V.
Further, FPGA using three-stage state machine controls the dragging down of its SSN signal, draws high and read and write operation；Institute
Stating three-stage state machine, there are five states altogether, are respectively as follows: IDLE, READ_SSN, WRITE_SSN, READ_DATA and WRITE_
DATA；When idle, state machine is in IDLE state, when needing to write data toward TDC, first jumps to WRITE_ from IDLE state
SSN state drags down SSN signal；WRITE_DATA state is immediately hopped to later, and eight bit data is write into Serial Peripheral Interface (SPI)
The transmitter register of SPI is converted to Serial output by transmitter register displacement, is sent the data to using MOSI signal wire
TDC；Data jump to WRITE_SSN state after being sent completely again, draw high SSN signal.
Further, the method that FPGA configures TDC are as follows: FPGA carries out electrification reset to TDC write-in 50h；Then match
6 registers are set, 80000422h configuration register 0 is written into TDC by FPGA, so that TDC selects measurement range 1, carries out automatic
Calibration, after crystal oscillator powers on starting of oscillation always and select START signal rising edge trigger, STOP_1 signal failing edge triggering；FPGA
81014100h configuration register 1 is written to TDC, defining TDC internal calculation mode is first pulse with the channel STOP_1
Rising edge subtracts the rising edge of first pulse in the channel START；82E00000h configuration register 2 is written to TDC in FPGA, opens
All interrupt sources, so that the opens interrupters after TDC receives pick-off signal；83000000h and 84200000h is written to TDC in FPGA
Configuration register 3 and register 4；85080000h is written to TDC in FPGA, closes element of noise.
Further, FPGA controls the process that TDC carries out time difference measurements are as follows: FPGA carries out initialization survey to TDC write-in 70h
Amount makes TDC enter measurement preparation state；After the channel START and the channel STOP_1, which all receive pulse signal, completes measurement,
TDC generates interruption, and when INTN interrupt signal is low, TDC sends read command, and FPGA reads the read states register on MISO line
Data judge whether to overflow, if being read as 0200h, represent TDC spilling, and 70h is written to TDC to initialize in FPGA, if reading
It for 0009h, then represents in measurement range, continues that B0h is written to TDC, FPGA reads the data in register 0, is stored in OUT
In register, initial time difference data is obtained；For FPGA after running through a data, three-stage state machine returns to IDLE shape
State re-powers reset.
Further, TDC will be transferred to FPGA the time difference after the calculating of deadline difference, and FPGA is converted to the TDC time difference
Display is sent to show range information after range information.
Compared with prior art, the present invention its remarkable advantage is, it is contemplated that pulsed laser ranging is to TOA measurement accuracy
Requirement, and in order to reduce the measurement error that supply voltage and environmental temperature fluctuation generate as far as possible, when the present invention selects
Between number conversion chip TDC_GP2 carry out laser ranging, TDC_GP2 chip time difference measurement is from the commencing signal received to cut-off
Signal, the number for calculating the high-speed cells of generation obtain temporal information；The present invention, which proposes to cooperate in FPGA, realizes TDC-GP2 chip
Configuration, realize measurement result output and subsequent result processing.
Detailed description of the invention
Fig. 1 is TDC_GP2 laser distance measuring principle frame diagram.
Fig. 2 is TDC_GP2 time measurement system schematic diagram.
Fig. 3 is that the present invention is based on the schematic diagrams of the accurate time difference measurement of the TDC of FPGA.
Fig. 4 is SPI com-state machine flow chart.
Fig. 5 is TDC work flow diagram.
Fig. 6 is the initial distance of FPGA and adjusted range relational graph.
Specific embodiment
It is readily appreciated that, technical solution according to the present invention, in the case where not changing connotation of the invention, this field
Those skilled in the art can imagine the numerous embodiments of the TDC laser distance measurement method the present invention is based on FPGA.Therefore, with
Lower specific embodiment and attached drawing are only the exemplary illustrations to technical solution of the present invention, and are not to be construed as of the invention complete
Portion is considered as limitation or restriction to technical solution of the present invention.
Time difference in the present invention, between the measurement of the pulse time-of-flight based on TDC, i.e. commencing signal and pick-off signal
Measurement, by；FPGA and TDC are completed jointly.TDC be used for accurately calculate between the commencing signal and pick-off signal received when
Between it is poor；FPGA is used to provide the pulse signal of Laser emission, is also used to communicate with TDC, provides commencing signal and pick-off signal, and
The time difference information that TDC is surveyed is processed into range information, improves measurement accuracy.
Measuring principle are as follows: the pulse signal that FPGA is generated, while driving laser diode transmitting laser pulse, input
To the channel START of TDC, for triggering the time difference measurements between commencing signal and pick-off signal, once passed back from object
Reflected impulse reaches photodetector (receiving circuit), then pick-off signal is input to the channel STOP_1 of TDC by FGPA, this is constantly
Difference measurements are completed.Register configuration and time measurement control are carried out for TDC by FPGA, TDC was completed the time after measuring
Measurement result is returned to FPGA and carries out accurately calculating for distance by algorithm, to being shown result by RS-422 serial ports in electricity
On brain, entire pulsed laser ranging function is completed.
Measuring process are as follows:
Step 1, FPGA generates the channel START of commencing signal access TDC, and the echo-signal that range laser generates first passes through
Then FPGA accesses the channel STOP_1 of DC_GP2 chip, and configured the interface of FPGA and TDC.
Step 2, FPGA is by SPI protocol and TDC chip communication, to TDC power on and register configuration after, by measure when
Poor information is passed FPGA back again and is handled.
Step 3, FPGA is converted into actual range data using the time difference data that time gap transfer algorithm is surveyed TDC.
Step 4, FPGA shows actual range data on computers by RS-422 serial ports, completes entire ranging work.
START channel of the pulse signal as commencing signal access TDC is generated for step 1, such as Fig. 3, first FPGA, is used
In triggering TDC time difference measurement, while pulse signal accesses transmit circuit, generates laser.Laser encounters barrier, returning after reflection
Wave signal accesses the I/O port of FPGA, and the I/O port output of FPGA is connected to the channel STOP_1 of TDC as pick-off signal.Wherein, echo
Signal is not directly accessed TDC but first passes through after FPGA changes into digital signal and access TDC, may make commencing signal and cut-off in this way
Signal all generates corresponding delay by FPGA, and the time error of commencing signal access FPGA can be eliminated when subtracting each other inside TDC,
Improve measurement accuracy.And the rising edge rise time of the digital signal of the FPGA shorter measurement for being conducive to TDC.Finally,
During FPGA is connect with TDC, configured clock signal, INTN interrupt signal, RST reset signal and SPI serial data port (SSN,
SCK, MOSI, MISO).
In circuit, damage of the sink current for TDC chip in order to prevent, the pin voltage (Vio) and supply voltage of TDC
(Vcc) it needs to meet claimed below: firstly, power supply is compatible for TTL and CMOS level, needing to meet formula Vio > Vcc-0.5V,
Else if Vcc is excessive, it will form sink current, chip overheating may be made even to burn chip, therefore pin voltage Vio and electricity
Source voltage vcc all uses the builtin voltage 3.3V of FPGA, without separately designing power supply and meeting circuit requirement again.In addition, in order to
Avoid Interference from the power supply wire as far as possible, stabilized power supply value, the pin voltage Vio voltage filter capacitor of TDC need to be added to compare it is larger
Value, and it is more closer better from TDC.
For step 2, FPGA completes the configuration of system clock first, and the FPGA of dominant frequency 50M is separated by phaselocked loop
10M clock supplies TDC module；Then the configuration of SPI communication serial ports is completed, such as Fig. 4, FPGA are controlled using three-stage state machine
The dragging down of SSN signal is drawn high and read and write operation.State machine shares 5 states: IDLE, READ_SSN, WRITE_SSN,
READ_DATA and WRITE_DATA.When idle, state machine is in IDLE state, when needing to write data toward TDC, first from IDLE
State transition drags down SSN signal to WRITE_SSN state；WRITE_DATA state is immediately hopped to later, by 8 data
The transmitter register that (byte) writes serial peripheral equipment interface SPI is converted to Serial output by transmitter register displacement, benefit
It is sent to TDC with MOSI signal wire, entire step cycle n times (n is the byte number that need to be sent) jump to again after being sent completely
WRITE_SSN state draws high SSN, completes write operation.The process that data are read from TDC is similar with data are write, and only believes SSN
Number rear state transition is dragged down to READ_DATA state, TDC sends the data to FPGA using MISO signal wire, remaining is constant, complete
At read operation.In addition, READ_SSN state is used to read the value of SSN signal wire, do not need to use this state under normal conditions,
Only in view of the integrality of function remains this state.
After FPGA and TDC communication, by reading and writing configuration of the data completion to TDC, process such as Fig. 5 toward TDC internal register.
Firstly, FPGA carries out electrification reset to TDC module write-in 50h；Then 6 registers are configured, FPGA is written into TDC
80000422h configuration register 0 so that TDC select measurement range 1, calibrated automatically, after crystal oscillator powers on starting of oscillation always and
The triggering of START signal rising edge is selected, the triggering of STOP_1 signal failing edge meets short distance laser measurement requirement；FPGA is to TDC
81014100h configuration register 1 is written in module, so that defining TDC internal calculation mode is first with the channel STOP_1
The rising edge of pulse subtracts the rising edge of first pulse in the channel START；82E00000h configuration is written into TDC module by FPGA
Register 2 opens all interrupt sources with this, so that the opens interrupters after TDC receives pick-off signal, FPGA can be read at this time
Measured time difference signal；83000000h, 84200000h default configuration register 3 and 4 is written into TDC module by FPGA；
85080000h is written into TDC module by FPGA, element of noise is closed, so that measured value is not superimposed additional noise.FPGA later
Initialization survey is carried out to TDC module write-in 70h, so that TDC enters measurement preparation state.When the channel START and STOP_1 are logical
Road all receives pulse, and after completing measurement, TDC can generate interruption, and when judging that INTN interrupt signal is low, TDC, which is sent, reads life
It enables, FPGA reads the read states register data on MISO line, judges whether to overflow.If being read as 0200h, show that TDC overflows
Out, 70h is written to TDC module to initialize in FPGA, if being read as 0009h, represents in measurement range, continues to TDC mould
B0h is written in block, and FPGA reads the data in register 0, is stored in 32 OUT registers, when just obtaining initial at this time
Difference data.After running through a data, state machine returns to IDLE state, re-powers reset rather than returns to init state,
It can guarantee TDC test constantly in this way, be not in that TDC blocks the case where can not continuing measurement next pulse.
For step 3, since the exomonental frequency of FPGA is 1KHz, so every 1ms should receive a time difference data.
In order to accurately receive each data, in addition a DONE signal is set when receiving data, when only DONE signal is high,
Data in OUT register could be effectively.Temporal information measured by 32 bit registers can be converted to distance letter according to formula 1
Breath.
In formula (1), T is time data measured by 32 bit registers；V is the light velocity 3 × 108m/s；Divided by 2 be due to
What is measured is round-trip distance；It is since 16 are integer part before 32 bit registers divided by 65536, latter 16 are fractional part；
Divided by 109It is since the time obtained before is as unit of ns；250 be that TDC inside modules crystal oscillator 4M carrys out frequency of amendment.
After obtaining initial range information, pass through least square methodFitting amendment.Table 1 is measured in experiment
Part valid data, wherein first is classified as the initial apart from (s) of FPGA output, second is classified as reference distance (s0), third column
For the actual range (s ') after fitting amendment.
Table 1: experimental data
| s/m | s0/m | s′/m |
| 25 | 1.506 | 1.59 |
| 29 | 3.782 | 3.74 |
| 33 | 6.240 | 6.23 |
| 37 | 8.672 | 8.77 |
| 41 | 11.008 | 11.10 |
| 45 | 13.306 | 13.35 |
| 49.5 | 15.882 | 15.98 |
| 53 | 18.310 | 18.21 |
| 57 | 20.676 | 20.65 |
| 61 | 23.080 | 22.98 |
| 65 | 25.488 | 25.54 |
| 69 | 27.706 | 27.67 |
| 73 | 30.212 | 30.15 |
| 77 | 32.392 | 32.49 |
| 80.5 | 34.300 | 34.41 |
| 83.5 | 36.466 | 36.36 |
| 86.5 | 37.944 | 38.02 |
Through least square refinement, the value of the SOUT register output of FPGA is final distance values.
Synchronised clock RS_422 serial ports biography can be used in order to ensure the accuracy of data in transmission process for step 4
It is defeated.See Fig. 5.
For chip TDC-GP2, the speed of pulse signal is faster, and bandwidth is wider, then measurement accuracy is mutually deserved to get over
It is high.In addition, there are two measurement range, measurement range 1 and measurement ranges 2 for TDC-GP2 chip itself.The time of measurement range 1 surveys
Amount is about 0-270m for distance from 0ps-1.8us.The measurement range of measurement range 2 is all from 2 times of high-frequency clock
Phase, maximum distance was up to 20km to 4ms.The present invention is based on measurement ranges 1 to complete accurate time difference measurement.
Claims (5)
1. a kind of TDC laser distance measurement method based on FPGA, which is characterized in that completed jointly by FPGA and TDC；Wherein, TDC is used
Time difference between calculating commencing signal and pick-off signal；FPGA is converted to the TDC time difference for providing pulse signal
Range information；Pulse signal is used for the commencing signal for driving laser emitter and carrying out time difference measurements as triggering TDC；Institute
Stating TDC is TDC-GP2；
TDC is configured and controlled to TDC by FPGA and carries out time difference measurements；
FPGA controls the dragging down of its SSN signal using three-stage state machine, draws high and read and write operation；The three-stage state
There are five states altogether for machine, are respectively as follows: IDLE, READ_SSN, WRITE_SSN, READ_DATA and WRITE_DATA；When idle, shape
State machine is in IDLE state, when needing to write data toward TDC, first jumps to WRITE_SSN state from IDLE state, SSN is believed
It number drags down；WRITE_DATA state is immediately hopped to later, and the transmission that eight bit data writes serial peripheral equipment interface SPI is deposited
Device is converted to Serial output by transmitter register displacement, sends the data to TDC using MOSI signal wire；Data have been sent
It jumps to WRITE_SSN state again after, draws high SSN signal；
The method that FPGA configures TDC are as follows: FPGA carries out electrification reset to TDC write-in 50h；Then 6 registers are configured,
80000422h configuration register 0 is written into TDC by FPGA, so that TDC selects measurement range 1, is calibrated automatically, on crystal oscillator
After electricity starting of oscillation always and select START signal rising edge trigger, STOP_1 signal failing edge triggering；FPGA is written to TDC
81014100h configuration register 1, defining TDC internal calculation mode is to be subtracted with the rising edge of first pulse in the channel STOP_1
Remove the rising edge of first pulse in the channel START；82E00000h configuration register 2 is written to TDC in FPGA, opens all interruptions
Source, so that the opens interrupters after TDC receives pick-off signal；83000000h and 84200000h configuration deposit is written to TDC in FPGA
Device 3 and register 4；85080000h is written to TDC in FPGA, closes element of noise；
FPGA control TDC carry out time difference measurements process are as follows: FPGA to TDC write-in 70h carry out initialization survey, make TDC into
Enter to measure preparation state；After the channel START and the channel STOP_1, which all receive pulse signal, completes measurement, TDC generates interruption,
When INTN interrupt signal is low, TDC sends read command, and FPGA reads the read states register data on MISO line, and judgement is
No spilling represents TDC spilling if being read as 0200h, and FPGA is initialized to TDC write-in 70h, if being read as 0009h,
It representing in measurement range, continues that B0h is written to TDC, FPGA reads the data in register 0, is stored in OUT register,
Obtain initial time difference data；For FPGA after running through a data, three-stage state machine returns to IDLE state, re-powers
It resets.
2. the TDC laser distance measurement method based on FPGA as described in claim 1, which is characterized in that the pulse signal is driving
TDC is triggered while laser transmitter projects laser；Photodetector once receives reflected impulse, and FGPA will turn off signal
Input to the channel STOP of TDC.
3. the TDC laser distance measurement method based on FPGA as described in claim 1, which is characterized in that target echo signal is introduced into
FPGA, FPGA give TDC after echo-signal is converted to digital signal.
4. the TDC laser distance measurement method based on FPGA as described in claim 1, which is characterized in that the pin voltage Vio of TDC with
Power source voltage Vcc is all made of the builtin voltage power supply of FPGA, and Vio > Vcc-0.5V.
5. the TDC laser distance measurement method based on FPGA as described in claim 1, which is characterized in that TDC is calculated in deadline difference
After will be transferred to FPGA the time difference, FPGA, which is converted to the TDC time difference, send display to show range information after range information.
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| CN107315177B (en) * | 2017-07-06 | 2018-09-28 | 深圳乐创信息通讯技术有限公司 | Laser ranging circuit, laser ranging system, preventing collision of vehicles collision device and its control method |
| CN111033312A (en) * | 2017-08-31 | 2020-04-17 | 深圳市大疆创新科技有限公司 | Delay time calibration for optical distance measurement devices and associated systems and methods |
| CN109870702A (en) * | 2019-03-28 | 2019-06-11 | 河北镭族光电科技有限公司 | A kind of distant-range high-precision laser ranging system and distance measuring method based on TDC |
| CN114137558B (en) * | 2022-02-07 | 2022-04-29 | 杭州宏景智驾科技有限公司 | Control method and device for improving laser radar precision and laser radar system |
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