WO2021036071A1

WO2021036071A1 - Pulse signal generation device and method

Info

Publication number: WO2021036071A1
Application number: PCT/CN2019/122491
Authority: WO
Inventors: 于龙; 李春雨; 陈俊
Original assignee: 武汉光迅科技股份有限公司
Priority date: 2019-08-23
Filing date: 2019-12-02
Publication date: 2021-03-04
Also published as: CN110514404A

Abstract

Disclosed in embodiments of the present invention are a pulse signal generation device and method. The device comprises a clock module, an FPGA module and a control module. The clock module is used to provide a reference clock signal to the FPGA module. The control module is used to acquire a configuration parameter and send the configuration signal to the FPGA module. The FPGA module is used to generate, on the basis of the reference clock signal, a pulse signal corresponding to the configuration parameter.

Description

Pulse signal generating device and method

Cross-references to related applications

This application is filed based on a Chinese patent application with the application number 201910786531.0 and the filing date on August 23, 2019, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated into this application by reference.

Technical field

This application relates to the field of integrated circuit technology, in particular to a pulse signal generating device and method.

Background technique

Optical Time Domain Reflectometer (OTDR) is used to monitor the performance of optical fibers to determine optical fiber fusion splices, connectors, or breaks. The optical pulse signal is injected into the optical fiber input end, and then the optical fiber reflected light signal is collected at the input end at a high speed to obtain a series of sampling point data, each of which represents the reflected light power value of a certain point in the optical fiber. The distance to the input end is taken as the abscissa, and the reflected light power value of each sampling point is taken as the ordinate to obtain the relationship between the fiber attenuation and the length, thereby reflecting the performance of the fiber under test. Two important parameters reflecting the performance of the fiber under test are blind zone and dynamic range, because the size of the blind zone determines the measurement accuracy of the OTDR, and the size of the dynamic range determines the measurement distance of the OTDR. However, the pulse width sent by the OTDR directly affects the dynamic range, distance resolution, and blind zone technical indicators. For example, the narrower the pulse width, the smaller the blind zone, the higher the measurement accuracy of the OTDR; the wider the pulse width, the greater the dynamic range, the OTDR's The farther the measuring distance is. However, none of the existing pulse generators can generate a pulse signal with a continuously adjustable dynamic range, and cannot meet the current OTDR measurement requirements.

Summary of the invention

In view of this, the embodiments of the present application provide a pulse signal generating device and method in order to solve at least one problem existing in the prior art.

In order to achieve the foregoing objectives, the technical solutions of the embodiments of the present application are implemented as follows:

In the first aspect, an embodiment of the present application provides a pulse signal generating device, the device includes: a clock module, an FPGA module, and a control module; wherein,

The clock module is used to provide a reference clock signal to the Field Programmable Gate Array (FPGA) module;

The control module is used to obtain configuration parameters and send the configuration parameters to the FPGA module;

The FPGA module is configured to generate a pulse signal corresponding to the configuration parameter based on the reference clock signal.

In an optional implementation manner, the FPGA module includes at least one of the following:

The first sub-module is used to generate the first type of pulse signal;

The second sub-module is used to generate the second type of pulse signal;

The third sub-module is used to generate the third type of pulse signal;

Wherein, the first type of pulse signal, the second type of pulse signal and the third type of pulse signal represent different types of pulse signals.

In an optional implementation manner, the FPGA module further includes:

A phase-locked loop, the phase-locked loop is connected to the clock module, and is used to generate multiple clock signals based on the reference clock signal, wherein each clock signal has a different frequency.

In an optional implementation manner, the FPGA module further includes:

The multiplexer is used to select one periodic signal from at least two periodic signals as the reference signal, and output the reference signal.

In an optional implementation manner, the first sub-module is connected to the multiplexer; wherein,

The multiplexer sends the reference signal to the first sub-module, and the first sub-module generates the first-type pulse signal according to the reference signal.

In an optional implementation manner, the first sub-module includes: a delay module and a trigger, the delay module is connected to the trigger; wherein,

The multiplexer sends the reference signal to the delay module and the trigger respectively, and the delay module sends the delay signal to the trigger based on the reference signal, and the trigger according to The reference signal and the delayed signal generate the first-type pulse signal.

In an optional implementation manner, the second sub-module is connected to the phase-locked loop and the multiplexer; the multi-channel clock signal generated by the phase-locked loop at least includes The clock signal and the second clock signal; among them,

The phase-locked loop sends the first clock signal and the second clock signal to the second sub-module, and the multiplexer sends the reference signal to the second sub-module; The second sub-module generates the second type pulse signal according to the first clock signal, the second clock signal, and the reference signal.

In an optional implementation manner, the third sub-module is connected to the phase-locked loop and the multiplexer; the multi-channel clock signal generated by the phase-locked loop includes at least the first channel The clock signal and the third clock signal; among them,

The phase-locked loop sends the first clock signal and the third clock signal to the third sub-module, and the multiplexer sends the reference signal to the third sub-module; The third sub-module generates the third type of pulse signal according to the first clock signal, the third clock signal, and the reference signal.

In an optional implementation manner, the FPGA module further includes:

A level conversion module, which is connected to the third sub-module, and is used to convert the interface level of the third sub-module into a single-ended level.

In an optional implementation manner, the device further includes:

A drive module, which is connected to the FPGA module and is used to convert the pulse signal generated by the FPGA module into a large current drive signal.

In a second aspect, an embodiment of the present application provides a method for generating a pulse signal, and the method includes:

Generate a reference clock signal;

Get configuration parameters;

A pulse signal corresponding to the configuration parameter is generated based on the reference clock signal.

In an optional embodiment, the pulse signal includes at least one of the following: a first type of pulse signal, a second type of pulse signal, and a third type of pulse signal;

The pulse signal generation device and method provided by the embodiments of the present application include: a clock module, an FPGA module, and a control module; wherein the clock module is used to provide a reference clock signal to the FPGA module; The control module is configured to obtain configuration parameters and send the configuration parameters to the FPGA module; the FPGA module is configured to generate pulse signals corresponding to the configuration parameters based on the reference clock signal. In this way, the embodiment of the present application does not need to add additional analog devices outside the FPGA, and directly utilizes the internal resources of the FPGA to generate the pulse signal.

Description of the drawings

Figure 1 is a simplified schematic diagram of a typical OTDR system in the prior art;

2 is a schematic structural diagram of an implementation manner of a pulse signal generating device provided by an embodiment of this application;

FIG. 3 is a schematic structural diagram of another implementation manner of a pulse signal generating device provided by an embodiment of the application; FIG.

FIG. 4 is a schematic structural diagram of an implementation manner of a first submodule provided by an embodiment of this application;

FIG. 5 is a schematic structural diagram of another implementation manner of the first submodule provided by an embodiment of the application;

FIG. 6 is a schematic structural diagram of a second sub-module provided by an embodiment of the application;

FIG. 7 is a schematic structural diagram of a third sub-module provided by an embodiment of the application;

FIG. 8 is a schematic structural diagram of a temperature compensation module provided by an embodiment of the application;

FIG. 9 is a schematic flowchart of a method for generating a pulse signal according to an embodiment of the application.

detailed description

In order to have a more detailed understanding of the characteristics and technical content of the embodiments of the present application, the implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings. The attached drawings are for reference and explanation purposes only, and are not used to limit the embodiments of the present application.

Laser ranging uses a laser as a light source for distance measurement. The measurement principle is that light travels back and forth between the distance measuring device and the object to be measured. Half of the product of the speed of light and the round-trip time is the distance between the distance measuring device and the object to be measured. distance. Laser ranging generally has two ways to measure distance: pulse method and phase method. The process of pulse distance measurement is as follows: the laser light emitted by the range finder is reflected by the object to be measured and then received by the range finder, and the range finder records the round-trip time of the laser at the same time. Laser ranging has the advantages of strong anti-interference ability, short measurement time, large range, high accuracy, etc., and has been widely used in many fields, such as robotics, vehicle-mounted fields, surveying and mapping radars, etc.

As a transmission medium, optical fiber is widely used in optical fiber communication. The uniformity, defects, breakage, and coupling of the optical fiber will affect the performance and quality of communication. OTDR can be used to measure fiber attenuation, connector loss, fiber fault location, and to understand the loss distribution along the length of the fiber. It is an indispensable tool in the construction, maintenance and monitoring of optical cables. The basic principle of OTDR is to use the method of analyzing the backscattered light or forward scattered light in the optical fiber to measure the optical fiber transmission loss due to scattering, absorption and other reasons and the structural loss caused by various structural defects. OTDR measurement is carried out by emitting light pulses into the optical fiber and then receiving the return light. When the light pulse is transmitted in the optical fiber, it will be scattered and reflected due to the nature of the optical fiber, the connector, the joint, the bending or other similar events. Part of the scattering and reflection will return to the OTDR, and they will be used as time or curve fragments at different positions in the fiber. From the time it takes to transmit the signal to the return signal, and then to determine the speed of the light in the fiber, the distance between the distance measuring device and the measured point can be calculated. A typical OTDR system is simplified as shown in Figure 1. After the light pulse is sent out, it is transmitted in the air. If it encounters an obstacle or a target, the reflected light enters the receiving system. If you measure the time between the pulse edges of the two beams of light, multiply by the speed of light and divide by 2, you can get the detection distance. The two important parameters of OTDR measurement are blind zone and dynamic range, because the size of the blind zone determines the measurement accuracy of the OTDR, and the size of the dynamic range determines the measurement distance of the OTDR. However, the pulse width sent by the OTDR directly affects the dynamic range, distance resolution, and blind zone technical indicators. For example, the narrower pulse width, the smaller the blind zone, the higher the measurement accuracy of the OTDR; the wider the pulse width, the greater the dynamic range, the OTDR's The farther the measuring distance is.

The pulse width of the electrical pulse directly affects the generation of the light pulse, thereby determining the measurement distance and accuracy of the OTDR. However, in the prior art, it is difficult to obtain narrow pulses and wide pulses at the same time, especially when multiple pulse signals need to be output. The pulse signal generated by the traditional pulse generator has a small dynamic range and low resolution (≤250ps), and most of it is a single-channel signal output. Therefore, the traditional pulse generator cannot meet the current OTDR measurement requirements.

To this end, the following technical solutions of the embodiments of the present application are proposed.

An embodiment of the present application provides a pulse signal generating device. FIG. 2 is a schematic structural diagram of an implementation manner of the pulse signal generating device provided by an embodiment of the application. As shown in FIG. 2, the device includes: a clock module 11, an FPGA Module 12 and control module 13; among them,

The clock module 11 is used to provide a reference clock signal to the FPGA module 12;

The control module 13 is configured to obtain configuration parameters and send the configuration parameters to the FPGA module 12;

The FPGA module 12 is configured to generate a pulse signal corresponding to the configuration parameter based on the reference clock signal.

The FPGA module 12 includes at least one of the following:

The first sub-module 121 is used to generate a pulse signal of the first type;

The second sub-module 122 is used to generate a second type of pulse signal;

The third sub-module 123 is used to generate a third type of pulse signal;

The FPGA module 12 further includes:

A phase-locked loop 124, which is connected to the clock module 11, is configured to generate multiple clock signals based on the reference clock signal, wherein each clock signal has a different frequency.

In the embodiment of the present application, the phase-locked loop 124 may divide or multiply the frequency of the reference clock signal to generate multiple clock signals, wherein each clock signal has a different frequency.

The FPGA module 12 further includes:

The multiplexer 125 is configured to select one periodic signal from at least two periodic signals as a reference signal, and output the reference signal.

In the embodiment of the present application, the multiplexer 125 may be used to select one of the external periodic signal and the internal periodic signal as the reference signal, and output the reference signal.

In practical applications, the external periodic signal is a periodic signal set by a user, and the internal periodic signal is a periodic signal generated internally by the pulse signal generating device.

The first sub-module 121 is connected to the multiplexer 125; wherein,

The multiplexer 125 sends the reference signal to the first sub-module 121, and the first sub-module 121 generates the first-type pulse signal according to the reference signal.

FIG. 4 is a schematic structural diagram of an implementation manner of a first sub-module provided by an embodiment of the application. As shown in FIG. 4, the first sub-module 121 includes a delay module 1211 and a trigger 1212. The module 1211 is connected to the trigger 1212; wherein,

The multiplexer 125 sends the reference signal to the delay module 1211 and the trigger 1212 respectively, and the delay module 1211 sends a delay signal to the trigger 1212 based on the reference signal, The trigger 1212 generates the first-type pulse signal according to the reference signal and the delay signal.

In the embodiment of the present application, the flip-flop 1212 may be a D flip-flop, the multiplexer 125 sends the reference signal to the D flip-flop, and the reference signal serves as the setting of the D flip-flop The delay module 1211 sends a delay signal to the D flip-flop based on the reference signal. The delay signal is used as the input signal of the clock terminal of the D flip-flop. The input signal of the set terminal and the input signal of the clock terminal generate the first-type pulse signal.

The second sub-module 122 is connected to the phase-locked loop 124 and the multiplexer 125; the multiple clock signals generated by the phase-locked loop 124 at least include the first clock signal and the second clock signal. Clock signal; where,

The phase-locked loop 124 sends the first clock signal and the second clock signal to the second sub-module 122, and the multiplexer 125 sends the reference signal to the second sub-module 122. Sub-module 122; The second sub-module 122 generates the second type of pulse signal according to the first clock signal, the second clock signal, and the reference signal.

The third sub-module 123 is connected to the phase-locked loop 124 and the multiplexer 125; the multiple clock signals generated by the phase-locked loop 124 at least include the first clock signal and the third clock signal. Clock signal; where,

The phase locked loop 124 sends the first clock signal and the third clock signal to the third sub-module 123, and the multiplexer 125 sends the reference signal to the third sub-module 123. Sub-module 123; The third sub-module 123 generates the third-type pulse signal according to the first clock signal, the third clock signal, and the reference signal.

The FPGA module 12 further includes:

A level conversion module 126, which is connected to the third sub-module 123, and is configured to convert the interface level of the third sub-module 123 to a single-ended level.

It should be noted that the interface level of the third sub-module 123 is a differential level, which does not match the single-ended level of the driving module 14. Therefore, the third sub-module 126 needs to be The interface level of the module 123 is converted into a single-ended level matching the driving module 14.

The pulse signal generating device further includes:

The driving module 14 is connected to the FPGA module 12 and used to convert the pulse signal generated by the FPGA module 12 into a large current driving signal.

In actual application, the driving module 14 is respectively connected to the first sub-module 121, the second sub-module 122 and the third sub-module 123 in the FPGA module 12, and is used to connect the first sub-module 121, the second sub-module 121 and the third sub-module 123. The pulse signals generated by the second sub-module 122 and the third sub-module 123 are respectively converted into high-current drive signals.

It should be noted that the FPGA module 12 in the embodiment of the application includes three sub-modules, and the three sub-modules respectively generate different types of pulse signals. Therefore, in the embodiment of the application, three drive modules 14 are provided, and each drive module Correspond to and connect to a sub-module.

It should be noted that the pulse signal generating device provided in the embodiment of the present application can be applied to a laser ranging system and an OTDR system to generate a pulse signal required by the system.

FIG. 3 is a schematic structural diagram of another implementation manner of a pulse signal generating device provided by an embodiment of the application. As shown in FIG. 3, the device includes: a clock module 11, an FPGA module 12, and a control module 13; among them,

In practical applications, the clock module 11 may be a constant temperature crystal oscillator source, and the constant temperature crystal oscillator source is used to provide a stable and accurate reference clock signal.

In practical applications, the FPGA module 12 and the control module 13 constitute a system on chip (System on Chip, SOC), and the control module 13 may be a central processing unit (CPU) embedded in the SOC. Wherein, the CPU module can perform functions such as external communication, obtaining configuration parameters, and program loading.

The FPGA module 12 includes at least one of the following:

The first sub-module 121 is used to generate a pulse signal of the first type;

The second sub-module 122 is used to generate a second type of pulse signal;

The third sub-module 123 is used to generate a third type of pulse signal;

In the embodiment of the present application, the first sub-module 121 may be a look-up table sub-module, the second sub-module 122 may be a high-speed IO interface sub-module, and the third sub-module 123 may be a dedicated SERDES interface sub-module . Then the first type of pulse signal is the pulse signal generated by the look-up table sub-module; then the second type of pulse signal is the pulse signal generated by the high-speed IO interface sub-module; then the third type of pulse signal is the dedicated SERDES interface sub-module Pulse signal generated by the module. Wherein, the first type of pulse signal, the second type of pulse signal, and the third type of pulse signal may represent pulse signals with different pulse width ranges.

The FPGA module 12 further includes:

The first sub-module 121 is connected to the multiplexer 125; wherein,

In the embodiment of the present application, the first submodule 121 includes: a delay module 1211 and a trigger 1212, and the delay module 1211 is connected to the trigger 1212; wherein,

In the embodiment of the present application, the second sub-module 122 is connected to the phase-locked loop 124 and the multiplexer 125; the multiple clock signals generated by the phase-locked loop 124 include at least the first A clock signal and a second clock signal; among them,

In the embodiment of the present application, the second sub-module 122 may include a high-speed IO pulse generation logic 1221 and a high-speed IO interface 1222, and the high-speed IO pulse generation logic 1221 is connected to the high-speed IO interface 1222. Wherein, the high-speed IO pulse generation logic 1221 is used to generate a digital signal based on the first clock signal and the reference signal for input to the high-speed IO interface 1222.

In the embodiment of the present application, the first clock signal generated by the phase-locked loop 124 may be a slow clock signal with a frequency of hundreds of MHz, and the first clock signal may be used as the second sub-module 122 Reference clock signal; the second clock signal generated by the phase-locked loop 124 may be a high-speed clock signal with a frequency of 1 GHz, and the second clock signal may be used as an internal clock signal of the second sub-module 122. The second sub-module 122 generates the second-type pulse signal according to the reference clock signal of the second sub-module 122, the internal clock signal of the second sub-module 122, and the reference signal.

In the embodiment of the present application, the third sub-module 123 is connected to the phase-locked loop 124 and the multiplexer 125; the multi-channel clock signal generated by the phase-locked loop 124 includes at least the first A clock signal and a third clock signal; among them,

The phase-locked loop 124 sends the first clock signal and the third clock signal to the third sub-module 123, and the multiplexer 125 sends the reference signal to the third sub-module 123. Sub-module 123; The third sub-module 123 generates the third-type pulse signal according to the first clock signal, the third clock signal, and the reference signal.

In the embodiment of the present application, the third sub-module 123 may include a dedicated SERDES pulse generating logic 1231 and a dedicated SERDES interface 1232, and the dedicated SERDES pulse generating logic 1231 is connected to the dedicated SERDES interface 1232. Wherein, the dedicated SERDES pulse generating logic 1231 is used to generate a digital signal based on the first clock signal and the reference signal to input to the dedicated SERDES interface 1232.

In the embodiment of the present application, the first clock signal generated by the phase-locked loop 124 may be a slow clock signal with a frequency of hundreds of MHz, and the first clock signal may be used as the third sub-module 123 Reference clock signal; the third clock signal generated by the phase-locked loop 124 can be a very high-speed clock signal with a frequency of tens of GHz, and the third clock signal can be used as the internal clock signal of the third sub-module 123 . The third sub-module 123 generates the third-type pulse signal according to the reference clock signal of the third sub-module 123, the internal clock signal of the third sub-module 123, and the reference signal.

The FPGA module 12 further includes:

It should be noted that the interface level of the third sub-module 123 is a differential level, which does not match the single-ended level of the driving module 14. Therefore, the third sub-module 126 needs to be used to convert the third sub-module 126 to the single-ended level. The interface level of the module 123 is converted to a single-ended level matching the driving module 14.

As shown in FIG. 3, the pulse signal generating device further includes:

The pulse signal generating device further includes:

The communication interface 15 is used to establish a communication connection with a processor or a computer to set configuration parameters. The configuration parameters are the parameters required when the pulse signal generator generates the pulse signal, for example, the delay unit (search Table) Number, pulse period, pulse width, etc.

The pulse signal generating device further includes:

The storage module 16 is used to store program codes and logic codes.

The pulse signal generating device further includes:

The power supply module 17 is used to adjust the input power supply voltage to the working voltage required by the pulse signal generating device.

The pulse signal generating device further includes:

The temperature detection module 18 is used to provide temperature information to the FPGA module 12.

FIG. 5 is a schematic structural diagram of another implementation manner of the first submodule provided by an embodiment of the application. As shown in FIG. 5, the first submodule 521 includes: N lookup tables 5211, lookup table multiplexers 5212 and a D flip-flop 5213, the N look-up tables 5211 are connected to the look-up table multiplexer 5212, and the look-up table multiplexer 5212 is connected to the D flip-flop 5213.

In the embodiment of the present application, the multiplexer 125 sends the reference signal to the N look-up tables 5211 and the D flip-flop 5213 respectively. As shown in FIG. 5, the reference signal is divided into two channels, one connected to one channel. At the set end of the D flip-flop 5213, one way is connected to the clock end of the D flip-flop 5213 through N cascaded look-up tables. N look-up tables form the delay chain of the first sub-module 521, and each look-up table can output one look-up table delay signal after the reference signal passes through a look-up table, and each look-up table delay signal is connected to the look-up table multiplexer 5212 The lookup table multiplexer 5212 is used to select one of the lookup table delay signals from the N lookup table delay signals as the delay signal, and output the delay signal to the clock terminal of the D flip-flop 5213. In practical applications, the number of look-up tables with delay can be dynamically configured, wherein the delay time of the reference signal passing through a look-up table is T _lut , and the reference signal passing the delay time of the look-up table multiplexer 5212 T _mux , the maximum delay time of the reference signal passing through the N look-up tables and look-up table multiplexer 5212 is

In other words, the maximum delay time of the delayed signal input to the clock terminal of the D flip-flop 5213 is

In practical application, the input terminal of the D flip-flop 5213 is fixed at low level. When the signal (reference signal) of the set terminal of the D flip-flop 5213 changes from low level to high level, the D flip-flop 5213 The set terminal of 5213 is first effective. At this time, the output signal of the D flip-flop 5213 is high. Since the signal of the clock terminal of the D flip-flop 5213 is a signal output after the delay of the N look-up tables and the look-up table multiplexer 5212, the signal of the clock terminal of the D flip-flop 5213 lags behind all the signals. The signal of the set end of the D flip-flop 5213. When the signal (delay signal) of the clock terminal of the D flip-flop 5213 changes from low level to high level, the clock terminal of the D flip-flop 5213 is valid. At this time, the output signal of the D flip-flop 5213 is low. Level, the D flip-flop 5213 generates a pulse signal (the output signal changes from high level to low level), and the width of the pulse signal is equal to the delay time of the N look-up tables and the number of the look-up tables. The sum of the delay time of the way selector 5212. In the embodiment of the present application, the look-up table multiplexer 5212 may select the output signal of one of the look-up tables from the N look-up tables as the delayed signal for output, so as to dynamically adjust the look-up table through which the reference signal passes. That is, the look-up table multiplexer 5212 can change the delay time from the reference signal to the clock terminal of the D flip-flop. _{The delay time T lut of} the look-up table determines the precision of the pulse width, so that the pulse width precision of the first sub-module 521 can reach tens of ps, and the resources of the look-up table are relatively abundant. Therefore, the first sub-module 521 It is suitable for generating pulse signals with a pulse width of less than 100ns and a resolution of less than 100ps, and can output dozens of pulse signals at the same time.

FIG. 6 is a schematic structural diagram of a second sub-module provided by an embodiment of the application. As shown in FIG. 6, the second sub-module 622 includes a high-speed IO pulse generation logic 6221 and a high-speed IO interface 6222. The high-speed IO pulse generation The logic 6221 is connected to the high-speed IO interface 6222.

In the embodiment of the present application, the high-speed IO pulse generation logic 6221 is configured to generate a digital signal based on the reference clock signal of the second sub-module 622 and the reference signal for input to the high-speed IO interface 6222, The digital signal is a periodic parallel digital signal, for example, the digital signal may be 0000110000_0000000000_..._0001100000_0000000000_.... Among them, "1" represents the high level, the number of "1" represents the pulse width, and the interval between two discontinuous "1" represents the pulse period. The high-speed IO interface 6222 is used to convert parallel digital signals into pulse signals. The clock signal frequency of the high-speed IO interface 6222 is a multiple of the clock signal frequency of the high-speed IO pulse generation logic 6221. In actual application, the clock signal of the high-speed IO interface 6222 may be the internal clock signal of the second sub-module 622, and the clock signal of the high-speed IO pulse generation logic 6221 may be the reference of the second sub-module 622 Clock signal. The width of the pulse signal output by the high-speed IO interface 6222 is determined by the clock signal of the high-speed IO interface 6222. The minimum width of the pulse signal is the width of the clock signal of the high-speed IO interface 6222. The resolution is also the width of the clock signal of the high-speed IO interface 6222, the width of the clock signal of the high-speed IO interface 6222 is about 1 ns, and the frequency of the clock signal of the high-speed IO interface 6222 is about 1 GHz. Therefore, the first The two sub-modules 622 are suitable for generating pulse signals with a pulse width of 1 ns to 1 ms. The pulse signals have a large dynamic range and can output dozens of pulse signals at the same time.

FIG. 7 is a schematic structural diagram of a third sub-module provided by an embodiment of the application. As shown in FIG. 7, the third sub-module 723 includes: a dedicated SERDES pulse generation logic 7231 and a dedicated SERDES interface 7232. The dedicated SERDES pulse generation The logic 7231 is connected to the dedicated SERDES interface 7232.

In the embodiment of the present application, the dedicated SERDES pulse generation logic 7231 is configured to generate a digital signal based on the reference clock signal of the third sub-module 723 and the reference signal to input to the dedicated SERDES interface 7232, the The digital signal is a periodic parallel digital signal, for example, the digital signal may be 0000110000_0000000000_..._0001100000_0000000000_.... Among them, "1" represents the high level, the number of "1" represents the pulse width, and the interval between two discontinuous "1" represents the pulse period. The dedicated SERDES interface 7232 is used to convert parallel digital signals into pulse signals. The frequency of the clock signal of the dedicated SERDES interface 7232 is a multiple of the frequency of the clock signal of the dedicated SERDES pulse generating logic 7231. In practical applications, the clock signal of the dedicated SERDES interface 7232 may be the internal clock signal of the third sub-module 723, and the clock signal of the dedicated SERDES pulse generation logic 7231 may be the reference of the third sub-module 723 Clock signal. The width of the pulse signal output by the dedicated SERDES interface 7232 is determined by the clock signal of the dedicated SERDES interface 7232, the minimum width of the pulse signal is the width of the clock signal of the dedicated SERDES interface 7232, and the minimum of the pulse signal The resolution is also the width of the clock signal of the dedicated SERDES interface 7232, the width of the clock signal of the dedicated SERDES interface 7232 is about 100 ps, and the frequency of the clock signal of the dedicated SERDES interface 7232 is about 10 GHz. Therefore, the first The three sub-modules 723 are suitable for generating pulse signals with a pulse width of hundreds of ps to 1 ms. The pulse signal has a large dynamic range and can output several pulse signals at the same time.

FIG. 8 is a schematic structural diagram of a temperature compensation module provided by an embodiment of the application. As shown in FIG. 8, an embodiment of the application also provides a temperature compensation module based on the temperature detection module 18, and the temperature compensation module includes: The detection module 18, the storage module 16, and the communication interface 15.

As the delay time will vary greatly under different ambient temperatures, such as when the ambient temperature rises, the delay time will also be prolonged. Therefore, the delay time (or delay chain) needs to be compensated according to the current ambient temperature. In the embodiment of the present application, a temperature compensation coefficient table is configured through the communication interface 15, and the temperature compensation coefficient table is stored in the storage module 16 in the form of a storage table. The current environmental temperature is detected by the temperature detection module 18, and the detected environmental temperature information is sent to the FPGA module 12. The FPGA module 12 queries the temperature compensation coefficient table according to the environmental temperature information, so as to obtain the compensation coefficient corresponding to the environmental temperature. The FPGA module 12 obtains the number of actual delay units (look-up table) at the current ambient temperature based on the compensation coefficient and the number of delay units (look-up table) currently set. The number is compensated to improve the accuracy of pulse width.

FIG. 9 is a schematic flowchart of a method for generating a pulse signal according to an embodiment of the application. As shown in FIG. 9, the method for generating a pulse signal includes the following steps:

Step 901: Generate a reference clock signal.

Step 902: Obtain configuration parameters.

In the embodiment of the present application, the clock module generates a reference clock signal and sends the reference clock signal to the FPGA module, and the control module obtains configuration parameters based on the communication interface, and sends the configuration parameters to the FPGA module. The FPGA module.

Step 903: Generate a pulse signal corresponding to the configuration parameter based on the reference clock signal.

In the embodiment of the present application, the FPGA module generates a pulse signal corresponding to the configuration parameter based on the reference clock signal.

The pulse signal generation method provided by the embodiment of the present application generates a reference clock signal, obtains configuration parameters, and generates a pulse signal corresponding to the configuration parameter based on the reference clock signal. In this way, the embodiment of the present application does not need to add additional analog devices outside the FPGA, and directly utilizes the internal resources of the FPGA to generate the pulse signal.

It can be understood that the storage module in the embodiment of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), and electrically available Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory. The volatile memory may be random access memory (Random Access Memory, RAM), which is used as an external cache. By way of exemplary but not restrictive description, many forms of RAM are available, such as static random access memory (Static RAM, SRAM), dynamic random access memory (Dynamic RAM, DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (Double Data Rate SDRAM, DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (Enhanced SDRAM, ESDRAM), Synchronous Link Dynamic Random Access Memory (Sync Link DRAM, SLDRAM) ) And Direct Rambus RAM (DRRAM). The storage modules of the methods described herein are intended to include, but are not limited to, these and any other suitable types of storage.

The control module may be an integrated circuit chip with signal processing capabilities. In the implementation process, the steps of the above method can be completed by the integrated logic circuit of the hardware in the control module or the instructions in the form of software. The above-mentioned control module may be a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (ASIC), an FPGA or other programmable logic device, a discrete gate or transistor logic device, a discrete Hardware components. The methods, steps, and logical block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like. The steps of the method disclosed in the embodiments of the present application can be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, registers. The storage medium is located in the storage module, and the control module reads the information in the storage module, and completes the steps of the above method in combination with its hardware.

It can be understood that the embodiments described herein can be implemented by hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application specific integrated circuits (ASIC), digital signal processor (Digital Signal Processing, DSP), digital signal processing equipment (DSP Device, DSPD), programmable Logic device (Programmable Logic Device, PLD), FPGA, general-purpose processor, controller, microcontroller, microprocessor, other electronic units for performing the functions described in this application, or a combination thereof.

For software implementation, the technology described herein can be implemented by modules (such as procedures, functions, etc.) that perform the functions described herein. The software code can be stored in the storage module and executed by the control unit. The storage module can be implemented in the control unit or outside the control unit.

The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application. Should be covered within the scope of protection of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, the appearances of "in one embodiment" or "in an embodiment" in various places throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not correspond to the embodiments of the present application. The implementation process constitutes any limitation. The serial numbers of the foregoing embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

It should be noted that in this article, the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, It also includes other elements not explicitly listed, or elements inherent to the process, method, article, or device. If there are no more restrictions, the element defined by the sentence "including a..." does not exclude the existence of other identical elements in the process, method, article, or device that includes the element.

In the several embodiments provided in this application, it should be understood that the disclosed method and device can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, such as: multiple units or components can be combined, or It can be integrated into another system, or some features can be ignored or not implemented. In addition, the coupling, or direct coupling, or communication connection between the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms. of.

The units described above as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, the functional units in the embodiments of the present application can be all integrated into one processing module, or each unit can be individually used as a unit, or two or more units can be integrated into one unit; the above-mentioned integration The unit can be implemented in the form of hardware, or in the form of hardware plus software functional units. A person of ordinary skill in the art can understand that all or part of the steps in the above method embodiments can be implemented by a program instructing relevant hardware. The foregoing program can be stored in a computer readable storage medium. When the program is executed, it is executed. Including the steps of the foregoing method embodiment; and the foregoing storage medium includes: removable storage devices, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks, etc. A medium that can store program codes.

The methods disclosed in the several method embodiments provided in this application can be combined arbitrarily without conflict to obtain new method embodiments.

The features disclosed in the several product embodiments provided in this application can be combined arbitrarily without conflict to obtain new product embodiments.

The features disclosed in the several method or device embodiments provided in this application can be combined arbitrarily without conflict to obtain a new method embodiment or device embodiment.

Claims

A pulse signal generating device, the device comprising: a clock module, a field programmable logic gate array FPGA module and a control module; wherein,

The clock module is used to provide a reference clock signal to the FPGA module;

The control module is used to obtain configuration parameters and send the configuration parameters to the FPGA module;

The FPGA module is configured to generate a pulse signal corresponding to the configuration parameter based on the reference clock signal.
The device according to claim 1, wherein the FPGA module comprises at least one of the following:

The first sub-module is used to generate the first type of pulse signal;

The second sub-module is used to generate the second type of pulse signal;

The third sub-module is used to generate the third type of pulse signal;

Wherein, the first type of pulse signal, the second type of pulse signal and the third type of pulse signal represent different types of pulse signals.
The device according to claim 2, wherein the FPGA module further comprises:

A phase-locked loop, the phase-locked loop is connected to the clock module, and is used to generate multiple clock signals based on the reference clock signal, wherein each clock signal has a different frequency.
The device according to claim 3, wherein the FPGA module further comprises:

The multiplexer is used to select one periodic signal from at least two periodic signals as the reference signal, and output the reference signal.
The device according to claim 4, wherein the first sub-module is connected to the multiplexer; wherein,

The multiplexer sends the reference signal to the first sub-module, and the first sub-module generates the first-type pulse signal according to the reference signal.
The device according to claim 5, wherein the first sub-module comprises: a delay module and a trigger, and the delay module is connected to the trigger; wherein,

The multiplexer sends the reference signal to the delay module and the trigger respectively, and the delay module sends the delay signal to the trigger based on the reference signal, and the trigger according to The reference signal and the delayed signal generate the first-type pulse signal.
The device according to claim 4, wherein the second sub-module is connected to the phase-locked loop and the multiplexer; the multi-channel clock signal generated by the phase-locked loop includes at least the first A clock signal and a second clock signal; among them,

The phase-locked loop sends the first clock signal and the second clock signal to the second sub-module, and the multiplexer sends the reference signal to the second sub-module; The second sub-module generates the second type pulse signal according to the first clock signal, the second clock signal, and the reference signal.
The device according to claim 4, wherein the third sub-module is connected to the phase-locked loop and the multiplexer; the multiple clock signals generated by the phase-locked loop include at least the first A clock signal and a third clock signal; among them,

The phase-locked loop sends the first clock signal and the third clock signal to the third sub-module, and the multiplexer sends the reference signal to the third sub-module; The third sub-module generates the third type of pulse signal according to the first clock signal, the third clock signal, and the reference signal.
The device according to claim 4, wherein the FPGA module further comprises:

A level conversion module, which is connected to the third sub-module, and is used to convert the interface level of the third sub-module into a single-ended level.
A pulse signal generation method, wherein the method includes:

Generate a reference clock signal;

Get configuration parameters;

A pulse signal corresponding to the configuration parameter is generated based on the reference clock signal.