CN204089753U - A kind of many groups 8 road direct-flow signal generators - Google Patents
A kind of many groups 8 road direct-flow signal generators Download PDFInfo
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- CN204089753U CN204089753U CN201420545665.6U CN201420545665U CN204089753U CN 204089753 U CN204089753 U CN 204089753U CN 201420545665 U CN201420545665 U CN 201420545665U CN 204089753 U CN204089753 U CN 204089753U
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Abstract
The utility model provides a kind of many groups 8 road direct-flow signal generators.It comprises monolithic FPGA and 8 road direct current signal generating units, FPGA is built-in interface unit, clock generation unit and amplitude control logic unit.Multiple 8 road direct current signal generating units of the present utility model can organize 8 road direct current signals more; Each road range parameter is all independently arranged, and microprocessor arranges once just Absorbable organic halogens; Analog circuit is without integrated DAC.As produced 24 road direct current signals, only use 1 three tunnel 2 to select 1 analog switch, 38 are selected 1 variable connector, and 4 four high guaily units, also use some resistance, electric capacity, inductance, hardware cost is low.Microprocessor Zhi Xuduimei road direct current signal code value is arranged once, fixes with regard to Ke Ranggai road direct-flow signal voltage value.
Description
(1) technical field
The utility model relates to a kind of multipath CD signal generator, particularly a kind of many groups of 8 road direct-flow signal generators of low cost.
(2) background technology
Multipath CD signal is generally used for offset compensation in electronic circuit system, gain controls, and as the DC signal source of PLC, as the control voltage of multichannel voltage controlled oscillator, therefore can have a wide range of applications.
For the ease of providing multi-channel DC voltage, ADI company utilizes its denseDAC technology to be proposed multichannel DAC, and monolithic DAC can reach 40 passages at most, but such major path number DAC chip is expensive, temporarily for being used widely.
For producing multi-channel DC signal, the normal technology adopted has two kinds: one to be allow several multichannel DAC concurrent working, and to realize the port number of required direct current signal, this method chip hardware cost is high; Two Shi Yongji road DAC are by the port number of timesharing technology of sharing expansion direct current signal, and this just needs microprocessor ceaselessly to rewrite DAC code value.
(3) summary of the invention
The purpose of this utility model is to provide a kind of Zhi Xuduimei road direct current signal code value to arrange once, with regard to the many groups of 8 road direct-flow signal generators that Ke Ranggai road direct-flow signal voltage value is fixing.
The purpose of this utility model is achieved in that it comprises monolithic FPGA and 8 road direct current signal generating units, FPGA is built-in interface unit, clock generation unit, amplitude control logic unit; Interface unit connects microprocessor, clock generation unit comprises frequency multiplication of phase locked loop unit and binary system frequency unit, external crystal-controlled oscillation connects frequency multiplication of phase locked loop unit, frequency multiplication of phase locked loop unit connects binary system frequency unit, binary system frequency unit and interface unit are connected amplitude control logic unit respectively, and binary system frequency unit and amplitude control logic unit are connected 8 road direct current signal generating units respectively.
The utility model also has some technical characteristics like this:
1, described amplitude control logic unit comprises the 8 road range parameter setting units, 8 connected successively and selects 1 bus data switch and data comparator, interface unit connects 8 road range parameter setting units, binary system frequency unit connects 8 respectively and selects 1 bus data switch and data comparator, and data comparator connects 8 road direct current signal generating units;
2,8 described road direct current signal generating units comprise 2 and select 1 analog switch, active low-pass filter, 8 to select 1 variable connector and 8 sampling holders, amplitude control logic unit output amplitude logical signal PWM drives 2 to select the input of 1 analog switch to connect positive and negative benchmark respectively, 2 select the common port of 1 analog switch to connect active low-pass filter, the output signal of active low-pass filter connects the common port that 8 select 1 variable connector, under channel selecting signal CH [2..0] and sampling allow signal OUTE to control, 8 select 8 of 1 variable connector outputs to connect 8 sampling holders respectively.
In interface unit of the present utility model, the inside parallel bus BUS that the universal serial bus from microprocessor is converted to, to arrange each channel DC signal amplitude.In clock generation unit, outside inputs crystal oscillator after frequency multiplication of phase locked loop unit as system clock, system clock produces array Fout through binary system frequency unit, the highest 4 the selection signal controlling CH [2..0] as 8 passages of Fout and permission signal OUTE, the frequency of Fout low level determination amplitude logical signal.In amplitude control logic unit, internal bus BUS arranges 8 direct current signal range parameters, and channel selecting signal CH [2..0] controls 8 and selects 1 bus data switch, and 8 data characterizing direct current signal amplitude are become 1 variable data stream; Fout low level compares with variable data stream, and the output (being less than or equal to defeated logical relation) of data comparator is an amplitude logical signal PWM.In 8 road direct current signal generating units, amplitude logical signal PWM controls 2 and selects 2 of 1 analog switch inputs to connect positive and negative benchmark respectively, 2 select 1 analog switch common port to connect active low-pass filter, and the output signal periodically-varied of active low-pass filter, timesharing characterizes 8 direct current signal amplitudes.The output signal of active low-pass filter connects the common port that 8 select 1 variable connector, under channel selecting signal CH [2..0] and sampling allow signal OUTE to control, 8 outputs of analog switch connect 8 sampling hold circuits (by resistance, electric capacity and in-phase amplifier) respectively, form 8 tunnel independent direct current signal V
0 ~ 7.
Multiple 8 road direct current signal generating units of the present utility model can organize 8 road direct current signals more; Each road range parameter is all independently arranged, and microprocessor arranges once just Absorbable organic halogens; Analog circuit is without integrated DAC.As produced 24 road direct current signals, only use 1 three tunnel 2 to select 1 analog switch, 38 are selected 1 variable connector, and 4 four high guaily units, also use some resistance, electric capacity, inductance, hardware cost is low.Microprocessor Zhi Xuduimei road direct current signal code value is arranged once, fixes with regard to Ke Ranggai road direct-flow signal voltage value.
(4) accompanying drawing explanation
Fig. 1 is 3 group of 8 road direct-flow signal generator structured flowchart of the present utility model.
Fig. 2 is the built-in amplitude control logic unit theory diagram of FPGA.
Fig. 3 is 8 road direct current signal generating unit theory diagrams.
(5) embodiment
The utility model below in conjunction with the drawings and specific embodiments is further described:.
Composition graphs 1,3 group of 8 road direct-flow signal generator i.e. 24 road direct current signal circuit for generatings are made up of FPGA and analog circuit two parts, two parts are by 3 amplitude logical signal PWM [2..0], and 3 channel selecting signal CH [2..0], 1 sampling allow signal OUTE to be connected.
Composition graphs 1, the present embodiment FPGA adopts EP2C5T144, outside input crystal oscillator is the system clock Fsys of 280MHz after digital phase-locked loop frequency multiplication, Fsys produces array Fout [27..0] through counter frequency division, Fout [27..25] is as the selection signal controlling CH [2..0] of 8 passages, Fout [24] allows signal OUTE as sampling, and Fout [15..0] determines the frequency of amplitude logical signal.
Fig. 2 is amplitude control logic unit theory diagram, microprocessor arranges 8 road 16Bit range parameters, channel selecting signal CH [2..0] drives 8 to select 1 bus data switch, and the data being 16Bit by 8 width characterizing direct current signal amplitude become the variable data stream that 1 width is 16Bit; Fout [15..0] compares with variable data stream, and the output that is less than or equal to of data comparator is amplitude logical signal PWM.
Be 8 road direct current signal generating unit theory diagrams in figure 3, its operation principle is discussed at utility model content part, and 3 group of 8 channel DC signal generating unit composition produces whole 24 road direct current signals.
Whole analog circuit is by 1 74HC4053,3 74HC4051,7 TL084, and 1 TL082,1 LM336-5V, some resistance, inductance, electric capacity form, and without integrated DAC, hardware cost is low.Operational amplifier adopts positive and negative 15V power supply, and variable connector chip adopts positive and negative 5V power supply, and positive and negative 5V power supply is realized through voltage stabilizing regulation output by positive and negative 15V power supply, and LM336-5V normally works and exports after following is positive benchmark, is negative benchmark after positive benchmark is anti-phase.
Claims (3)
1. organize 8 road direct-flow signal generators more, it is characterized in that: it comprises monolithic FPGA and 8 road direct current signal generating units, FPGA is built-in interface unit, clock generation unit, amplitude control logic unit; Interface unit connects microprocessor, clock generation unit comprises frequency multiplication of phase locked loop unit and binary system frequency unit, external crystal-controlled oscillation connects frequency multiplication of phase locked loop unit, frequency multiplication of phase locked loop unit connects binary system frequency unit, binary system frequency unit and interface unit are connected amplitude control logic unit respectively, and binary system frequency unit and amplitude control logic unit are connected 8 road direct current signal generating units respectively.
2. one according to claim 1 organizes 8 road direct-flow signal generators more, it is characterized in that: described amplitude control logic unit comprises the 8 road range parameter setting units, 8 connected successively and selects 1 bus data switch and data comparator, interface unit connects 8 road range parameter setting units, binary system frequency unit connects 8 respectively and selects 1 bus data switch and data comparator, and data comparator connects 8 road direct current signal generating units.
3. one according to claim 1 and 2 organizes 8 road direct-flow signal generators more, it is characterized in that: 8 described road direct current signal generating units comprise 2 and select 1 analog switch, active low-pass filter, 8 select 1 variable connector and 8 sampling holders, amplitude control logic unit output amplitude logical signal PWM drives 2 to select the input of 1 analog switch to connect positive and negative benchmark respectively, 2 select the common port of 1 analog switch to connect active low-pass filter, the output signal of active low-pass filter connects the common port that 8 select 1 variable connector, under channel selecting signal CH [2..0] and sampling allow signal OUTE to control, 8 select 8 of 1 variable connector outputs to connect 8 sampling holders respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420545665.6U CN204089753U (en) | 2014-09-23 | 2014-09-23 | A kind of many groups 8 road direct-flow signal generators |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420545665.6U CN204089753U (en) | 2014-09-23 | 2014-09-23 | A kind of many groups 8 road direct-flow signal generators |
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| CN204089753U true CN204089753U (en) | 2015-01-07 |
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| CN201420545665.6U Expired - Fee Related CN204089753U (en) | 2014-09-23 | 2014-09-23 | A kind of many groups 8 road direct-flow signal generators |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021036071A1 (en) * | 2019-08-23 | 2021-03-04 | 武汉光迅科技股份有限公司 | Pulse signal generation device and method |
-
2014
- 2014-09-23 CN CN201420545665.6U patent/CN204089753U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021036071A1 (en) * | 2019-08-23 | 2021-03-04 | 武汉光迅科技股份有限公司 | Pulse signal generation device and method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150107 Termination date: 20150923 |
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| EXPY | Termination of patent right or utility model |