CN103063917B - High-precision phase and frequence measuring system - Google Patents
High-precision phase and frequence measuring system Download PDFInfo
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- CN103063917B CN103063917B CN201210593724.2A CN201210593724A CN103063917B CN 103063917 B CN103063917 B CN 103063917B CN 201210593724 A CN201210593724 A CN 201210593724A CN 103063917 B CN103063917 B CN 103063917B
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Abstract
Provided is a high-precision phase and frequence measuring system. An input signal conditioning circuit in the system respectively converts a channel A signal, a channel B signal and a reference clock signal from external input into pulse signals and sends the pulse signals to a field programmable gata array (FPGA) circuit. The FPGA circuit makes a rough count measurement on the time interval between the treated channel A signal and the channel B signal and generates two interpolating pulses at the beginning and the end of the time interval and respectively outputs two interpolating pulses into an integral analog extension circuit. Two integral pulses sent back from the integral artificial extension circuit are received, a count measurement on the pulses which are sent back are respectively made, combining the count measurement and delay correction parameters to obtain phases and frequencies of the A signal and the B signal through calculations, and the phases and frequencies are sent to a host computer through an asynchronous serial communication circuit. The integral extension circuit forms an integral voltage according to the interpolating pulses, compares, reforms and sends the integral voltage to the FPGA circuit. The asynchronous serial communication circuit is used for communicating with host computer serial ports and a parameter storing circuit is used for storing delay correction parameters.
Description
Technical field
The present invention relates to high-precision phase position and frequency measurement technology, on the basis of the thick count measurement method of tradition, comprehensive employing double interpolation method and integration type simulation stretching method, the time interval to be measured is divided into three parts and carries out precision measurement respectively, make the Measurement Resolution in the time interval reach 50ps, measurement range can cover 50ps to the time interval long arbitrarily.This technology, in traditional telecommunication path engineering practice field, atomic nuclear physics theoretical research field, especially at space flight military technological fields such as Modern Laser range measurement system, NAVSTAR, has widely and the application of key.
Background technology
Phase place and frequency are the important physical parameters of two of signal, all require to carry out precision measurement to them in modern times a lot of engineering practice and theoretical research field.The measurement of phase place refers to the measurement to two signal phase difference time interval t.Frequency refers to the periodicity of periodic signal process in the unit interval, is often designated as f, is expressed from the next:
In formula: n is the periodicity of periodic signal process in time interval t, if t=1s, then frequency representation is per second through n cycle, i.e. nHz.
In traditional measuring method, be all the method adopting conventional counting to the measurement of phase place and frequency.When measuring phase place, directly counted by the time interval of reference clock to phase differential, count results is multiplied by the cycle of reference clock, is namely phase difference measurements.When survey frequency, calculate the periodicity n of measured signal experience with reference clock, then divided by time interval t, just obtain the frequency f of periodic signal.
Easily find out, the measuring method of traditional direct counting, maximum source of error has the ± Randomized Quantizing error of 1 count value between the measured time interval and reference clock.For phase measurement, measuring error is:
Δt＝±1T
0
In formula, Δ t is phase differential time interval measurement error, T
0for the cycle of reference clock.If for 10MHz reference clock, namely the measuring error in the phase differential time interval is ± 100ns.This is concerning high-precision phase measurement requires, error is too large.To the relative error of frequency measurement be:
In formula, Δ f is frequency error value, and f is actual frequency values, f
0the frequency of reference clock.If for 10MHz reference clock, the relative error of frequency measurement is 2 × 10
-7.
As from the foregoing, traditional conventional count measurement method, brings very large error term.And measuring accuracy will be improved, must improve constantly reference clock frequency, reference clock frequency is higher, and the quantization error that ± 1 count value is brought will be less.
In modern time interval measurement technology, also has a kind of time-to-digit converter based on digital tapped delay line method, but this element height depends on the manufacturing process of integrated circuit, fabrication error can bring measuring error item, and the change of environment temperature is very large on lag line impact, also brings larger measuring error item.The measuring accuracy of usual this technology can only reach 500ps, and measurement range is very little.
In modern high-acruracy survey application, usually require that the measuring error in the phase differential time interval is less than 1ns, the relative error of frequency measurement is less than 1 × 10
-9.The conventional thick method of counting of tradition has obviously been difficult to meet such accuracy requirement.And although modern digital formula tapped delay line measuring technique can meet some application demand to a certain extent, to the rigors of manufacturing process and working environment, make this technology measuring error in actual applications comparatively large, and cost is higher.In addition, the measurement range that tapped delay line technology is less is also difficult to meet a lot of measurement and applies requirement.
Summary of the invention
Technology of the present invention is dealt with problems: overcome the conventional thick method of counting measuring accuracy of tradition too low, and measuring accuracy depends on the problem of reference clock frequency size, provides a kind of high-precision phase position and frequency measuring system.
Technical solution of the present invention: high-precision phase position and frequency measuring system, comprises input signal conditioning circuit, FPGA circuit, integration type simulation extension circuit, Asynchronous Serial Communication Circuit and parameter storage circuit;
Input signal conditioning circuit: the pulse signal that the passage a-signal, pass B signal and the reference clock signal that are inputted outside change CMOS fiduciary level respectively into delivers to FPGA circuit;
FPGA circuit: thick count measurement t is carried out to the time interval between the passage a-signal after the process of input signal conditioning circuit input and pass B signal
1, and in the beginning in the described time interval and ending place generation two interpolation pulses, and two interpolation pulses are exported respectively to integration type simulation extension circuit; Receive two integrated pulses that integration type simulation extension circuit returns, and respectively count measurement t is carried out to the pulse returned
2and t
3, the Deferred Correction parametric t that incorporating parametric memory circuit stores
d, calculate the exact time duration t=t in the time interval between A, B signal
1+ t
2-t
3+ t
d, and then calculate phase place t and the frequency f of A, B signal, and result of calculation is sent to host computer by Asynchronous Serial Communication Circuit;
Integration type simulation extension circuit: in each interpolation pulse interval, integrating capacitor is charged, after interpolation end-of-pulsing, integrating capacitor is discharged, the charging and discharging process of integrating capacitor forms integral voltage, and integral voltage is compared the integrated pulse that shaping obtains standard CMOS level, and this integrated pulse is delivered to FPGA circuit;
Asynchronous Serial Communication Circuit: FPGA circuit is connected with host computer serial ports, for host computer serial communication, the state of real-time report input signal, phase place and frequency computation part result;
Parameter storage circuit: be connected with FGAP circuit, for storage delay corrected parameter.
Described integration type simulation extension circuit comprises speed-sensitive switch device, JFET integration extensor, high-speed comparator, charge reference level circuit and electric discharge reference level circuit;
Speed-sensitive switch device is according to the interpolation pulse of input, control charge reference level circuit to charge to the integrating capacitor in JFET integration extensor in interpolation pulse interval, after interpolation end-of-pulsing, discharged to electric discharge reference level circuit by integrating capacitor, the charging and discharging process of integrating capacitor forms integral voltage and exports to high-speed comparator; Integral voltage is compared the integrated pulse being shaped to standard CMOS level and delivers to FPGA circuit by high-speed comparator.
Described electric discharge compares at least 1000 times with the time constant of charging.
The generation of two described interpolation pulses is respectively: between the rising edge of signal A and the rising edge of reference clock or negative edge, form an interpolation pulse; Second interpolation pulse is formed between the rising edge of signal B and the rising edge of reference clock or negative edge.
Described interpolation pulse width engineering is generally T
0~ 2T
0, T
0for the one-period of reference clock.
Described integrating capacitor engineering generally chooses 100pF-1nF.
Principle of the present invention: the present invention to the Technology Precision of signal phase and frequency, principle is first all unified in time domain to the Technology of Precision Measurement in the time interval.Then by double interpolation measuring principle and integrating analog extension principle to row precision measurement during the time interval, thus realization is to the high-acruracy survey of phase place and frequency.The concrete principle of the present invention is discussed below:
As previously mentioned, to the measurement of phase place, be namely the measurement to the signal phase difference time interval, and can be obtained by the frequency departure measured between it and reference clock the measurement of signal frequency, frequency departure is defined by following formula:
In formula, Δ f is frequency departure, and f is signal frequency, f
0for reference clock frequency.In fact, the frequency departure that just can obtain between signal and reference clock by asking the phase variation rate of signal, this is because frequency departure is the basic reason causing signal phase to change, and therefore can obtain frequency departure by following formula:
In formula, Δ t is phase changing capacity, and T is measuring period.From above formula, just can be obtained the frequency values of signal by the variable quantity measuring the signal phase difference time interval in a period of time, thus realize the high-acruracy survey to signal phase.Therefore, to the high-acruracy survey of signal phase and frequency, the precision measurement to the time interval can be first converted into.
Front already described, due to the uncertainty of phase place between input signal and reference clock, the count value quantization error that conventional phase and frequency measurement method maximum error source are ± 1 word, namely ± 1T
0.This quantization error is the fraction part that the thick count measurement of tradition does not detect.And the use of interpolater, be exactly in order to precision measurement fraction part.
Double interpolation ratio juris of the present invention such as institute Fig. 2 shows.During double interpolation method measuring intervals of TIME, first t is divided into 3 partial separation: a long interval coarse counter measures t in real time
1; Two remaining short intervals are respectively at the beginning t of t
2with end t
3place.Wherein, t
2and t
3be generally T
0~ 2T
0, these two periods of time intervals, the fraction part measured exactly was also the maximum source of error of traditional measurement method relative to the thick counting integer measuring method of tradition.Therefore, the time interval t measured by interpolation method is expressed by following formula:
t＝t
1+t
2-t
3
In formula, thick count measurement t
1=NT
0, t
2and t
3it is the time interval between the rising edge of input signal A and signal B and second nearest reference clock rising edge.To t
1measurement use traditional coarse counter, to t
2and t
3two-part measurement, then adopt following integration type simulation stretching method to carry out precision measurement respectively.
Integration type simulation extension ratio juris of the present invention as shown in Figure 3.To the time interval t of aforementioned interpolation
2or t
3when adopting integration type simulation stretching method to measure, in interpolation pulse interval τ, to integrating capacitor charging, after interpolation end-of-pulsing, integrating capacitor is externally discharged, if discharge time and duration of charging are than being k, then discharge time is k τ.Therefore, the molded breadth of integrated pulse width is (k+1) τ, that is: the integrated pulse width obtained that extends is interpolation pulse width (k+1) times.Usual definition K=k+1 is the extension factor, and the Measurement Resolution of defining integration formula simulation stretching method:
The circuit theory of integration type simulation stretching method of the present invention as shown in Figure 4.The charging and discharging process of JFET integrator is control by high-speed analog switch.In charging process, charge reference level is 5V, and charging resistor is 1K ohm, and therefore charging current is 5mA; In discharge process, electric discharge datum is-2.5V, and discharge resistance is 1M ohm, and therefore discharge current is-2.5 μ A.Therefore the charge and discharge time than k is:
Extension factor K=k+1=2001 times ≈ 2000 times.Be the reference clock of 10MHz for frequency, Measurement Resolution is:
And Measurement Resolution is T in classic method
0, be 10MHz reference clock to frequency, resolution only has 100ns.Therefore adopt integration type simulation stretching method, measuring accuracy is greatly improved.
Front already described, frequency departure is defined by following formula:
In formula, Δ t is phase changing capacity, and the Measurement Resolution of Δ t described above can reach 50ps, and therefore, for measurement period T=1s, the Measurement Resolution of Δ f just can reach 5 × 10
-11.Measurement period T is longer, and the measuring accuracy of frequency f is higher.
High-precision phase position of the present invention and frequency measurement technology are on the thick method of counting basis of tradition, and comprehensive interpolation method and the integration type simulation stretching method of adopting expands measuring accuracy.Due to the use of coarse counter, the measurement range in the time interval is very large; Due to the use of integrating analog stretching method, the Measurement Resolution of phase place and frequency reaches very high.In addition, when measuring at every turn, all can carry out primary calibration, eliminate the measuring error that in measuring process, variation of ambient temperature is brought.
The present invention is compared with existing measuring technique, and advantage is:
(1) comprehensive advanced double interpolation method and the integration type of adopting simulates stretching method, and reach 50ps to the Measurement Resolution in the time interval, the measurement far away higher than classic method is differentiated.
(2) to the measuring technique of frequency, improve measuring accuracy by the method for indirect inspection phase changing capacity, make frequency measurement accuracy reach 5 × 10
-11above.
(3) measuring method of the present invention is on the basis of the conventional method of counting of tradition, adopt double interpolation method, and the measurement range in the time interval is guaranteed, and can carry out precision measurement to 50ps to any long-time interval.
(4) possessing self-calibrating capabilities, all carry out primary calibration operation when each measurement, eliminating the change of ambient temperature to measuring the error brought.
(5) compared with modern digital formula tapped delay line technology, measuring method of the present invention not by the impact of integrated circuit fabrication process, and has higher Measurement Resolution.
(6) there is lower hardware cost advantage.
Accompanying drawing explanation
Fig. 1 is general principles block diagram of the present invention;
Fig. 2 is double interpolation method schematic diagram of the present invention;
Fig. 3 is integration type of the present invention simulation stretching method schematic diagram;
Fig. 4 is integration type of the present invention simulation extension circuit theory diagrams;
Fig. 5 is input signal conditioning circuit diagram of the present invention;
Fig. 6 is FPGA circuit diagram of the present invention;
Fig. 7 is integration type of the present invention simulation stretching method circuit diagram;
Fig. 8 is serial communication circuit figure of the present invention;
Fig. 9 is FPGA program flow diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing and example, the present invention is elaborated, specific as follows:
As shown in Figure 1, hardware circuit of the present invention forms primarily of input signal conditioning circuit 1, FPGA circuit 2, integration type simulation extension circuit 3, serial communication circuit 4 and parameter storage circuit 5.
One, input signal conditioning circuit 1
Passage a-signal, pass B signal and reference clock signal that input signal conditioning circuit 1 and outside input are connected, and three road input signals are all transformed into respectively the pulse signal of CMOS fiduciary level, give FPGA circuit 2.Every road specifically comprises resistors match/attenuator circuit and ac/dc coupled circuit and high-speed comparator circuit.What the impedance matching of input signal and decay adopted is ∏ type resistor network.The coupling of input signal is optional chooses friends stream coupling scheme or DC coupling mode.The core devices that high speed comparator circuit adopts is MAX961 ultrahigh-speed comparator.
As shown in Figure 5, be the input modulate circuit figure of passage a-signal, pass B signal is identical with it with the input modulate circuit of reference clock signal.Input end coupling in input signal conditioning circuit 1 adopts ∏ type resistor network, both can meet the impedance matching of input signal, also suitably can decay to signal volt value.Maxim MAX961 selected by high-speed comparator.The object of input signal conditioning circuit is pulse signal input signal being converted to standard CMOS level.
Two, FPGA circuit 2
As shown in Figure 1, in FPGA circuit 2, fpga chip is the core processor as primary control logic, asynchronous serial communication logic, parameter stored logic and precision measurement algorithm realization.FPGA circuit specifically comprises fpga chip 21 and FPGA configuring chip 22.Fpga chip 21 internal logic program is mainly divided into following components: coarse counter and double interpolation device logic 211, pulse are extended and thin counter logic 212, phase place and frequency calculation processing unit 213 and asynchronous serial communication logic 214.Major function: the passage a-signal after the process input input signal conditioning circuit 1 and the time interval between pass B signal carry out thick count measurement t
1, and generate an interpolation pulse respectively in the beginning in the described time interval and ending, and two interpolation pulses are exported respectively to integration type simulation extension circuit 3; Receive two integrated pulses that integration type simulation extension circuit 3 returns, and respectively count measurement is carried out to the pulse returned, the Deferred Correction parameter that incorporating parametric memory circuit 5 stores, calculate the exact time duration in the time interval between A, B signal, and then calculate phase place and the frequency of A, B signal, and result of calculation is sent to host computer by Asynchronous Serial Communication Circuit (4).
Coarse counter in the inner coarse counter of FPGA circuit 2 and double interpolation device logic 211 carries out thick count measurement to the time interval between signal A, B, and measurement result is designated as t
1, and by double interpolation device this period of time interval and ending place generate interpolation pulse and (as shown in Figure 2, between the rising edge of signal A and the rising edge of reference clock or negative edge, form an interpolation pulse; Second interpolation pulse is formed between the rising edge of signal B and the rising edge of reference clock or negative edge; Interpolation pulse width engineering is generally T
0~ 2T
0, T
0for the one-period of reference clock.), and carry out scale amplifying by interpolation pulse feeding integration type simulation extension circuit 3, then carry out count measurement by the integrated pulse after pulse extension and thin counter logic 212 pairs of broadenings, measurement result is designated as t
2, t
3.First phase place and frequency calculation processing unit 213 read Deferred Correction parametric t from parameter storage circuit 5
d, and according to formula t=t
1+ t
2-t
3+ t
dobtain the exact time duration (phase place namely between signal AB) in the time interval between A, B signal, and then determine the phase changing capacity Δ t under measurement period T, then according to following formula determination frequency f:
Result of calculation is also sent to Asynchronous Serial Communication Circuit 4 by asynchronous serial communication logic 214 by phase place and frequency calculation processing unit 213.Result of calculation packing is formed frame, in the form of frames correspondence with foreign country by asynchronous serial communication logic 214.
As shown in Figure 6, FPGA circuit be Survey control, the core processing circuit that realizes of the access of serial communication, parameter and phase place and frequency algorithm.The power module of FPGA circuit uses the PTH04070WAD (N1, N2 in figure) of TI company.Fpga chip D1 adopts Cyclone II series EP2C20F256I8, and it has the advantage of Large Copacity logical block, low cost; Configuring chip D2 adopts EPCS4I8.
FPGA program circuit as shown in Figure 9, after power-up initializing, first detects the state of input signal and reference clock, if no signal or reference clock input, then produce alerting signal, intuitively shown by LED light, and signal condition is reported host computer by serial communication.Otherwise start the fixed delay corrected parameter read in EEPROM, initialization survey, line time interval measurement of going forward side by side, phase place and frequency calculation processing unit, according to signal phase difference time interval measurement result, calculate phase place and the frequency of signal in real time.After power-up initializing, the serial ports of serial communication logic receives the data that buffering FIFO constantly receives host computer transmission, and carries out Frame Synchronization Test and command parameter decoding, and respective logic module is delivered in the order received and parameter.The transmission link of serial communication is by phase place and frequency measurement, input signal and reference clock status information simultaneously, and packing forms transmission frame, sends into serial ports and sends buffering FIFO, be uploaded to host computer by serial port circuit.
Three, integration type simulation extension circuit 3
Integration type simulation extension circuit 3 major function: in an interpolation pulse interval, integrating capacitor is charged, after interpolation end-of-pulsing, integrating capacitor is discharged, the charging and discharging process of integrating capacitor forms integral voltage, integral voltage is compared the integrated pulse being shaped to standard CMOS level, and this integrated pulse is delivered to FPGA circuit 2;
Integration type simulation extension circuit 3 comprises speed-sensitive switch device 31, JFET integration extensor 32, high-speed comparator 33, charge reference level circuit 34 and electric discharge reference level circuit 35; Speed-sensitive switch device 31 is according in the interpolation arteries and veins of input, control charge reference level circuit 34 to charge to the integrating capacitor in JFET integration extensor 32 in interpolation pulse interval, after interpolation end-of-pulsing, discharged to electric discharge reference level circuit 35 by integrating capacitor, the charging and discharging process of integrating capacitor forms integral voltage and exports to high-speed comparator 33; Integral voltage is compared the integrated pulse being shaped to standard CMOS level and delivers to FPGA circuit 2 by high-speed comparator 33.
As shown in Figure 7, the core devices of integration type simulation extension circuit 3 comprises datum chip LM336, speed-sensitive switch device MAX4614, JFET operational amplifier TLE2072I and high-speed comparator MAX9142.
5V reference level circuit in integration type simulation extension circuit 3 is generated, for the charging process of JFET integration extensor 32 by LM336-5 (in figure D16) chip;-2.5V reference level circuit is generated, for the discharge process of JFET integration extensor 32 by LM336-2.5 (in figure D20) chip.
Charging resistor (in figure R214 and R215) and discharge resistance (in figure R230 and R231), should select that high frequency performance is good, temperature coefficient function admirable, the resistance that precision is higher.The ratio of charging resistor resistance and discharge resistance resistance is not more than 1: 1000, and such as, charging resistor resistance is designed to 1k ohm, and discharge resistance resistance is designed to 1M ohm.
Speed-sensitive switch device 31 controls the charging and discharging process to JFET integration extensor 32, in interpolation pulse interval, high-speed analog switch conducting, 5V datum charges to the integrating capacitor (C148 and C149 in figure) in JFET integration extensor; After interpolation end-of-pulsing, high-speed analog switch is closed, and the p-2.5V datum of integrating capacitor discharges.The MAX4614 of Maxim selected by speed-sensitive switch device 31, and be characterized in that four-way, switching speed are fast, conducting resistance is very little, closedown leakage current is also very little.
JFET integration extensor 32 is cores of integration type simulation extension circuit, and JFET integration extensor 32 produces integral voltage in above-mentioned charge and discharge process, and its oscillogram is as shown in the integral process in Fig. 3.JFET operational amplifier selects the TLE2072I of TI company, and its maximum feature is that input impedance is very high, and the leakage current therefore in integrating capacitor charging and discharging process is just very little, and the measuring error caused because of leakage current is also just very little.The integration extension that monolithic TLE2072I can meet the pulse of two-way interpolation is simultaneously measured.
Integrating capacitor (C148 and C149 in figure) will select temperature coefficient function admirable, low dielectric loss, capacitance stability is high and insulation resistance is high I class porcelain condenser.Choosing of capacitance size considers the integral voltage reached in JFET operational amplifier supply voltage and measuring intervals of TIME, and the capacitance that in figure, circuit design is chosen is 100pF, and engineering generally chooses 100pF-1nF.
The integral voltage that JFET integration extensor 32 exports is converted to the integrated pulse of CMOS level as shown in Figure 3 by high-speed comparator 33, exports to FPGA circuit 2 and measures.The high-speed comparator 33 that the present invention adopts is MAX9142 of Maxim, and it has the features such as high speed, low-power consumption, binary channels, single power supply.
Designed by the multiple of charge/discharge datum and charge/discharge resistance in this example, extension factor K is designed to 2000 times, thus makes Measurement Resolution bring up to 50ps.
Four, serial communication circuit 4, parameter storage circuit 5
Asynchronous Serial Communication Circuit 4: FPGA circuit 2 is connected with host computer serial ports, for communicating with host computer, the state of real-time report input signal, phase place and frequency computation part result;
Parameter storage circuit 5: be connected with FGAP circuit 2, is made up of, for storage delay corrected parameter a slice serial line interface eeprom memory.
As shown in Figure 8, the major function of Asynchronous Serial Communication Circuit 4 is level conversion, by the generic asynchronous serial communication bus signal of the CMOS level that fpga chip exports, is converted to standard RS232 signal, directly can be connected with serial ports of computers like this and communicates.The core devices that serial communication circuit adopts is the MAX3232ESE of Maxim, is a low-power consumption, twin-channel standard RS-232 transceiver.
The content be not described in detail in instructions of the present invention belongs to the known technology of professional and technical personnel in the field.
Claims (5)
1. high-precision phase position and frequency measuring system, is characterized in that: comprise input signal conditioning circuit (1), FPGA circuit (2), integration type simulation extension circuit (3), Asynchronous Serial Communication Circuit (4) and parameter storage circuit (5);
Input signal conditioning circuit (1): the pulse signal that the passage a-signal, pass B signal and the reference clock signal that are inputted outside change CMOS fiduciary level respectively into delivers to FPGA circuit (2);
FPGA circuit (2): the passage a-signal after the process input input signal conditioning circuit (1) and the time interval between pass B signal carry out thick count measurement t
1, and in the beginning in the described time interval and ending place generation two interpolation pulses, and two interpolation pulses are exported respectively to integration type simulation extension circuit (3); Receive two integrated pulses that integration type simulation extension circuit (3) returns, and respectively count measurement t is carried out to the pulse returned
2and t
3, the Deferred Correction parametric t that incorporating parametric memory circuit (5) stores
d, calculate the exact time duration t=t in the time interval between A, B signal
1+ t
2-t
3+ t
d, and then calculate phase place t and the frequency f of A, B signal, and result of calculation is sent to host computer by Asynchronous Serial Communication Circuit (4);
Integration type simulation extension circuit (3): in each interpolation pulse interval, integrating capacitor is charged, after interpolation end-of-pulsing, integrating capacitor is discharged, the charging and discharging process of integrating capacitor forms integral voltage, and integral voltage is compared the integrated pulse that shaping obtains standard CMOS level, and this integrated pulse is delivered to FPGA circuit (2);
Asynchronous Serial Communication Circuit (4): FPGA circuit (2) is connected with host computer serial ports, for host computer serial communication, the state of real-time report input signal, phase place and frequency computation part result;
Parameter storage circuit (5): be connected with FGAP circuit (2), for storage delay corrected parameter;
Described integration type simulation extension circuit (3) comprises speed-sensitive switch device (31), JFET integration extensor (32), high-speed comparator (33), charge reference level circuit (34) and electric discharge reference level circuit (35);
Speed-sensitive switch device (31) is according to the interpolation pulse of input, control charge reference level circuit (34) to charge to the integrating capacitor in JFET integration extensor (32) in interpolation pulse interval, after interpolation end-of-pulsing, discharged to electric discharge reference level circuit (35) by integrating capacitor, the charging and discharging process of integrating capacitor forms integral voltage and exports to high-speed comparator (33); Integral voltage is compared the integrated pulse being shaped to standard CMOS level and delivers to FPGA circuit (2) by high-speed comparator (33).
2. high-precision phase position according to claim 1 and frequency measuring system, is characterized in that: described electric discharge compares at least 1000 times with the time constant of charging.
3. high-precision phase position according to claim 1 and frequency measuring system, is characterized in that: the generation of two described interpolation pulses is respectively: between the rising edge of signal A and the rising edge of reference clock or negative edge, form an interpolation pulse; Second interpolation pulse is formed between the rising edge of signal B and the rising edge of reference clock or negative edge.
4. high-precision phase position according to claim 3 and frequency measuring system, is characterized in that: described interpolation pulse width engineering is T
0~ 2T
0, T
0for the one-period of reference clock.
5. high-precision phase position according to claim 1 and frequency measuring system, is characterized in that: described integrating capacitor engineering chooses 100pF-1nF.
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| CN103354448B (en) * | 2013-06-18 | 2015-09-30 | 西安电子科技大学 | Based on the high resolution time interval generation system of FPGA |
| CN104062511B (en) * | 2014-07-03 | 2016-06-22 | 中国人民解放军国防科学技术大学 | A kind of precise phase measuring method of multichannel multiple target echo-signal |
| CN106093567A (en) * | 2016-06-01 | 2016-11-09 | 深圳先进技术研究院 | A kind of high-precision wide frequency-domain frequency measures system and frequency measurement method |
| CN106443179B (en) * | 2016-08-30 | 2019-06-11 | 石家庄数英仪器有限公司 | A kind of ps grades of time and frequency measurement circuit and measurement method |
| CN107346976B (en) * | 2017-07-13 | 2020-03-17 | 电子科技大学 | Digital-analog mixed time-to-digital conversion circuit |
| CN114019857B (en) * | 2021-10-28 | 2024-03-22 | 华中师范大学 | High-precision phase adjustment and measurement system and method based on phase interpolation |
| CN114697237B (en) * | 2022-04-15 | 2023-12-26 | 北京广利核系统工程有限公司 | Bus communication cycle test system and method |
| CN117439609B (en) * | 2023-12-21 | 2024-03-08 | 杭州万高科技股份有限公司 | Time-to-digital conversion circuit based on pulse stretching and chopping PLL |
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| US6091671A (en) * | 1999-07-14 | 2000-07-18 | Guide Technology, Inc. | Time interval analyzer having interpolator with constant current capacitor control |
| CN100579134C (en) * | 2004-12-17 | 2010-01-06 | 中国电子科技集团公司第五十研究所 | Modulating domain analyzing module based on A/D conversion |
| US7945408B2 (en) * | 2007-09-20 | 2011-05-17 | Voxis, Inc. | Time delay estimation |
| CN101976037B (en) * | 2010-11-29 | 2012-01-25 | 北京一朴科技有限公司 | Method and device for measuring time intervals of repeated synchronous interpolation simulation |
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