CN103063917A - High-precision phase and frequence measuring system - Google Patents
High-precision phase and frequence measuring system Download PDFInfo
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- CN103063917A CN103063917A CN2012105937242A CN201210593724A CN103063917A CN 103063917 A CN103063917 A CN 103063917A CN 2012105937242 A CN2012105937242 A CN 2012105937242A CN 201210593724 A CN201210593724 A CN 201210593724A CN 103063917 A CN103063917 A CN 103063917A
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Abstract
Provided is a high-precision phase and frequence measuring system. An input signal conditioning circuit in the system respectively converts a channel A signal, a channel B signal and a reference clock signal from external input into pulse signals and sends the pulse signals to a field programmable gata array (FPGA) circuit. The FPGA circuit makes a rough count measurement on the time interval between the treated channel A signal and the channel B signal and generates two interpolating pulses at the beginning and the end of the time interval and respectively outputs two interpolating pulses into an integral analog extension circuit. Two integral pulses sent back from the integral artificial extension circuit are received, a count measurement on the pulses which are sent back are respectively made, combining the count measurement and delay correction parameters to obtain phases and frequencies of the A signal and the B signal through calculations, and the phases and frequencies are sent to a host computer through an asynchronous serial communication circuit. The integral extension circuit forms an integral voltage according to the interpolating pulses, compares, reforms and sends the integral voltage to the FPGA circuit. The asynchronous serial communication circuit is used for communicating with host computer serial ports and a parameter storing circuit is used for storing delay correction parameters.
Description
Technical field
The present invention relates to high-precision phase position and frequency measurement technology, on the basis of the thick count measurement method of tradition, comprehensive double interpolation method and the integration type simulation stretching method of adopting, the time interval to be measured is divided into three parts carries out respectively precision measurement, make the Measurement Resolution in the time interval reach 50ps, measurement range can cover 50ps to the long arbitrarily time interval.Present technique especially at space flight military technological fields such as Modern Laser range measurement system, NAVSTAR, has very extensive and crucial application in traditional telecommunication path engineering practice field, atomic nuclear physics theoretical research field.
Background technology
Phase place and frequency are two important physical parameters of signal, all require they are carried out precision measurement in a lot of engineering practices of modern times and theoretical research field.The measurement of phase place refers to the measurement to two signal phase difference time interval t.Frequency refers to the periodicity of periodic signal process in the unit interval, often is designated as f, is expressed from the next:
In the formula: n is the periodicity of periodic signal process in time interval t, if t=1s, then the frequency representation per second is through n cycle, i.e. nHz.
In traditional measuring method, all be the method that adopts conventional counting to the measurement of phase place and frequency.When measuring phase place, by reference clock the time interval of phase differential directly to be counted, count results multiply by the cycle of reference clock, namely is the phase difference measurement result.When survey frequency, calculate the periodicity n of measured signal experience with reference clock, again divided by time interval t, just obtain the frequency f of periodic signal.
Easily find out, the measuring method of traditional direct counting, maximum source of error is to have between the measured time interval and the reference clock ± the Randomized Quantizing error of 1 count value.For phase measurement, measuring error is:
Δt＝±1T
0
In the formula, Δ t is phase differential time interval measurement error, T
0Be the cycle of reference clock.If take the 10MHz reference clock as example, the measuring error in the phase differential time interval namely is ± 100ns.This is concerning high-precision phase measurement requires, and error is too large.Relative error to frequency measurement is:
Δ f is frequency error value in the formula, and f is actual frequency values, f
0The frequency of reference clock.If take the 10MHz reference clock as example, the relative error of frequency measurement is 2 * 10
-7
As from the foregoing, traditional conventional count measurement method is brought very large error term.And to improve measuring accuracy, and must improve constantly reference clock frequency, reference clock frequency is higher, and the quantization error that ± 1 count value is brought will be less.
In the modern time interval measurement technology, also has a kind of time-to-digit converter based on digital tapped delay line method, yet this element height depends on the manufacturing process of integrated circuit, fabrication error can bring the measuring error item, and the variation of environment temperature is very large on the lag line impact, also brings larger measuring error item.The measuring accuracy of common this technology can only reach 500ps, and measurement range is very little.
In modern high-acruracy survey is used, usually require the measuring error in the phase differential time interval less than 1ns, the relative error of frequency measurement is less than 1 * 10
-9The conventional thick method of counting of tradition obviously has been difficult to satisfy such accuracy requirement.Although and modern digital formula tapped delay line measuring technique can satisfy some application demand to a certain extent, to the harsh requirement of manufacturing process and working environment, so that this technology measuring error in actual applications is larger, and cost is higher.In addition, the measurement range that the tapped delay line technology is less also is difficult to satisfy a lot of application requirements of measuring.
Summary of the invention
Technology of the present invention is dealt with problems: overcome the conventional thick method of counting measuring accuracy of tradition too low, and measuring accuracy depends on the problem of reference clock frequency size, a kind of high-precision phase position and frequency measuring system are provided.
Technical solution of the present invention: high-precision phase position and frequency measuring system comprise input signal conditioning circuit, FPGA circuit, integration type simulation extension circuit, Asynchronous Serial Communication Circuit and Parameter storage circuit;
The input signal conditioning circuit: the pulse signal that passage a-signal, channel B signal and the reference clock signal of outside input is changed respectively into the CMOS fiduciary level is delivered to the FPGA circuit;
FPGA circuit: passage a-signal and the time interval between the channel B signal after the processing of input signal conditioning circuit input are carried out thick count measurement t
1, and generate two interpolation pulses in the beginning in the described time interval and ending place, and export respectively two interpolation pulses to integration type simulation extension circuit; Receive two integrated pulses that integration type simulation extension circuit returns, and count measurement t is carried out respectively in the pulse of returning
2And t
3, the Deferred Correction parametric t of incorporating parametric memory circuitry stores
d, calculate the precise time length t=t in the time interval between A, the B signal
1+ t
2-t
3+ t
d, and then calculate phase place t and the frequency f of A, B signal, and result of calculation is sent to host computer by Asynchronous Serial Communication Circuit;
Integration type simulation extension circuit: in each interpolation pulse interval, integrating capacitor is charged, behind the interpolation end-of-pulsing, integrating capacitor is discharged, the charging and discharging process of integrating capacitor forms integral voltage, and integral voltage comparison shaping is obtained the integrated pulse of standard CMOS level, and this integrated pulse is delivered to the FPGA circuit;
Asynchronous Serial Communication Circuit: the FPGA circuit is linked to each other with the host computer serial ports, be used for and host computer serial communication, the state of real-time report input signal, phase place and frequency computation part result;
Parameter storage circuit: be connected with the FGAP circuit, be used for the storage delay corrected parameter.
Described integration type simulation extension circuit comprises speed-sensitive switch device, JFET integration extensor, high-speed comparator, charging reference level circuit and discharge reference level circuit;
The speed-sensitive switch device is according to the interpolation pulse of input, control charging reference level circuit is charged to the integrating capacitor in the JFET integration extensor in the interpolation pulse interval, behind the interpolation end-of-pulsing, by integrating capacitor the discharge reference level circuit is discharged, the charging and discharging process of integrating capacitor forms integral voltage and exports to high-speed comparator; High-speed comparator is delivered to the FPGA circuit with the integrated pulse that integral voltage relatively is shaped to the standard CMOS level.
The time constant of described discharge and charging is than at least 1000 times.
The generation of described two interpolation pulses is respectively: form an interpolation pulse between the rising edge of the rising edge of signal A and reference clock or negative edge; Between the rising edge of the rising edge of signal B and reference clock or negative edge, form second interpolation pulse.
Be generally T on the described interpolation pulse width engineering
0～2T
0, T
0One-period for reference clock.
Generally choose 100pF-1nF on the described integrating capacitor engineering.
Principle of the present invention: the present invention is to the Technology Precision of signal phase and frequency, at first all unify on the principle on time domain to the Technology of Precision Measurement in the time interval.Row precision measurement when then simulating the extension principle to the time interval by double interpolation measuring principle and integration, thus realization is to the high-acruracy survey of phase place and frequency.The concrete principle of the present invention is discussed below:
As previously mentioned, to the measurement of phase place, namely be the measurement to the signal phase difference time interval, and the measurement of signal frequency can be obtained by the frequency departure of measuring between it and the reference clock, frequency departure is defined by following formula:
Δ f is frequency departure in the formula, and f is signal frequency, f
0Be reference clock frequency.In fact, just can obtain frequency departure between signal and the reference clock by the phase variation rate of asking signal, this is because frequency departure is the basic reason that causes signal phase to change, and therefore can obtain frequency departure by following formula:
Δ t is phase changing capacity in the formula, and T is measuring period.By following formula as can be known, just can obtain the frequency values of signal by the variable quantity of measuring the signal phase difference time interval in a period of time, thereby realize the high-acruracy survey to signal phase.Therefore, to the high-acruracy survey of signal phase and frequency, can at first be converted into the precision measurement to the time interval.
Before state because the uncertainty of phase place between input signal and the reference clock, conventional phase and frequency measurement method maximum error source are the count value quantization error of ± 1 word, namely ± 1T
0This quantization error is the fraction part that the thick count measurement of tradition does not detect.And the use of interpolater is exactly for the precision measurement fraction part.
Double interpolation ratio juris of the present invention such as the Fig. 2 of institute show.During double interpolation method measuring intervals of TIME, first t is divided into 3 part intervals: t is measured in real time with coarse counter in a long interval
1Two remaining short intervals are respectively at the beginning t of t
2With end t
3The place.Wherein, t
2And t
3Be generally T
0～2T
0, these two periods time intervals are slightly counted the integer measuring method with respect to tradition, are exactly the fraction part of measuring, and also are the source of errors of traditional measurement method maximum.Therefore, the time interval t that measures by interpolation method is expressed by following formula:
t＝t
1+t
2-t
3
In the formula, thick count measurement is t as a result
1=NT
0, t
2And t
3It is the rising edge of input signal A and signal B and the time interval between second nearest reference clock rising edge.To t
1Measurement use traditional coarse counter, to t
2And t
3Two-part measurement then adopts following integration type simulation stretching method to carry out respectively precision measurement.
Integration type simulation extension ratio juris of the present invention as shown in Figure 3.Time interval t to aforementioned interpolation
2Or t
3When adopting integration type simulation stretching method to measure, in interpolation pulse interval τ, to the integrating capacitor charging, behind the interpolation end-of-pulsing, integrating capacitor is externally discharged, if be k with the duration of charging ratio discharge time, then be k τ discharge time.Therefore, the molded breadth of integrated pulse width is (k+1) τ, that is: the integrated pulse width obtain of extending be interpolation pulse width (k+1) doubly.Usually definition K=k+1 is the extension factor, and the Measurement Resolution of defining integration formula simulation stretching method:
The circuit theory of integration type simulation stretching method of the present invention as shown in Figure 4.The charging and discharging process of JFET integrator is being controlled by high-speed analog switch.In charging process, the charging datum is 5V, and charging resistor is 1K ohm, so charging current is 5mA; In discharge process, the discharge datum is-2.5V that discharge resistance is 1M ohm, so discharge current is-2.5 μ A.Therefore the charge and discharge time than k is:
2000 times of extension factor K=k+1=2001 times ≈.Be the reference clock of 10MHz for frequency, Measurement Resolution is:
And Measurement Resolution is T in the classic method
0, be the 10MHz reference clock to frequency, resolution only has 100ns.Therefore adopt integration type simulation stretching method, measuring accuracy is greatly improved.
Before state, frequency departure is defined by following formula:
In the formula, Δ t is phase changing capacity, and the Measurement Resolution of Δ t can reach 50ps as mentioned above, and therefore, for measurement period T=1s, the Measurement Resolution of Δ f just can reach 5 * 10
-11Measurement period T is longer, and the measuring accuracy of frequency f is higher.
High-precision phase position of the present invention and frequency measurement technology are on the thick method of counting of tradition basis, comprehensively adopt interpolation method and integration type simulation stretching method expansion measuring accuracy.Because the use of coarse counter, the measurement range in the time interval is very large; Because the use of integration simulation stretching method, it is very high that the Measurement Resolution of phase place and frequency reaches.In addition, when each the measurement, all can carry out primary calibration, eliminate the measuring error that variation of ambient temperature is brought in the measuring process.
The present invention compares with existing measuring technique, and advantage is:
(1) comprehensive advanced double interpolation method and the integration type simulation stretching method of adopting reaches 50ps to the Measurement Resolution in the time interval, is higher than the measurement resolution of classic method far away.
(2) to the measuring technique of frequency, the method by indirect measurement phase changing capacity has improved measuring accuracy, makes the frequency measurement accuracy reach 5 * 10
-11Above.
(3) measuring method of the present invention is to adopt the double interpolation method on the basis of the conventional method of counting of tradition, and the measurement range in the time interval is guaranteed, and can carry out precision measurement to arbitrarily long-time interval to 50ps.
(4) possess the self calibration ability, when each the measurement, all carry out the primary calibration operation, the error that the variation of elimination ambient temperature brings to measurement.
(5) compare with modern digital formula tapped delay line technology, measuring method of the present invention is not subjected to the impact of integrated circuit fabrication process, and has higher Measurement Resolution.
(6) has lower hardware cost advantage.
Description of drawings
Fig. 1 is general principles block diagram of the present invention;
Fig. 2 is double interpolation method schematic diagram of the present invention;
Fig. 3 is integration type simulation stretching method schematic diagram of the present invention;
Fig. 4 is integration type simulation extension circuit theory diagrams of the present invention;
Fig. 5 is input signal conditioning circuit diagram of the present invention;
Fig. 6 is FPGA circuit diagram of the present invention;
Fig. 7 is integration type simulation stretching method circuit diagram of the present invention;
Fig. 8 is serial communication circuit figure of the present invention;
Fig. 9 is FPGA program flow diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing and example the present invention is elaborated, specific as follows:
As shown in Figure 1, hardware circuit of the present invention mainly is comprised of input signal conditioning circuit 1, FPGA circuit 2, integration type simulation extension circuit 3, serial communication circuit 4 and Parameter storage circuit 5.
One, the input signal conditioning circuit 1
Input signal conditioning circuit 1 links to each other with passage a-signal, channel B signal and the reference clock signal of outside input, three road input signals all is transformed into respectively the pulse signal of CMOS fiduciary level, gives FPGA circuit 2.Every road specifically comprises resistors match/attenuator circuit and ac/dc coupled circuit and high-speed comparator circuit.The impedance matching of input signal is ∏ type resistor network with the decay employing.Optional stream coupling scheme or the DC coupling mode of choosing friends of the coupling of input signal.The core devices that the high speed comparator circuit adopts is the MAX961 ultrahigh-speed comparator.
As shown in Figure 5, be the input modulate circuit figure of passage a-signal, the input modulate circuit of channel B signal and reference clock signal is identical with it.Input end coupling in the input signal conditioning circuit 1 adopts ∏ type resistor network, both can satisfy the impedance matching of input signal, also can suitably decay to signal volt value.High-speed comparator is selected the U.S. letter MAX961 of company.The purpose of input signal conditioning circuit is the pulse signal that input signal is converted to the standard CMOS level.
Two, the FPGA circuit 2
As shown in Figure 1, fpga chip is the core processor of realizing as major control logic, asynchronous serial communication logic, Parameter storage logic and precision measurement algorithm in the FPGA circuit 2.The FPGA circuit specifically comprises fpga chip 21 and FPGA configuring chip 22.Fpga chip 21 internal logic programs mainly are divided into following components: coarse counter and double interpolation device logic 211, pulse are extended and thin counter logic 212, phase place and frequency calculation processing unit 213 and asynchronous serial communication logic 214.Major function: passage a-signal and the time interval between the channel B signal after the processing of input signal conditioning circuit 1 input are carried out thick count measurement t
1, and generate respectively an interpolation pulse in the beginning in the described time interval and ending, and export respectively two interpolation pulses to integration type simulation extension circuit 3; Receive two integrated pulses that integration type simulation extension circuit 3 returns, and the pulse of returning carried out respectively count measurement, the Deferred Correction parameter of incorporating parametric memory circuit 5 storages, calculate the precise time length in the time interval between A, the B signal, and then calculate phase place and the frequency of A, B signal, and result of calculation is sent to host computer by Asynchronous Serial Communication Circuit (4).
Coarse counter in FPGA circuit 2 inner coarse counters and the double interpolation device logic 211 carries out thick count measurement to the time interval between signal A, the B, and measurement result is designated as t
1, and generate the interpolation pulse by the double interpolation device in the beginning in this section time interval and ending place and (as shown in Figure 2, between the rising edge of the rising edge of signal A and reference clock or negative edge, form an interpolation pulse; Between the rising edge of the rising edge of signal B and reference clock or negative edge, form second interpolation pulse; Be generally T on the interpolation pulse width engineering
0～2T
0, T
0One-period for reference clock.), and the interpolation pulse sent into carries out ratio in the integration type simulation extension circuit 3 and amplify, again by pulse extend with thin 212 pairs of broadenings of counter logic after integrated pulse carry out count measurement, measurement result is designated as t
2, t
3Phase place and frequency calculation processing unit 213 at first read the Deferred Correction parametric t from Parameter storage circuit 5
d, and according to formula t=t
1+ t
2-t
3+ t
dObtain the precise time length (being the phase place between the signal AB) in the time interval between A, the B signal, and then the phase changing capacity Δ t under definite measurement period T, determine frequency f according to following formula again:
Phase place and frequency calculation processing unit 213 also send to Asynchronous Serial Communication Circuit 4 with result of calculation by asynchronous serial communication logic 214.Asynchronous serial communication logic 214 forms frame with the result of calculation packing, with the form correspondence with foreign country of frame.
As shown in Figure 6, the FPGA circuit is for measuring the core processing circuit of control, serial communication, parameter access and phase place and frequency algorithm realization.That the power module of FPGA circuit uses is the PTH04070WAD (N1 among the figure, N2) of TI company.Fpga chip D1 adopts Cyclone II series EP2C20F256I8, and it has large capacity logical block, advantage cheaply; Configuring chip D2 adopts EPCS4I8.
The FPGA program circuit behind the power-up initializing, at first detects the state of input signal and reference clock as shown in Figure 9, if no signal or reference clock input, then produce alerting signal, intuitively show by LED light, and signal condition is reported host computer by serial communication.Otherwise, begin to read the fixed delay corrected parameter in the EEPROM, initialization survey, the line time interval measurement of going forward side by side, phase place and frequency calculation processing unit calculate phase place and the frequency of signal in real time according to signal phase difference time interval measurement result.Behind power-up initializing, the serial ports of serial communication logic receives buffering FIFO and constantly receives the data that host computer sends, and carries out frame synchronization detection and command parameter decoding, and order and the parameter received are delivered to the respective logic module.The transmission link of serial communication is with phase place and frequency measurement, input signal and reference clock status information simultaneously, and packing forms and sends frame, sends into serial ports and sends buffering FIFO, is uploaded to host computer by serial port circuit.
Three, integration type simulation extension circuit 3
Integration type simulation extension circuit 3 major functions: in an interpolation pulse interval, integrating capacitor is charged, behind the interpolation end-of-pulsing, integrating capacitor is discharged, the charging and discharging process of integrating capacitor forms integral voltage, integral voltage relatively is shaped to the integrated pulse of standard CMOS level, and this integrated pulse is delivered to FPGA circuit 2;
Integration type simulation extension circuit 3 comprises speed-sensitive switch device 31, JFET integration extensor 32, high-speed comparator 33, charging reference level circuit 34 and discharge reference level circuit 35; In the interpolation arteries and veins of speed-sensitive switch device 31 according to input, control charging reference level circuit 34 is charged to the integrating capacitor in the JFET integration extensor 32 in the interpolation pulse interval, behind the interpolation end-of-pulsing, by integrating capacitor discharge reference level circuit 35 is discharged, the charging and discharging process of integrating capacitor forms integral voltage and exports to high-speed comparator 33; High-speed comparator 33 is delivered to FPGA circuit 2 with the integrated pulse that integral voltage relatively is shaped to the standard CMOS level.
As shown in Figure 7, the core devices of integration type simulation extension circuit 3 comprises datum chip LM336, speed-sensitive switch device MAX4614, JFET operational amplifier TLE2072I and high-speed comparator MAX9142.
5V reference level circuit in the integration type simulation extension circuit 3 is generated by LM336-5 (D16 among the figure) chip, is used for the charging process of JFET integration extensor 32;-2.5V reference level circuit is generated by LM336-2.5 (D20 among the figure) chip, is used for the discharge process of JFET integration extensor 32.
Charging resistor (R214 and R215 among the figure) and discharge resistance (R230 and R231 among the figure) should select that high frequency performance is good, the temperature coefficient function admirable, the resistance that precision is higher.The ratio of charging resistor resistance and discharge resistance resistance is not more than 1: 1000, and for example, the charging resistor resistance is designed to 1k ohm, and the discharge resistance resistance is designed to 1M ohm.
Speed-sensitive switch device 31 is being controlled the charging and discharging process to JFET integration extensor 32, in the interpolation pulse interval, the high-speed analog switch conducting, the 5V datum charges to the integrating capacitor in the JFET integration extensor (C148 among the figure and C149); Behind the interpolation end-of-pulsing, high-speed analog switch is closed, and the p-2.5V datum of integrating capacitor discharges.Speed-sensitive switch device 31 is selected the MAX4614 of U.S. letter company, is characterized in four-way, switching speed is fast, conducting resistance is very little, closes leakage current also very little.
Integrating capacitor (C148 among the figure and C149) will be selected temperature coefficient function admirable, low dielectric loss, the appearance value stabilization is high and insulation resistance is high I class porcelain condenser.Choosing of appearance value size is to consider the integral voltage that reaches in JFET operational amplifier supply voltage and the measuring intervals of TIME, and the appearance value that circuit design is chosen among the figure is 100pF, generally chooses 100pF-1nF on the engineering.
The integrated pulse that high-speed comparator 33 is converted to the CMOS level with the integral voltage of JFET integration extensor 32 output is exported to FPGA circuit 2 and is measured as shown in Figure 3.The high-speed comparator 33 that the present invention adopts is MAX9142 of U.S. letter company, and it has the characteristics such as high speed, low-power consumption, binary channels, single power supply.
By the multiple design of charge/discharge datum and charge/discharge resistance, the extension factor K is designed to 2000 times, thereby makes Measurement Resolution bring up to 50ps in this example.
Four, serial communication circuit 4, Parameter storage circuit 5
Asynchronous Serial Communication Circuit 4: FPGA circuit 2 is linked to each other with the host computer serial ports, be used for communicating by letter the state of real-time report input signal, phase place and frequency computation part result with host computer;
Parameter storage circuit 5: be connected with FGAP circuit 2, consisted of by a slice serial line interface eeprom memory, be used for the storage delay corrected parameter.
As shown in Figure 8, the major function of Asynchronous Serial Communication Circuit 4 is level conversion, and the universal asynchronous serial communication bus signal with the CMOS level of fpga chip output is converted to standard RS232 signal, can directly be connected communication with serial ports of computers like this.The core devices that serial communication circuit adopts is the MAX3232ESE of U.S. letter company, is a low-power consumption, twin-channel standard RS-232 transceiver.
The content that is not described in detail in the instructions of the present invention belongs to this area professional and technical personnel's known technology.
Claims (6)
1. high-precision phase position and frequency measuring system is characterized in that: comprise input signal conditioning circuit (1), FPGA circuit (2), integration type simulation extension circuit (3), Asynchronous Serial Communication Circuit (4) and Parameter storage circuit (5);
Input signal conditioning circuit (1): the pulse signal that passage a-signal, channel B signal and the reference clock signal of outside input is changed respectively into the CMOS fiduciary level is delivered to FPGA circuit (2);
FPGA circuit (2): passage a-signal and the time interval between the channel B signal after the processing of input signal conditioning circuit (1) input are carried out thick count measurement t
1, and generate two interpolation pulses in the beginning in the described time interval and ending place, and export respectively two interpolation pulses to integration type simulation extension circuit (3); Receive two integrated pulses that integration type simulation extension circuit (3) returns, and count measurement t is carried out respectively in the pulse of returning
2And t
3, the Deferred Correction parametric t of incorporating parametric memory circuit (5) storage
d, calculate the precise time length t=t in the time interval between A, the B signal
1+ t
2-t
3+ t
d, and then calculate phase place t and the frequency f of A, B signal, and result of calculation is sent to host computer by Asynchronous Serial Communication Circuit (4);
Integration type simulation extension circuit (3): in each interpolation pulse interval, integrating capacitor is charged, behind the interpolation end-of-pulsing, integrating capacitor is discharged, the charging and discharging process of integrating capacitor forms integral voltage, and integral voltage comparison shaping is obtained the integrated pulse of standard CMOS level, and this integrated pulse is delivered to FPGA circuit (2);
Asynchronous Serial Communication Circuit (4): FPGA circuit (2) is linked to each other with the host computer serial ports, be used for and host computer serial communication, the state of real-time report input signal, phase place and frequency computation part result;
Parameter storage circuit (5): be connected with FGAP circuit (2), be used for the storage delay corrected parameter.
2. high-precision phase position according to claim 1 and frequency measuring system is characterized in that: described integration type simulation extension circuit (3) comprises speed-sensitive switch device (31), JFET integration extensor (32), high-speed comparator (33), charging reference level circuit (34) and the reference level circuit (35) of discharging;
Speed-sensitive switch device (31) is according to the interpolation pulse of input, control charging reference level circuit (34) is charged to the integrating capacitor in the JFET integration extensor (32) in the interpolation pulse interval, behind the interpolation end-of-pulsing, by integrating capacitor discharge reference level circuit (35) is discharged, the charging and discharging process of integrating capacitor forms integral voltage and exports to high-speed comparator (33); High-speed comparator (33) is delivered to FPGA circuit (2) with the integrated pulse that integral voltage relatively is shaped to the standard CMOS level.
3. high-precision phase position according to claim 2 and frequency measuring system is characterized in that: the time constant of described discharge and charging is than at least 1000 times.
4. high-precision phase position according to claim 1 and frequency measuring system, it is characterized in that: the generation of described two interpolation pulses is respectively: form an interpolation pulse between the rising edge of the rising edge of signal A and reference clock or negative edge; Between the rising edge of the rising edge of signal B and reference clock or negative edge, form second interpolation pulse.
5. high-precision phase position according to claim 4 and frequency measuring system is characterized in that: be generally T on the described interpolation pulse width engineering
0～2T
0, T
0One-period for reference clock.
6. high-precision phase position according to claim 1 and 2 and frequency measuring system is characterized in that: generally choose 100pF-1nF on the described integrating capacitor engineering.
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| CN103354448A (en) * | 2013-06-18 | 2013-10-16 | 西安电子科技大学 | High resolution time interval generation system based on FPGA |
| CN104062511A (en) * | 2014-07-03 | 2014-09-24 | 中国人民解放军国防科学技术大学 | Accurate phase measurement method of multipath multi-target echo signal |
| CN106093567A (en) * | 2016-06-01 | 2016-11-09 | 深圳先进技术研究院 | A kind of high-precision wide frequency-domain frequency measures system and frequency measurement method |
| CN106443179A (en) * | 2016-08-30 | 2017-02-22 | 石家庄数英仪器有限公司 | Ps-grade time frequency measurement circuit and measurement method thereof |
| CN107346976A (en) * | 2017-07-13 | 2017-11-14 | 电子科技大学 | A kind of time-to-digital conversion circuit of numerical model analysis |
| CN114019857A (en) * | 2021-10-28 | 2022-02-08 | 华中师范大学 | High-precision phase adjusting and measuring system and method based on phase interpolation |
| CN114697237A (en) * | 2022-04-15 | 2022-07-01 | 北京广利核系统工程有限公司 | Bus communication cycle test system and method |
| CN117439609A (en) * | 2023-12-21 | 2024-01-23 | 杭州万高科技股份有限公司 | Time-to-digital conversion circuit based on pulse stretching and chopping PLL |
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| CN103354448A (en) * | 2013-06-18 | 2013-10-16 | 西安电子科技大学 | High resolution time interval generation system based on FPGA |
| CN104062511A (en) * | 2014-07-03 | 2014-09-24 | 中国人民解放军国防科学技术大学 | Accurate phase measurement method of multipath multi-target echo signal |
| CN104062511B (en) * | 2014-07-03 | 2016-06-22 | 中国人民解放军国防科学技术大学 | A kind of precise phase measuring method of multichannel multiple target echo-signal |
| CN106093567A (en) * | 2016-06-01 | 2016-11-09 | 深圳先进技术研究院 | A kind of high-precision wide frequency-domain frequency measures system and frequency measurement method |
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| CN114019857A (en) * | 2021-10-28 | 2022-02-08 | 华中师范大学 | High-precision phase adjusting and measuring system and method based on phase interpolation |
| CN114019857B (en) * | 2021-10-28 | 2024-03-22 | 华中师范大学 | High-precision phase adjustment and measurement system and method based on phase interpolation |
| CN114697237A (en) * | 2022-04-15 | 2022-07-01 | 北京广利核系统工程有限公司 | Bus communication cycle test system and method |
| CN114697237B (en) * | 2022-04-15 | 2023-12-26 | 北京广利核系统工程有限公司 | Bus communication cycle test system and method |
| CN117439609A (en) * | 2023-12-21 | 2024-01-23 | 杭州万高科技股份有限公司 | Time-to-digital conversion circuit based on pulse stretching and chopping PLL |
| CN117439609B (en) * | 2023-12-21 | 2024-03-08 | 杭州万高科技股份有限公司 | Time-to-digital conversion circuit based on pulse stretching and chopping PLL |
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