CN106682258A - Method and system for multi-operand addition optimization in high-level synthesis tool - Google Patents
Method and system for multi-operand addition optimization in high-level synthesis tool Download PDFInfo
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- CN106682258A CN106682258A CN201611009866.4A CN201611009866A CN106682258A CN 106682258 A CN106682258 A CN 106682258A CN 201611009866 A CN201611009866 A CN 201611009866A CN 106682258 A CN106682258 A CN 106682258A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
Abstract
The invention discloses a method and system for multi-operand addition optimization in a high-level synthesis tool. The method comprises the steps that a high-level functional description of circuit design is obtained, and further calculation operations and operands contained in the circuit design can be obtained; the calculation operations are analyzed, whether the three or more than three operands are added continuously is judged, wherein following steps will be continued if the continuous addition is found and otherwise the step will be stopped; an optimization target in a user configuration document is read, a compression tree is established according to the optimization target, and information of the compression tree is stored; and a compression tree HDL code which can synthesized is generated according to the information of the compression tree. According to the invention, design space optimization of the multi-operand addition can be achieved according to the optimization target in the user configuration document at a high-level synthesis stage, so a multi-operand addition circuit with better performance can be generated, and performance of the high-level synthesis tool can be enhanced. The method and system for the multi-operand addition optimization in the high-level synthesis tool disclosed by the invention can be widely applied in the field of computer and circuit design.
Description
Technical field
The present invention relates to the multioperand in computer and circuit design field, more particularly to a kind of High Level Synthesis instrument
Addition optimization method and system.
Background technology
In Design of Digital Circuit, multioperand addition is in Digital Signal Processing, picture video process, high-performance calculation etc.
Many aspects tool is widely used, and its arithmetic speed often produces material impact with resource overhead to circuit design quality.
High-level language is converted directly into hardware and is retouched by High Level Synthesis technology by processes such as compiling, scheduling, resource allocations
Predicate is sayed, can effectively improve design efficiency and save design time.Efficient algorithm and hardware circuit design method are conducive to
Lift the performance of High Level Synthesis instrument.For multioperand addition, its hardware circuit realizes can thering is various structures.But
In conventional High Level Synthesis system, generally multioperand is realized using full adder, half adder or traditional adder tree and added
Method, and do not deeply consider the design space exploration of multioperation addition and related optimization.On the one hand so can cause larger to enter
Position propagation delay；On the other hand tend not to be well adapted for the logical structure of target platform, be especially for target platform
The situation of field programmable gate array (FPGA).Therefore, by conventional High Level Synthesis system, the hardware circuit for automatically generating sets
In meter, if with fairly large multioperand add operation, this part design often has larger time delay and takes
More hardware resource, so as to affect the total quality of hardware designs.
The content of the invention
In order to solve above-mentioned technical problem, the purpose of the present invention is：There is provided and be based in a kind of High Level Synthesis instrument broad sense
The high-performance multioperand addition optimization method that parallel counter is realized.
In order to solve above-mentioned technical problem, it is another object of the present invention to：There is provided and be based in a kind of High Level Synthesis instrument
The high-performance multioperand addition optimization system that generalized parallel enumerator is realized.
The technical solution adopted in the present invention is：A kind of multioperand addition optimization method in High Level Synthesis instrument,
Include following steps：
A, obtain the high layer function description of circuit design, so obtain arithmetic operation that the circuit design included and
Operand；
B, judge that the operand whether arithmetic operation obtained in step A occurs 3 or more than 3 is continuously added, if so,
Addition optimization processing unit is then loaded into, and this processing unit is performed into step C, otherwise then terminated；
C, the optimization aim data read in user profile, according to optimization aim data compressed tree is set up, and is preserved
Compressed tree information；
D, being generated according to the compressed tree information preserved in step C can comprehensive compressed tree HDL code.
Further, step C is specifically included：
C1, read user profile and obtain optimization aim data, and according to optimization aim to generalized parallel enumerator
Carry out prioritization；
C2, use are processed multiple operands through the generalized parallel enumerator of prioritization, generate compressed tree
And preserve compressed tree information.
Further, in step B, operand two-dimensional lattice figure is represented.
Further, in step C2, the compressed tree is used to many numbers be sued for peace and using it and as output, protected
The series of the compressed tree information deposited including compressed tree, the generalized parallel counter type used per one-level and use number and
The input/output information of last adder.
Further, in step C, the operand being input into as multioperand addition of the compressed tree, the compressed tree
It is output as the sum of the operand of multioperand addition, the function of the compressed tree and the addition function phase of multioperand addition
Together.
Another technical scheme of the present invention is：A kind of multioperand addition optimization system in High Level Synthesis instrument
System, the system includes：
Acquiring unit, the high layer function for obtaining circuit design is described, and then obtains what the circuit design was included
Arithmetic operation and operand；
Judging unit, for judging acquiring unit in the arithmetic operation that obtains whether there is the operand of 3 or more than 3
It is continuous to be added, addition optimization processing unit is if so, then loaded into, and into this processing unit of execution, otherwise then terminate；
Addition optimization processing unit, for reading user profile in optimization aim data, according to optimization aim number
According to setting up compressed tree, and preserve compressed tree information；
Code generating unit, the compressed tree information for being preserved according to addition optimization processing unit generates compression that can be comprehensive
Tree HDL code.
Further, the addition optimization processing unit includes：
Order module, for reading user profile and obtaining design optimization target data, according to optimization aim data
Prioritization is carried out to generalized parallel enumerator；
Generation module, for using the generalized parallel enumerator of prioritization was carried out in order module to multiple operations
Number is processed, and is generated compressed tree and is preserved compressed tree information.
Further, in the judging unit, operand two-dimensional lattice figure is represented.
Further, in the generation module, the compressed tree is used to that many numbers to be sued for peace and using it and as output,
The series of the compressed tree information of preservation including compressed tree, the generalized parallel counter type used per one-level and use number, with
And the input/output information of last adder.
Further, in the addition optimization processing unit, the input of the compressed tree is the operand of multioperand addition,
The compressed tree is output as the sum of the operand of multioperand addition, the function of the compressed tree and adding for multioperand addition
Method function phase is same.
The invention has the beneficial effects as follows：By using the inventive method, can be matched somebody with somebody according to user in the High Level Synthesis stage
Putting the optimization aim in file carries out the design space optimization of many behaviour's number additions, contributes to the more excellent multioperand of generation performance and adds
Method circuit, while being conducive to lifting the performance of High Level Synthesis instrument.
Another beneficial effect of the present invention is：By using present system, can be matched somebody with somebody according to user in High Level Synthesis
Putting the optimization aim in file carries out the design space optimization of many behaviour's number additions, contributes to the more excellent multioperand of generation performance and adds
Method circuit, while being conducive to lifting the performance of High Level Synthesis instrument.
Description of the drawings
The specific embodiment of the present invention is described further below in conjunction with the accompanying drawings：
The step of Fig. 1 is the inventive method flow chart；
The step of Fig. 2 is the inventive method specific embodiment flow chart；
Fig. 3 is the addition schematic diagram in the inventive method specific embodiment；
Fig. 4 is the two-dimensional points system of battle formations in the inventive method specific embodiment；
Fig. 5 is the part GPC dot chart schematic diagrams of the inventive method；
Fig. 6 is compressed tree product process figure in the inventive method specific embodiment；
Fig. 7 is the structured flowchart of present system；
Fig. 8 is the structured flowchart in present system specific embodiment.
Specific embodiment
The specific embodiment of the present invention is described further below in conjunction with the accompanying drawings：
With reference to Fig. 1, the multioperand addition optimization method in a kind of High Level Synthesis instrument includes following steps：
A, obtain the high layer function description of circuit design, so obtain arithmetic operation that the circuit design included and
Operand；
The present embodiment is the unsigned number addition of 54 bits, and it is 4 additions and 5 operands to obtain result.
B, judge that the operand whether arithmetic operation obtained in step A occurs 3 or more than 3 is continuously added, if so,
Addition optimization processing unit is then loaded into, and this processing unit is performed into step C, otherwise then terminated；
The present embodiment will detect 5 operands and continuously be added, and judged result is yes, execution step C.5 in the present embodiment
Individual 4 bit unsigned number additive process is as shown in figure 3, wherein aijRepresent the jth position of i-th operand, skRepresent addition results
Kth position.
C, the optimization aim data read in user profile, according to optimization aim data compressed tree is set up, and is preserved
Compressed tree information；
D, being generated according to the compressed tree information preserved in step C can comprehensive compressed tree HDL code.
With reference to Fig. 2, it is further used as preferred embodiment, step C is specifically included：
C1, read user profile and obtain optimization aim data, and according to optimization aim to generalized parallel enumerator
(Generalized Parallel Counter, abbreviation GPC) carries out prioritization；
One of them specific GPC input/output relations GPC (1,4,1,5；5) illustrate, it is 0 that this GPC has 5 weights
Input, 1 weight is 1 input, and 4 weights are 2 input, and 1 weight is 3 input, and it is output as the nothing of 5 bits
Symbolic number R, when all inputs are all 1：
R=5 × 20+1×21+4×22+1×23=(11111)2=(31)10
C2, use are processed multiple operands through the generalized parallel enumerator of prioritization, generate compressed tree
And preserve compressed tree information.
It is further used as preferred embodiment, the design optimization target includes area-optimized, timing optimization or sequential
Area product optimization.
The hardware resource and its time delay for being input to output that difference GPC takes in FPGA is different, according to optimization mesh
Target difference carries out prioritization using different comparison criterions to it.
For example in the FPGA of Xilinx, GPC (2,6；4) 3 LUT have been used, its maximum delay for being input to output is
0.316ns, input is 2+6-4=4 with the number difference of output.And GPC (6；3) 2 LUT have been used, it is input to output most
Big time delay is 0.293ns, and input is 6-3=3 with the difference of output number.
If optimization aim is timing optimization, then be input into the maximum delay that output is input to the difference and GPC of output with GPC
Ratio (being designated as PD) for sequence benchmark.GPC(6；3) its PD value is 3/0.293=10.239, GPC (2,6；4) its PD value is 4/
0.316=12.658, due to 12.658>10.239, therefore GPC (2,6；4) priority ratio GPC (6；3) it is high.
If optimization aim is area-optimized, then be input into GPC and use resource (usually LUT) with the difference and GPC of output
Ratio (being designated as AD) for sequence benchmark.GPC(6；3) its AD value is 3/2=1.5, GPC (2,6；4) its AD value is 4/3=
1.333, due to 1.5>1.333, therefore GPC (6；3) priority ratio GPC (2,6；4) it is high.
If optimization aim is the product optimization of sequential area, the product (being designated as APD) of PD and AD is sequence benchmark.Such as GPC (6；3)
APD be 10.239*1.5=15.3585, GPC (2,6；4) APD values are 12.658*1.333=16.8731, due to
18.8731>15.3585, therefore GPC (2,6；4) priority ratio GPC (6；3) it is high.
Design optimization target is for area-optimized in the specific embodiment of the invention, is input into using GPC when being ranked up defeated
With the ratio E for using resource as order standard, this ratio shows that more greatly correspondence GPC can more use less money to the difference for going out number
Compress more input in source.GPC used in the present embodiment is GPC (1,4,1,5；5)、GPC(4；3) with GPC (3；2), they
The hardware resource of occupancy is respectively 42 and 1 LUT, and they to be input into and be respectively 6,1 and 1 with the difference of output, three GPC
Corresponding E values respectively 6/4=1.5,1/2=0.5,1/1=1, and 1.5>1>0.5, thus these three GPC according to priority from
High to Low sequence is followed successively by GPC (1,4,1,5；5)、GPC(3；2) with GPC (4；3).
It is further used as preferred embodiment, in step B, operand two-dimensional lattice figure is represented, such as Fig. 4 institutes
Show.
Fig. 4 is the corresponding two-dimensional points systems of battle formations of Fig. 3, the two-dimensional points system of battle formations by the operand for participating in computing it is abstract be a two-dimensional points
Battle array, each of which row represents an operand, and each point represents a certain position (value is 0 or 1) of operand, the point of the leftmost side
For the highest order of be expert at operand, the point of the rightmost side is the lowest order of be expert at operand, a little institute of institute on any string
The weight of representative is identical.
Fig. 5 lists the dot chart method for expressing of several different GPC.In the present embodiment, the output point system of battle formations of GPC networks
Each column is up to the output of 2 points, i.e. GPC networks and can constitute two new operands and is input in follow-up adder.
It is further used as preferred embodiment, in step C1, GPC is a kind of with M-bit input n-bit output
Circuit structure, its function be calculate representated by all inputs 1 number summation, and be expressed as the unsigned number of n-bit
As output result.Each of which is input into all with certain weight, and this weight represents the individual of the 1 of the actual representative of correspondence input
Number, if some input is actually entered as A (being only 0 or 1), its weight is W, then this input it is actual represent 1
Number is A*2W.GPC symbols can be designated as：(mk-1,mk-2,…,m1,m0；N), wherein mk-1>0,miMiddle i represents the weight of input, mi
Represent weight as i input number, k represents input digit, and n represents output digit, and has：
GPC can constantly compress the two-dimensional points system of battle formations being abstracted into by multiple operands, finally give the operation of required number
Number.The input number that can be reduced due to GPC not of the same race, the hardware resource for using, the time delay for being input to output are all different,
Therefore prioritization can be carried out to GPC according to different designs optimization aim, and is pressed using limit priority GPC as far as possible
Contracting.
It is further used as preferred embodiment, in step C2, the compressed tree is used to that many numbers to be sued for peace
And using it and as output, the compressed tree information of preservation includes the generalized parallel enumerator that the series of compressed tree, every one-level are used
Type and using number and the input/output information of last adder.
Compressed tree described in step C2 be it is a kind of many numbers can be sued for peace and using itself and as output structure,
Including GPC networks and adder two parts.GPC networks are divided into multiple levels (being assumed to be N levels), can choose according to algorithm policy per one-level
Inputs of the different GPC to this grade is selected to be compressed.1st grade of input be by multiple groups of operands into be originally inputted；To it
For its level, the input when prime is constituted by all grades before prime of remaining outputs and the remaining input being originally inputted.
Finally, the dot chart of number point needed for N levels GPC network is no more than initial dot chart boil down to each column.Finally by GPC
The output point system of battle formations of network is sued for peace as the input of adder, and finally gives the sum of multiple operands.
With reference to Fig. 6, by taking the GPC networks that the present embodiment is generated as an example：In figure frame for solid line rectangle represent GPC (1,4,
1,5；5), the point at solid line connecting line two ends represents GPC (1,4,1,5；5) output；Frame represents GPC (4 for the rectangle of dotted line；
3), the point of two sections of dashed connection line represents GPC (4；3) output；Frame is that the rectangle for having center pecked line represents GPC (3；2),
The point for having two sections of the connecting line of center pecked line represents GPC (3；2) output.GPC networks have 3 grades in the present embodiment, and first
Level has used 1 GPC (1,4,1,5；5) with 2 GPC (4；3), the second level has used 2 GPC (3；2), the third level has used 1
Individual GPC (3；2), as shown in Figure 6.The input of output adder as after of the third level, obtains multioperand and adds Jing after computing
The result of method.
It is further used as preferred embodiment, in step C, the input of the compressed tree is multioperand addition
Operand, the compressed tree is output as the sum of the operand of multioperand addition, the function and multioperand of the compressed tree
The addition function of addition is identical.
With reference to Fig. 7, a kind of multioperand addition optimization system in High Level Synthesis instrument, the system includes：
Acquiring unit, the high layer function for obtaining circuit design is described, and then obtains what the circuit design was included
Arithmetic operation and operand；
Judging unit, for judging acquiring unit in the arithmetic operation that obtains whether there is the operand of 3 or more than 3
It is continuous to be added, addition optimization processing unit is if so, then loaded into, and into this processing unit of execution, otherwise then terminate；
Addition optimization processing unit, for reading user profile in optimization aim data, according to optimization aim number
According to setting up compressed tree, and preserve compressed tree information；
Code generating unit, the compressed tree information for being preserved according to addition optimization processing unit generates compression that can be comprehensive
Tree HDL code.
With reference to Fig. 8, it is further used as preferred embodiment, the addition optimization processing unit includes：
Order module, for reading user profile and obtaining design optimization target data, according to optimization aim data
Prioritization is carried out to generalized parallel enumerator；
Generation module, for using the generalized parallel enumerator of prioritization was carried out in order module to multiple operations
Number is processed, and is generated compressed tree and is preserved compressed tree information.
It is further used as preferred embodiment, in the judging unit, operand two-dimensional lattice figure is represented.
It is further used as preferred embodiment, in the generation module, the compressed tree is used to be asked many numbers
With and using it and as output, series that the compressed tree information of preservation includes compressed tree, the generalized parallel used per one-level are counted
Device type and using number and the input/output information of last adder.
It is further used as preferred embodiment, in the addition optimization processing unit, the input of the compressed tree is many
The operand of operand addition, the compressed tree is output as the sum of the operand of multioperand addition, the work(of the compressed tree
Can be identical with the addition function of multioperand addition.
Above the preferable enforcement to the present invention is illustrated, but the invention is not limited to the embodiment,
Those of ordinary skill in the art can also make a variety of equivalent variations or replacement on the premise of without prejudice to spirit of the invention,
The deformation or replacement of these equivalents is all contained in the application claim limited range.
Claims (10)
1. the multioperand addition optimization method in a kind of High Level Synthesis instrument, it is characterised in that：Include following steps：
The high layer function description of A, acquisition circuit design, and then obtain arithmetic operation and the operation that the circuit design is included
Number；
B, judge that the operand whether arithmetic operation obtained in step A occurs 3 or more than 3 is continuously added, if so, then carry
Enter addition optimization processing unit, and this processing unit is performed into step C, otherwise then terminate；
C, the optimization aim data read in user profile, according to optimization aim data compressed tree is set up, and preserves compression
Tree information；
D, being generated according to the compressed tree information preserved in step C can comprehensive compressed tree HDL code.
2. the multioperand addition optimization method in a kind of High Level Synthesis instrument according to claim 1, its feature exists
In：Step C is specifically included：
C1, read user profile and obtain optimization aim data, and generalized parallel enumerator is carried out according to optimization aim
Prioritization；
C2, use are processed multiple operands through the generalized parallel enumerator of prioritization, are generated compressed tree and are simultaneously protected
Deposit compressed tree information.
3. the multioperand addition optimization method in a kind of High Level Synthesis instrument according to claim 1 and 2, its feature
It is：In step B, operand two-dimensional lattice figure is represented.
4. the multioperand addition optimization method in a kind of High Level Synthesis instrument according to claim 2, its feature exists
In：In step C2, the compressed tree is used to that many numbers to be sued for peace and using it and as output, the compressed tree letter of preservation
Series that breath includes compressed tree, the generalized parallel counter type used per one-level and use number and finally adder
Input/output information.
5. the multioperand addition optimization method in a kind of High Level Synthesis instrument according to claim 1 and 2, its feature
It is：In step C, the input of the compressed tree is the operand of multioperand addition, and the compressed tree is output as many
The sum of the operand of operand addition, the function of the compressed tree is identical with the addition function of multioperand addition.
6. the multioperand addition in a kind of High Level Synthesis instrument optimizes system, it is characterised in that：The system includes：
Acquiring unit, the high layer function for obtaining circuit design is described, and then obtains the computing that the circuit design is included
Operation and operand；
Judging unit, for judging acquiring unit in the arithmetic operation that obtains the operand of 3 or more than 3 whether occur continuous
It is added, is if so, then loaded into addition optimization processing unit, and into this processing unit of execution, otherwise then terminate；
Addition optimization processing unit, for reading user profile in optimization aim data, built according to optimization aim data
Vertical compressed tree, and preserve compressed tree information；
Code generating unit, the compressed tree information for being preserved according to addition optimization processing unit generates compressed tree that can be comprehensive
HDL code.
7. the multioperand addition in a kind of High Level Synthesis instrument according to claim 6 optimizes system, and its feature exists
In：The addition optimization processing unit includes：
Order module, for reading user profile and obtaining design optimization target data, according to optimization aim data to wide
Adopted parallel counter carries out prioritization；
Generation module, for being entered to multiple operands using the generalized parallel enumerator that prioritization was carried out in order module
Row is processed, and is generated compressed tree and is preserved compressed tree information.
8. the multioperand addition in a kind of High Level Synthesis instrument according to claim 6 or 7 optimizes system, its feature
It is：In the judging unit, operand two-dimensional lattice figure is represented.
9. the multioperand addition in a kind of High Level Synthesis instrument according to claim 6 or 7 optimizes system, its feature
It is：In the generation module, the compressed tree is used to that many numbers to be sued for peace and using it and as output, the compression of preservation
The series of tree information including compressed tree, the generalized parallel counter type used per one-level and use number and last addition
The input/output information of device.
10. the multioperand addition in a kind of High Level Synthesis instrument according to claim 6 or 7 optimizes system, and it is special
Levy and be：In the addition optimization processing unit, the operand being input into as multioperand addition of the compressed tree, the compression
Tree is output as the sum of the operand of multioperand addition, the function of the compressed tree and the addition function phase of multioperand addition
Together.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108009348A (en) * | 2017-11-30 | 2018-05-08 | 上海安路信息科技有限公司 | Plus/minus musical instruments used in a Buddhist or Taoist mass optimization method based on input bit time delay |
| CN109583360A (en) * | 2018-11-26 | 2019-04-05 | 中山大学 | A kind of video human Activity recognition method indicated based on space time information and level |
| CN113658623A (en) * | 2021-08-20 | 2021-11-16 | 湘潭大学 | Ferroelectric memory array capable of realizing multi-operand memory calculation |
| WO2024060446A1 (en) * | 2022-09-22 | 2024-03-28 | 中山大学 | Rapid linear programming method for high-level synthesis |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104360906A (en) * | 2014-10-31 | 2015-02-18 | 中山大学 | High-level comprehensive scheduling method based on difference constraint system and iterative model |
| CN104408232A (en) * | 2014-10-30 | 2015-03-11 | 中山大学 | Combinational logic optimization method and system in high-level synthesis |
| CN105005638A (en) * | 2015-06-04 | 2015-10-28 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | High-level comprehensive dispatching method based on linear delaying model |
-
2016
- 2016-11-16 CN CN201611009866.4A patent/CN106682258B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104408232A (en) * | 2014-10-30 | 2015-03-11 | 中山大学 | Combinational logic optimization method and system in high-level synthesis |
| CN104360906A (en) * | 2014-10-31 | 2015-02-18 | 中山大学 | High-level comprehensive scheduling method based on difference constraint system and iterative model |
| CN105005638A (en) * | 2015-06-04 | 2015-10-28 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | High-level comprehensive dispatching method based on linear delaying model |
Non-Patent Citations (1)
| Title |
|---|
| 光焱等: "一种基于FPGA的SHA-512算法高速实现", 《信息工程大学学报》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108009348A (en) * | 2017-11-30 | 2018-05-08 | 上海安路信息科技有限公司 | Plus/minus musical instruments used in a Buddhist or Taoist mass optimization method based on input bit time delay |
| CN109583360A (en) * | 2018-11-26 | 2019-04-05 | 中山大学 | A kind of video human Activity recognition method indicated based on space time information and level |
| CN109583360B (en) * | 2018-11-26 | 2023-01-10 | 中山大学 | Video human body behavior identification method based on spatio-temporal information and hierarchical representation |
| CN113658623A (en) * | 2021-08-20 | 2021-11-16 | 湘潭大学 | Ferroelectric memory array capable of realizing multi-operand memory calculation |
| CN113658623B (en) * | 2021-08-20 | 2024-03-01 | 湘潭大学 | Ferroelectric memory array capable of realizing multi-operand memory calculation |
| WO2024060446A1 (en) * | 2022-09-22 | 2024-03-28 | 中山大学 | Rapid linear programming method for high-level synthesis |
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