CN104408232A - Combinational logic optimization method and system in high-level synthesis - Google Patents
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Abstract
The invention discloses a combinational logic optimization method and system in high-level synthesis. The combinational logic optimization system in the high-level synthesis comprises an obtaining unit, a combinational logic optimization mapping unit and a reconstruction unit. The combinational logic optimization method in the high-level synthesis comprises the following steps of obtaining operations designed in a circuit and a data dependence relationship between the operations; optimizing the combinational logic operations having the data dependence relationship, performing lookup table mapping according to an optimized result, and accordingly constructing a lookup table operation network; replacing the combinational logic operations having the data dependence relationship with the lookup table operation network. The combinational logic optimization method and system in the high-level synthesis can optimize the designing combinational logic in a high-level synthesis stage, remove redundant combinational logic calculations, introduce bottom layer hardware information to the high-level synthesis by adding the lookup table operation, provide more accurate combinational logic time delay and resource expenditure information for a follow-up high-level synthesis step, are beneficial to improvement of performance of each high-level synthesis tool, and can be widely applied to the hardware design field.
Description
Technical field
The present invention relates to hardware design field, particularly relate to the combinatory logic optimization method and system in a kind of High Level Synthesis.
Background technology
High Level Synthesis comprises the steps such as compiling, optimization, scheduling, Resourse Distribute, controller synthesis.Higher level lanquage through compiling with after optimizing, by translated to low level in the middle of express, and as the input of follow-up scheduling and the contour level combining step of Resourse Distribute.
The study hotspot of current High Level Synthesis project is mainly placed on scheduling, Resourse Distribute and controller synthesis, and the step such as combinatory logic optimization and Technology Mapping is given follow-up fpga logic synthesis tool and come, therefore can obtain thus, in High Level Synthesis process, do not relate to the deep optimization for combinational logic operation in design, and Method at Register Transfer Level (RTL) hardware bottom layer information below can be ignored.The problem of two aspects can be caused like this: the combinational logic operation 1, in High Level Synthesis process does not carry out deep optimization, therefore the combinational logic operation of redundancy can be there is, can cause like this for hardware design distributes the too much clock period in scheduling process, thus impact generates the timing performance of hardware; 2, owing to not introducing hardware bottom layer information in High Level Synthesis process, therefore, the hardware generated in order to avoid High Level Synthesis instrument does not meet the sequential and resource requirement that design, then must carry out pessimism to the time delay of combinational logic operation and resource overhead to estimate, so then can cause distributing the unnecessary clock period thus the data throughout of impact generation hardware for designing in scheduling process, and can cause for design distributes less hardware resource in resource allocation process, thus reduce the concurrency of hardware design and have impact on the travelling speed of hardware.
Summary of the invention
In order to solve the problems of the technologies described above, the object of this invention is to provide a kind of combinatory logic optimization method in High Level Synthesis.
Another object of the present invention is to provide the combinatory logic optimization system in a kind of High Level Synthesis.
The technical solution adopted in the present invention is: a kind of combinatory logic optimization method in High Level Synthesis, and the method comprises:
The high layer function of A, acquisition cuicuit design describes, and then obtains the data dependence relation between each operation that this circuit design comprises and each operation;
C, the combinational logic operation with data dependence relation to be optimized, to carry out look-up table mapping according to the result after optimizing, and then build look up table operations network;
The look up table operations network that D, employing build replaces the described combinational logic operation with data dependence relation.
Further, described step D comprises:
The combinational logic operation with data dependence relation described in D1, deletion;
D2, topological sorting is carried out to the look up table operations in operation remaining in this circuit design and look up table operations network;
The topological sorting result that D3, basis obtain in step d 2, thus the look up table operations in remaining operation and look up table operations network is stored.
Further, there is described in being input as of described look up table operations network the input of the combinational logic operation of data dependence relation, the output of described look up table operations network for described in there is the output of the combinational logic operation of data dependence relation, the logic function that described look up table operations network realizes is identical with the logic function that the result after optimization realizes.
Further, described step C is specially: adopt integrated logic synthesis system to be optimized the combinational logic operation with data dependence relation, utilize target devices to carry out look-up table mapping according to the result after optimizing, and then build look up table operations network.
Further, be also provided with step B between described steps A and step C, described step B is:
According to the data dependence relation between each operation obtained and each operation, and then judge whether to exist the combinational logic operation with data dependence relation, if so, then perform step C, otherwise, then terminate.
Another technical scheme of the present invention is: the combinatory logic optimization system in a kind of High Level Synthesis, and this system comprises:
Acquiring unit, the high layer function for acquisition cuicuit design describes, and then obtains the data dependence relation between each operation that this circuit design comprises and each operation;
Combinatory logic optimization map unit, for being optimized the combinational logic operation with data dependence relation, carrying out look-up table mapping according to the result after optimizing, and then building look up table operations network;
Reconfiguration unit, for adopting the look up table operations network of structure to replace the described combinational logic operation with data dependence relation.
Further, described reconfiguration unit comprises:
Removing module, for deleting the described combinational logic operation with data dependence relation;
Order module, for carrying out topological sorting to the look up table operations in operation remaining in this circuit design and look up table operations network;
Build module, for according to the topological sorting result obtained in order module, thus the look up table operations in remaining operation and look up table operations network is stored.
Further, there is described in being input as of described look up table operations network the input of the combinational logic operation of data dependence relation, the output of described look up table operations network for described in there is the output of the combinational logic operation of data dependence relation, the logic function that described look up table operations network realizes is identical with the logic function that the result after optimization realizes.
Further, described combinatory logic optimization map unit is optimized the combinational logic operation with data dependence relation specifically for adopting integrated logic synthesis system, utilize target devices to carry out look-up table mapping according to the result after optimizing, and then build look up table operations network.
Further, judging unit is provided with between described acquiring unit and combinatory logic optimization map unit, described judging unit is used for according to the data dependence relation between each operation obtained and each operation, and then judge whether to exist the combinational logic operation with data dependence relation, if, then perform combinatory logic optimization map unit, otherwise, then terminate.
The invention has the beneficial effects as follows: the application of the invention method, can be optimized the combinational logic in design in the High Level Synthesis stage, thus reduce the redundancy of combinational logic computing, and in High Level Synthesis, introduce bottom hardware information by adding look up table operations, combinational logic time delay and resource overhead information more accurately can be provided for follow-up High Level Synthesis step, so then need not carry out pessimism to the time delay of combinational logic and resource overhead to estimate, be conducive to the performance promoting High Level Synthesis instrument, generate the hardware design that performance is more excellent.
Another beneficial effect of the present invention is: the application of the invention system, can High Level Synthesis perfecting by stage design in combinational logic, remove the combinational logic computing of redundancy, and in High Level Synthesis, introduce bottom hardware information by adding look up table operations, for follow-up High Level Synthesis step provides combinational logic time delay and resource overhead information more accurately, be conducive to the performance promoting High Level Synthesis instrument, generate the hardware design that performance is more excellent.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further:
Fig. 1 is the flow chart of steps of the combinatory logic optimization method in a kind of High Level Synthesis of the present invention;
Fig. 2 is the flow chart of steps of combinatory logic optimization method one specific embodiment in a kind of High Level Synthesis of the present invention;
Fig. 3 is the data dependence relation schematic diagram obtained in the inventive method one specific embodiment;
Fig. 4 is the data dependence relation schematic diagram of the combinational logic operation in the inventive method one specific embodiment with data dependence relation;
Fig. 5 is the data dependence relation schematic diagram between each operation in the inventive method one specific embodiment after operation reconstruct;
Fig. 6 is the structured flowchart of the combinatory logic optimization system in a kind of High Level Synthesis of the present invention;
Fig. 7 is the structured flowchart of combinatory logic optimization system one specific embodiment in a kind of High Level Synthesis of the present invention.
Embodiment
As shown in Figure 1, a kind of combinatory logic optimization method in High Level Synthesis, the method comprises:
The high layer function of A, acquisition cuicuit design describes, and then obtains the data dependence relation between each operation that this circuit design comprises and each operation;
C, the combinational logic operation with data dependence relation to be optimized, to carry out look-up table mapping according to the result after optimizing, and then build look up table operations network;
The look up table operations network that D, employing build replaces the described combinational logic operation with data dependence relation, thus realizes the reconstruct of operation.
According to the difference of actual conditions, described look up table operations network comprises a look up table operations, or described look up table operations network comprises plural look up table operations.
Be further used as preferred embodiment, described step D comprises:
The combinational logic operation with data dependence relation described in D1, deletion;
D2, topological sorting is carried out to the look up table operations in operation remaining in this circuit design and look up table operations network;
The topological sorting result that D3, basis obtain in step d 2, thus the look up table operations in remaining operation and look up table operations network is stored.
Be further used as preferred embodiment, there is described in being input as of described look up table operations network the input of the combinational logic operation of data dependence relation, the output of described look up table operations network for described in there is the output of the combinational logic operation of data dependence relation, the logic function that described look up table operations network realizes is identical with the logic function that the result after optimization realizes.
Be further used as preferred embodiment, described step C is specially: adopt integrated logic synthesis system to be optimized the combinational logic operation with data dependence relation, utilize target devices to carry out look-up table mapping according to the result after optimizing, and then build look up table operations network.
Be further used as preferred embodiment, be also provided with step B between described steps A and step C, described step B is:
According to the data dependence relation between each operation obtained and each operation, and then judge whether to exist the combinational logic operation with data dependence relation, if so, then perform step C, otherwise, then terminate.
One specific embodiment of the inventive method
As shown in Figure 2, a kind of combinatory logic optimization method in High Level Synthesis, it specifically comprises:
The high layer function of S1, acquisition cuicuit design describes, and then the data dependence relation obtained between each operation that this circuit design comprises and each operation, in the present embodiment, data dependence relation between each operation as shown in Figure 3, a node on behalf one operation in figure, the flow direction of direction of arrow representative data, the data dependence relation namely between each operation.
S2, according to obtain each operation and each operation between data dependence relation, and then judge whether to exist have data dependence relation combinational logic operation, if so, then perform step S3, otherwise, then terminate.For the operation of described combinational logic, its action type that can comprise have with operation or operate, not operation and xor operation, such as: described combinational logic operation can comprise two with operate; Described combinational logic operation can comprise one with operation, one or operate and an xor operation; Or described combinational logic operation can comprise two or operation and a not operation.
In the present embodiment, the combinational logic operation with data dependence relation comprise or operate OR1 or operation OR2 or operation OR3, with operate AND1 and or operate OR4, and their data dependence relation can be as shown in Figure 4.
S3, adopt integrated logic synthesis system to have data dependence relation combinational logic operation be optimized.In the present embodiment, by integrated logic synthesis system, combinational logic operation (((In_1|In_2) & (In_2|In_3)) | (In_4|In_5)) shown in Fig. 4 is optimized for ((In_2| (In_1 & In_3)) | (In_4|In_5)), wherein symbol " | " and " & " represent respectively or operate and with operation.Can obtain thus, the combinational logic operation with data dependence relation is optimized, then be equivalent to the simplification combinational logic operation with data dependence relation being carried out to combinational logic computing.
S4, according to the result ((In_2| (In_1 & In_3)) | (In_4|In_5)) after optimizing, thus utilize target devices to carry out look-up table mapping, and then build look up table operations network.
In the present embodiment, the target devices adopted, it is 4 input look-up table configuration, therefore, according to the look-up table mapping mode in integrated logic synthesis system, the result ((In_2| (In_1 & In_3)) | (In_4|In_5)) after optimizing can be mapped on two look-up tables by integrated logic synthesis system.And different according to adopted target devices and after optimizing result is different, the result after optimization can be mapped on a look-up table or plural look-up table by integrated logic synthesis system.
Wherein, combinational logic computing in result after optimization (In_2| (In_1 & In_3)) is mapped on first look-up table, described first look-up table be input as In_1, In_2 and In_3, export as OUT1, and its logic function truth table information is as shown in table 1.
Table 1
| Input | Input | Input | Export |
| In_2 | In_1 | In_3 | OUT1 |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 |
And optimize after result in combinational logic computing (OUT1| (In_4|In_5)) be mapped on second look-up table, described second look-up table be input as In_4, In_5 and OUT1, export as OUT2, and its logic function truth table information is as shown in table 2.
Table 2
| Input | Input | Input | Export |
| OUT1 | In_4 | In_5 | OUT2 |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 |
According to look-up table map information obtained above, first look-up table obtained after namely carrying out look-up table mapping and second look-up table, thus build corresponding the first look up table operations (LUT1) and second look-up table operation (LUT2).
According to the first look-up table obtained, thus build corresponding the first look up table operations (LUT1), even be namely input as In_1, In_2 and In_3(of the first look up table operations (LUT1) operate ADD1, MUL1 and ADD2 for LUT1 and provide input), export as OUT1, and its logic function truth table information is identical with above-mentioned table 1; According to the second look-up table obtained, thus build corresponding second look-up table operation (LUT2), even be namely input as In_4, In_5 and OUT1(of second look-up table operation (LUT2) operate LUT1, ADD3 and ADD4 for LUT2 and provide input), export as OUT2, and its logic function truth table information is identical with above-mentioned table 2.Can obtain thus, look up table operations network constructed in the present embodiment comprises the first look up table operations (LUT1) and second look-up table operation (LUT2), and it is known to operate (LUT2) by constructed the first look up table operations (LUT1) and second look-up table, described look up table operations network be input as In_1, In_2, In_3, In_4, In_5, namely there is described in being input as of described look up table operations network the input of the combinational logic operation of data dependence relation, the output of described look up table operations network is OUT2, namely described look up table operations network output for described in have data dependence relation combinational logic operation output, and the logic function that described look up table operations network realizes is identical with the logic function that the result after optimization realizes.
Being obtained by above-mentioned, by adopting the look up table operations network of above-mentioned structure to replace the original combinational logic operation with data dependence relation, just according to the information searching of input to corresponding output information, and then can export.
The look up table operations network that S5, employing build replaces the described combinational logic operation with data dependence relation, and it specifically comprises:
The combinational logic operation with data dependence relation described in S51, deletion, namely deletes combinational logic operation OR1, OR2, OR3, AND1 and the OR4 shown in Fig. 3;
S52, to operation remaining in this circuit design, namely ADD1, MUL1, ADD2, ADD3, ADD4, ADD5 and MUL2 is operated, and the look up table operations in look up table operations network, i.e. the first look up table operations LUT1 and second look-up table operation LUT2, carry out topological sorting, and the topological sorting result obtained is ADD1 → MUL1 → ADD2 → LUT1 → ADD3 → ADD4 → LUT2 → ADD5 → MUL2;
The topological sorting result that S53, basis obtain in step S52, thus to remaining operation, namely ADD1, MUL1, ADD2, ADD3, ADD4, ADD5 and MUL2 is operated, and the look up table operations in look up table operations network, namely the first look up table operations LUT1 and second look-up table operation LUT2, stores.Because the topological sorting result obtained in step S52 is ADD1 → MUL1 → ADD2 → LUT1 → ADD3 → ADD4 → LUT2 → ADD5 → MUL2, therefore, operation ADD1, MUL1, ADD2, ADD3, ADD4, ADD5, MUL2, LUT1 and LUT2, the sequencing that they store is: store operation ADD1, MUL1, ADD2, LUT1, ADD3, ADD4, LUT2, ADD5 and MUL2 successively after arriving first.Like this, the data dependence relation schematic diagram between final each operation generated as shown in Figure 5.
By adopting above-mentioned steps S52 and S53, like this in the process of sequence of operation execution, just can ensure for the first look up table operations LUT1 provide input each operation, namely ADD1, MUL1 and ADD2 is operated, after being all finished, just perform the first look up table operations LUT1, and ensure as second look-up table operates each operation that LUT2 provides input, namely operate after LUT1, ADD3 and ADD4 be finished, just perform second look-up table operation LUT2, that is, by adopting above-mentioned steps S52 and S53, the correctness of circuit design can be ensured.
For the content of the invention described above method, it is also applicable in the system of the following stated.
As shown in Figure 6 and Figure 7, the combinatory logic optimization system in a kind of High Level Synthesis, this system comprises:
Acquiring unit, the high layer function for acquisition cuicuit design describes, and then obtains the data dependence relation between each operation that this circuit design comprises and each operation;
Combinatory logic optimization map unit, for being optimized the combinational logic operation with data dependence relation, carrying out look-up table mapping according to the result after optimizing, and then building look up table operations network;
Reconfiguration unit, for adopting the look up table operations network of structure to replace the described combinational logic operation with data dependence relation.
Be further used as preferred embodiment, described reconfiguration unit comprises:
Removing module, for deleting the described combinational logic operation with data dependence relation;
Order module, for carrying out topological sorting to the look up table operations in operation remaining in this circuit design and look up table operations network;
Build module, for according to the topological sorting result obtained in order module, thus the look up table operations in remaining operation and look up table operations network is stored.
Be further used as preferred embodiment, there is described in being input as of described look up table operations network the input of the combinational logic operation of data dependence relation, the output of described look up table operations network for described in there is the output of the combinational logic operation of data dependence relation, the logic function that described look up table operations network realizes is identical with the logic function that the result after optimization realizes.
Be further used as preferred embodiment, described combinatory logic optimization map unit is optimized the combinational logic operation with data dependence relation specifically for adopting integrated logic synthesis system, utilize target devices to carry out look-up table mapping according to the result after optimizing, and then build look up table operations network.
Be further used as preferred embodiment, judging unit is provided with between described acquiring unit and combinatory logic optimization map unit, described judging unit is used for according to the data dependence relation between each operation obtained and each operation, and then judge whether to exist the combinational logic operation with data dependence relation, if, then perform combinatory logic optimization map unit, otherwise, then terminate.
More than that better enforcement of the present invention is illustrated, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite without prejudice to spirit of the present invention, and these equivalent distortion or replacement are all included in the application's claim limited range.
Claims (10)
1. the combinatory logic optimization method in High Level Synthesis, is characterized in that: the method comprises:
The high layer function of A, acquisition cuicuit design describes, and then obtains the data dependence relation between each operation that this circuit design comprises and each operation;
C, the combinational logic operation with data dependence relation to be optimized, to carry out look-up table mapping according to the result after optimizing, and then build look up table operations network;
The look up table operations network that D, employing build replaces the described combinational logic operation with data dependence relation.
2. a kind of combinatory logic optimization method according to claim 1 in High Level Synthesis, is characterized in that: described step D comprises:
The combinational logic operation with data dependence relation described in D1, deletion;
D2, topological sorting is carried out to the look up table operations in operation remaining in this circuit design and look up table operations network;
The topological sorting result that D3, basis obtain in step d 2, thus the look up table operations in remaining operation and look up table operations network is stored.
3. the combinatory logic optimization method in a kind of High Level Synthesis according to claim 1 or 2, it is characterized in that: the input described in being input as of described look up table operations network with the combinational logic operation of data dependence relation, the output of described look up table operations network for described in there is the output of the combinational logic operation of data dependence relation, the logic function that described look up table operations network realizes is identical with the logic function that the result after optimization realizes.
4. the combinatory logic optimization method in a kind of High Level Synthesis according to claim 1 or 2, it is characterized in that: described step C is specially: adopt integrated logic synthesis system to be optimized the combinational logic operation with data dependence relation, utilize target devices to carry out look-up table mapping according to the result after optimizing, and then build look up table operations network.
5. the combinatory logic optimization method in a kind of High Level Synthesis according to claim 1 or 2, is characterized in that: be also provided with step B between described steps A and step C, and described step B is:
According to the data dependence relation between each operation obtained and each operation, and then judge whether to exist the combinational logic operation with data dependence relation, if so, then perform step C, otherwise, then terminate.
6. the combinatory logic optimization system in High Level Synthesis, is characterized in that: this system comprises:
Acquiring unit, the high layer function for acquisition cuicuit design describes, and then obtains the data dependence relation between each operation that this circuit design comprises and each operation;
Combinatory logic optimization map unit, for being optimized the combinational logic operation with data dependence relation, carrying out look-up table mapping according to the result after optimizing, and then building look up table operations network;
Reconfiguration unit, for adopting the look up table operations network of structure to replace the described combinational logic operation with data dependence relation.
7. the combinatory logic optimization system according to claim 6 in a kind of High Level Synthesis, is characterized in that: described reconfiguration unit comprises:
Removing module, for deleting the described combinational logic operation with data dependence relation;
Order module, for carrying out topological sorting to the look up table operations in operation remaining in this circuit design and look up table operations network;
Build module, for according to the topological sorting result obtained in order module, thus the look up table operations in remaining operation and look up table operations network is stored.
8. the combinatory logic optimization system in a kind of High Level Synthesis according to claim 6 or 7, it is characterized in that: the input described in being input as of described look up table operations network with the combinational logic operation of data dependence relation, the output of described look up table operations network for described in there is the output of the combinational logic operation of data dependence relation, the logic function that described look up table operations network realizes is identical with the logic function that the result after optimization realizes.
9. the combinatory logic optimization system in a kind of High Level Synthesis according to claim 6 or 7, it is characterized in that: described combinatory logic optimization map unit is optimized the combinational logic operation with data dependence relation specifically for adopting integrated logic synthesis system, utilize target devices to carry out look-up table mapping according to the result after optimizing, and then build look up table operations network.
10. the combinatory logic optimization system in a kind of High Level Synthesis according to claim 6 or 7, it is characterized in that: between described acquiring unit and combinatory logic optimization map unit, be provided with judging unit, described judging unit is used for according to the data dependence relation between each operation obtained and each operation, and then judge whether to exist the combinational logic operation with data dependence relation, if, then perform combinatory logic optimization map unit, otherwise, then terminate.
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| CN106682258A (en) * | 2016-11-16 | 2017-05-17 | 中山大学 | Method and system for multi-operand addition optimization in high-level synthesis tool |
| CN106599370B (en) * | 2016-11-16 | 2019-12-13 | 中山大学 | automatic generation method and system for guide file in high-level comprehensive tool |
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