CN113658623A - Ferroelectric memory array capable of realizing multi-operand memory calculation - Google Patents
Ferroelectric memory array capable of realizing multi-operand memory calculation Download PDFInfo
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Abstract
The invention discloses a ferroelectric memory array capable of realizing multi-operand memory calculation, which comprises a sensing and multi-valued calculation unit, a sensing line driver and an address decoder, wherein the sensing and multi-valued calculation unit is connected with a memory array, and the memory array is connected with a forwarding row unit; the address decoder is connected with the memory array; the sensing and multivalued calculating unit is connected with the input end of the output buffer, the output end of the output buffer is connected with the first input end of the first data selector, the first input end of the second data selector and the input end of the input buffer, the output end of the first data selector is connected with the forwarding row unit, the output end of the input buffer is connected with the second input end of the second data selector, and the output end of the second data selector is connected with the memory array after passing through the sensing line driver. The present invention is applicable to all resistive-based cell designs, which require only N/2 clock cycles for CiM operations with N operands.
Description
Technical Field
The invention relates to the field of circuits, in particular to a ferroelectric memory array capable of realizing multi-operand memory calculation.
Background
The current computing mechanism of the storage and computation integrated architecture only considers the case of computing two operands in one clock cycle. This also means that when a command needs to be executed on N lines, N-1 clock cycles are required to operate. In addition, existing memory integrated architectures implement bitwise logic operations primarily by sensing the resulting current/voltage of the bit line and comparing it to a reference current/voltage. But multiple operands require more reference currents or voltages, which also results in high design costs. Therefore, how to effectively control the reference number when executing multiple operands is an inevitable problem.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a ferroelectric memory array capable of implementing multi-operand memory calculation, which has a simple structure and a wide application range.
The technical scheme for solving the problems is as follows: a ferroelectric memory array capable of realizing multi-operand memory calculation comprises a memory array, a sensing and multi-valued calculation unit, a sensing line driver, a forwarding row unit and an address decoder, wherein the sensing and multi-valued calculation unit is connected with the memory array, and the memory array is connected with the forwarding row unit; the address decoder is connected with the memory array and used for selecting rows or columns needing to be operated to carry out bitwise logic operation and obtaining an operation result in the sensing/multi-value calculation module; the sensing and multivalued computing unit is connected with the input end of the output buffer, the output end of the output buffer is connected with the first input end of the first data selector, the first input end of the second data selector and the input end of the input buffer, the I/O buffer is connected with the input end of the input buffer and the second input end of the first data selector, the output end of the first data selector is connected with the forwarding row unit, the output end of the input buffer is connected with the second input end of the second data selector, and the output end of the second data selector is connected with the memory array through the sensing line driver.
The ferroelectric memory array capable of realizing multi-operand memory calculation comprises a pre-charging circuit, a current mirror unit and an inverter group.
The ferroelectric memory array capable of realizing multi-operand memory calculation comprises a third data selector, a fourth data selector, a fifth data selector, a first switch, a second switch, a third switch, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first ferroelectric field effect transistor and a second ferroelectric field effect transistor, wherein a first input end of the third data selector is used as a first bit line end and connected with an output end of the fourth data selector, a first input end of the fourth data selector is a ground end, and a second input end of the fourth data selector is connected with a forwarding row unit; a second input end of the third data selector is used as a second bit line end and is connected with the forwarding line unit after passing through a third switch; the third input end of the third data selector is used as a sensing line end and connected with the output end of the fifth data selector, the first input end of the fifth data selector is connected with the switching and issuing unit, and the second input end of the fifth data selector is used as a ground end; the output end of the third data selector is connected with a pre-charging circuit of the sensing and multi-value computing unit, a current mirror unit of the sensing and multi-value computing unit is connected with a second bit line end after passing through the first switch, and an inverter group of the sensing and multi-value computing unit is connected with a sensing line end after passing through the second switch; the grid electrodes of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are all used as control ends, the drain electrode of the first MOS tube is connected with the second bit line end, the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube, the drain electrode of the second MOS tube and the drain electrode of the fourth MOS tube are both connected with the first bit line end, the source electrode of the fourth MOS tube is connected with the source electrode of the third MOS tube, the drain electrode of the third MOS tube is connected with the second bit line end, the grid electrode of the first ferroelectric field effect tube is used as a writing end, the drain electrode of the first ferroelectric field effect tube is connected with the source electrode of the first MOS tube, the source electrode of the first ferroelectric field effect tube is connected with a sensing line end, the grid electrode of the second ferroelectric field effect tube is used as a writing end, the drain electrode of the second ferroelectric field effect tube is connected with the source electrode of the third MOS tube, and the source electrode of the second ferroelectric field effect tube is connected with the sensing line end.
The ferroelectric memory array capable of realizing multi-operand memory calculation comprises a transfer unit and a transfer unit, wherein the transfer unit comprises a fifth MOS tube, a sixth MOS tube and a TG gate, a grid electrode of the fifth MOS tube is used as a control end, a drain electrode of the fifth MOS tube is connected with a second input end of a fourth data selector, a third switch and a first input end of a fifth data selector, a source electrode of the fifth MOS tube is connected with VDD after passing through the TG gate, a grid electrode of the sixth MOS tube is used as a control end, a drain electrode of the sixth MOS tube is connected with the source electrode of the fifth MOS tube, and a source electrode of the sixth MOS tube is grounded.
The invention has the beneficial effects that: under the condition of no extra reference current, each MOS tube in the cell is utilized to form a voltage divider, when bitwise logic operation is carried out, the voltage change of a sensing line is influenced by different logic values stored in the cell, and the memory calculation result can be output through a skew phase inverter.
Drawings
FIG. 1 is an architectural diagram of the present invention.
Fig. 2 is a block diagram of a 3T cell based on a ferroelectric field effect transistor according to the present invention.
FIG. 3 is a SA architecture diagram of the array provided by the present invention.
Fig. 4 is an equivalent circuit diagram of the present invention implementing an OR operation.
Fig. 5 is an equivalent circuit diagram of the present invention for implementing the AND operation.
Fig. 6 is an equivalent circuit diagram of the present invention implementing XOR operations.
Fig. 7 is a diagram of a forwarding row unit structure provided in the present invention.
Fig. 8 is an equivalent circuit diagram of the present invention implementing multi-operand a.b.c logic.
FIG. 9 is an equivalent circuit diagram of the present invention for implementing multi-operand A + B + C logic.
Fig. 10 is an equivalent circuit diagram of the invention for implementing multi-operand a ≦ B ≦ C logic.
FIG. 11 is a truth table for implementing multi-operand A ≦ C logic according to the present invention.
FIG. 12 is an equivalent circuit diagram of the present invention implementing multi-operand AB + C logic.
FIG. 13 is an equivalent circuit diagram of the present invention for implementing multi-operand (A + B) C logic.
Fig. 14 is a waveform diagram of the multi-operand a.b.c logic implemented in accordance with the present invention.
FIG. 15 is a waveform diagram of the implementation of the multiple operand A + B + C logic of the present invention.
Fig. 16 is a waveform diagram of the logic for implementing multiple operands a ≦ B ≦ C according to the present invention.
FIG. 17 is a waveform diagram of the multi-operand AB + C logic implemented in accordance with the present invention.
FIG. 18 is a waveform diagram of the multi-operand (A + B) C logic implementation of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings and examples.
As shown in fig. 1, fig. 2, and fig. 3, a ferroelectric memory array capable of implementing multi-operand memory computation includes a memory array, a sensing and multi-valued computation unit, a sensing line driver, a forwarding row unit, and an address decoder, where the sensing and multi-valued computation unit is connected to the memory array, and the memory array is connected to the forwarding row unit; the address decoder is connected with the memory array and used for selecting rows or columns needing to be operated to carry out bitwise logic operation and obtaining an operation result in the sensing/multi-value calculation module; the sensing and multivalued computing unit is connected with the input end of the output buffer, the output end of the output buffer is connected with the first input end of the first data selector, the first input end of the second data selector and the input end of the input buffer, the I/O buffer is connected with the input end of the input buffer and the second input end of the first data selector, the output end of the first data selector is connected with the forwarding row unit, the output end of the input buffer is connected with the second input end of the second data selector, and the output end of the second data selector is connected with the memory array through the sensing line driver.
The sensing and multivalued calculation unit includes a precharge circuit Pre, a current Mirror unit Mirror, and an inverter group inv.
The memory array comprises a third data selector MUX1, a fourth data selector MUX2, a fifth data selector MUX3, a first switch TG1, a second switch TG2, a third switch TG3, a first MOS transistor T1, a second MOS transistor T2, a third MOS transistor T3, a fourth MOS transistor T4, a first ferroelectric field effect transistor F1 and a second ferroelectric field effect transistor F2, wherein a first input end of the third data selector MUX1 is used as a first bit line end and connected with an output end of the fourth data selector MUX2, a first input end of the fourth data selector MUX2 is used as a ground end, and a second input end of the fourth data selector MUX2 is connected with a forwarding row unit; a second input end of the third data selector MUX1 is used as a second bit line end and is connected with the forwarding row unit after passing through a third switch TG 3; a third input terminal of the third data selector MUX1 is used as a sensing line terminal and is connected to the output terminal of the fifth data selector MUX3, a first input terminal of the fifth data selector MUX3 is connected to the issue unit, and a second input terminal of the fifth data selector MUX3 is a ground terminal; the output end of the third data selector MUX1 is connected with the precharge circuit of the sensing and multivalued computing unit, the current mirror unit of the sensing and multivalued computing unit is connected with the second bit line end after passing through the first switch TG1, and the inverter group of the sensing and multivalued computing unit is connected with the sensing line end after passing through the second switch TG 2; the gates of the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3 and the fourth MOS transistor T4 are all used as control terminals, the drain of the first MOS transistor T1 is connected to the second bit line terminal, the source of the first MOS transistor T1 is connected to the source of the second MOS transistor T2, the drain of the second MOS transistor T2 and the drain of the fourth MOS transistor T4 are both connected to the first bit line terminal, the source of the fourth MOS transistor T4 is connected to the source of the third MOS transistor T3, the drain of the third MOS transistor T3 is connected to the second bit line terminal, the gate of the first ferroelectric field effect transistor F1 is used as a write terminal, the drain of the first ferroelectric field effect transistor F1 is connected to the source of the first MOS transistor T1, the source of the first ferroelectric field effect transistor F1 is connected to the sense line terminal, the gate of the second ferroelectric field effect transistor F2 is used as a write terminal, the drain of the second ferroelectric field effect transistor F2 is connected to the source of the third MOS transistor T3, and the source of the second ferroelectric field effect transistor F2 is connected to the sense line terminal.
As shown in fig. 7, the issue unit includes a fifth MOS transistor Tf1, a sixth MOS transistor Tf2 and a TG gate, a gate SA-WB of the fifth MOS transistor Tf1 is used as a control terminal, a drain of the fifth MOS transistor Tf1 is connected to MUX2/TG3/MUX3, a source of the fifth MOS transistor Tf1 is connected to VDD through the TG gate, a gate Ctrl of the sixth MOS transistor Tf2 is used as a control terminal, a drain of the sixth MOS transistor Tf2 is connected to the source of the fifth MOS transistor Tf1, and a source of the sixth MOS transistor Tf2 is grounded.
And (3) conventional memory calculation:
for the OR operation, as shown in FIG. 4:
1. the MUX1 is activated, the TG1 and the TG2 are closed, and the SL is connected to a pre-charging circuit in the SA;
2. activating the ground port of MUX2 to ground BLD, TG3, MUX3 in the off state;
3. activating T2, T4 may connect A, B two memory cells in parallel in the circuit;
4. inputting a clock signalThe port, when the clock is low, the circuit is active and the voltage state on SL will be read by both inverters. The OR output is low only when both cells A, B are in the high impedance state, and high otherwise.
For the AND operation, as shown in FIG. 5:
1. the MUX1 is activated, TG1 and TG2 are closed, and the BLU is connected to a pre-charging circuit in the SA;
2. activating the ground port of MUX2 to ground BLD, TG3, MUX3 in the off state;
3. activating T1, T4 may connect A, B two memory cells in series in the circuit;
4. inputting a clock signalThe port, when the clock is low, the circuit is active and the voltage state on the BLU will be read by both inverters. The AND output results high only when both cells A, B are in the low resistance state, AND low otherwise.
For XOR operations, as shown in FIG. 6:
1. TG1 and TG2 are activated, MUX1 is turned off, BLU is connected to the current mirror block, SL is connected to the capacitive, skewed inverter bank block;
2. during the execution period, the capacitor C is precharged to 0.4V;
3. the precharge voltage is removed and the enable ports EN, T1 and T4 are briefly opened, while the current mirror M1-T1-F1-F2-T4 constitutes a simple voltage divider. The logic state stored in the two ferroelectric field effect transistors will affect the magnitude of the voltage value on SL;
4. turning off T1 and T4, the capacitor C will maintain the voltage value on SL and the skew inverter bank will read out the XOR output result.
There are four cases of voltage values on SL in the XOR operation: 1) when F1 and F2 are in the high impedance state, SL will remain at the 0.4V precharge voltage. 2) When F1 and F2 are in the low impedance state, SL is maintained at around 0.4V due to the voltage divider structure. 3) When F1 is in the high resistance state and F2 is in the low resistance state, SL will be discharged to low level. 4) When F1 is in the low resistance state and F2 is in the high resistance state, SL will charge to the high level.
When the voltage on SL is much lower than 0.4V, the set of down-biased inverters INVD will output a high level, reading the 01 result (case 3); when the voltage on SL is much higher than 0.4V, the up-skew inverter INVU group will output high, reading out 10 results (case 4); when the voltage on SL is around 0.4V, both inverter groups output low (cases 1, 2). The XOR result is read out by the two skewed inverter groups of access or gates.
For ADD operations:
the ADD operates the same as the XOR operation, and the result may be output along with the XOR result.
1. TG1 and TG2 are activated, MUX1 is turned off, BLU is connected to the current mirror block, SL is connected to the capacitive, skewed inverter bank block;
2. during the execution period, the capacitor C is precharged to 0.4V;
3. the precharge voltage is removed and the enable ports EN, T1 and T4 are briefly opened and the clock signal is input to the Clk port and the current mirror will mirror the current flowing through cell a, input to the sense current amplifier.
4. The reference current Iref is switched in and the sense current amplifier will sense the state stored by cell a when the clock signal of Clk is at the falling edge.
5. The following logical equation may be based for full adder operation:
the ADD result is added to the peripheral module output ADD as shown in figure 6.
Write-back based multi-operand memory computation:
when performing a multi-operand memory calculation, the previous data is input to the forwarding column through the output buffer. The transfer line is composed of two MOS transistors and a TG gate, and functions like a memory column, and the structure is shown in figure 4. The previous output result is sent to SA-WB to control the conduction of Tf1, and the transmission transistor Tf2 and the transmission gate TG control unit are controlled to be grounded or VDD.
For the a.b.c operation, as shown in fig. 8, 14:
1. the MUX1 is activated, TG1 and TG2 are closed, and the BLU is connected to a pre-charging circuit in the SA;
2. activating the forwarding row port of the MUX2 to connect the BLD with the forwarding row unit, and enabling the TG3 and the MUX3 to be in a closed state;
3. t1, T4, Tf2 are activated and the result is written back into Tf 1. At this time A, B, three units of the forwarding row are connected in series in the circuit;
4. inputting a clock signalThe port, when the clock is low, the circuit is active and the voltage state on the BLU will be read by both inverters. The AND output results high only when both cells A, B are in the low resistance state, AND low otherwise.
For a + B + C operation. As shown in fig. 9 and 15:
1. the MUX1 is activated, the TG1 and the TG2 are closed, and the SL is connected to a pre-charging circuit in the SA;
2. activating the ground port of MUX2 to ground the BLD, activating MUX3 to connect the forward row cells into SL;
3. t2, T4, Tf2 are activated and the result is written back into Tf 1. At this time A, B, three units of the forwarding row are connected in parallel in the circuit;
4. inputting a clock signalThe port, when the clock is low, the circuit is active and the voltage state on SL will be read by both inverters. The OR output is low only when all three cells are at logic '0' and high otherwise.
For a ≧ B ≦ C operation. As shown in fig. 10, 11, and 16:
1. TG1 and TG2 are activated, MUX1 is turned off, BLU is connected to the current mirror block, SL is connected to the capacitive, skewed inverter bank block;
2. activating the ground port of MUX2 to ground the BLD, activating MUX3 to connect the forward row cells into SL;
3. during the execution period, the capacitor C is precharged to 0.4V;
4. the precharge voltage is removed and the enable ports EN, T1 and T4 are briefly opened and a clock signal is input to the Clk port, the operating state of the burst is controlled by the result of the output cell a. When the unit A stores logic '1', Tf2 is conducted, and the transmission door is closed; conversely, Tf2 is closed and the transfer gate is opened.
5. The issue line, T1 and T4 are turned off, the capacitor C will maintain the voltage value on SL, and the skew inverter bank will read the XOR output. Fig. 11 shows the voltage state and output result on SL for each logic state.
For the a.b + C operation, as shown in fig. 12, 17:
1. the MUX1 is activated, TG1 and TG2 are closed, and the BLU is connected to a pre-charging circuit in the SA;
2. activating TG3 so that BLU is connected with the forwarding row unit, MUX2, MUX3 are in off state;
3. t1, T4, Tf2 are activated and the result is written back into Tf 1. At this time A, B, the two units are in series connection and connected to BLU in parallel with the forwarding line;
4. inputting a clock signalThe port, when the clock is low, the circuit is active and the voltage state on the BLU will be read by both inverters.
For (A + B). C operation. As shown in fig. 13 and 18:
1. the MUX1 is activated, the TG1 and the TG2 are closed, and the SL is connected to a pre-charging circuit in the SA;
2. activating the forwarding row port of the MUX2 to connect the BLD with the forwarding row unit, and enabling the TG3 and the MUX3 to be in a closed state;
3. t1, T4, Tf2 are activated and the result is written back into Tf 1. At this time A, B, the two units are in parallel connection and connected in series with the forwarding line to the BLD;
4. inputting a clock signalThe port, when the clock is low, the circuit is active and the voltage state on SL will be read by both inverters.
The invention can also be handled for three operand operations with any logical combination of AND, NAND, OR AND NOR. For example, for '(a NAND B) NOR C', which is equivalent to '(a AND B) AND NOT (C)', it can be implemented by a three-operand AND operation, where the forwarding line feeds NOT (C).
Claims (4)
1. A ferroelectric memory array capable of realizing multi-operand memory calculation is characterized by comprising a memory array, a sensing and multi-valued calculation unit, a sensing line driver, a forwarding row unit and an address decoder, wherein the sensing and multi-valued calculation unit is connected with the memory array, and the memory array is connected with the forwarding row unit; the address decoder is connected with the memory array and used for selecting rows or columns needing to be operated to carry out bitwise logic operation and obtaining an operation result in the sensing/multi-value calculation module; the sensing and multivalued computing unit is connected with the input end of the output buffer, the output end of the output buffer is connected with the first input end of the first data selector, the first input end of the second data selector and the input end of the input buffer, the I/O buffer is connected with the input end of the input buffer and the second input end of the first data selector, the output end of the first data selector is connected with the forwarding row unit, the output end of the input buffer is connected with the second input end of the second data selector, and the output end of the second data selector is connected with the memory array through the sensing line driver.
2. A ferroelectric memory array capable of performing multi-operand memory computations according to claim 1, wherein the sensing and multi-valued computation units comprise a precharge circuit, a current mirror unit and an inverter group.
3. The ferroelectric memory array capable of realizing multi-operand memory computation of claim 2, wherein the memory array comprises a third data selector, a fourth data selector, a fifth data selector, a first switch, a second switch, a third switch, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first ferroelectric field effect transistor and a second ferroelectric field effect transistor, a first input terminal of the third data selector is used as a first bit line terminal and connected to an output terminal of the fourth data selector, a first input terminal of the fourth data selector is a ground terminal, and a second input terminal of the fourth data selector is connected to the forwarding row unit; a second input end of the third data selector is used as a second bit line end and is connected with the forwarding line unit after passing through a third switch; the third input end of the third data selector is used as a sensing line end and connected with the output end of the fifth data selector, the first input end of the fifth data selector is connected with the switching and issuing unit, and the second input end of the fifth data selector is used as a ground end; the output end of the third data selector is connected with a pre-charging circuit of the sensing and multi-value computing unit, a current mirror unit of the sensing and multi-value computing unit is connected with a second bit line end after passing through the first switch, and an inverter group of the sensing and multi-value computing unit is connected with a sensing line end after passing through the second switch; the grid electrodes of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are all used as control ends, the drain electrode of the first MOS tube is connected with the second bit line end, the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube, the drain electrode of the second MOS tube and the drain electrode of the fourth MOS tube are both connected with the first bit line end, the source electrode of the fourth MOS tube is connected with the source electrode of the third MOS tube, the drain electrode of the third MOS tube is connected with the second bit line end, the grid electrode of the first ferroelectric field effect tube is used as a writing end, the drain electrode of the first ferroelectric field effect tube is connected with the source electrode of the first MOS tube, the source electrode of the first ferroelectric field effect tube is connected with a sensing line end, the grid electrode of the second ferroelectric field effect tube is used as a writing end, the drain electrode of the second ferroelectric field effect tube is connected with the source electrode of the third MOS tube, and the source electrode of the second ferroelectric field effect tube is connected with the sensing line end.
4. The ferroelectric memory array capable of realizing multi-operand memory calculation according to claim 3, wherein the issue unit comprises a fifth MOS transistor, a sixth MOS transistor and a TG gate, a gate of the fifth MOS transistor is used as a control terminal, a drain of the fifth MOS transistor is connected to the second input terminal of the fourth data selector, the third switch and the first input terminal of the fifth data selector, a source of the fifth MOS transistor is connected to VDD through the TG gate, a gate of the sixth MOS transistor is used as a control terminal, a drain of the sixth MOS transistor is connected to the source of the fifth MOS transistor, and a source of the sixth MOS transistor is grounded.
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