CN102866875A - Universal multi-operand summator - Google Patents
Universal multi-operand summator Download PDFInfo
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- CN102866875A CN102866875A CN2012103739088A CN201210373908A CN102866875A CN 102866875 A CN102866875 A CN 102866875A CN 2012103739088 A CN2012103739088 A CN 2012103739088A CN 201210373908 A CN201210373908 A CN 201210373908A CN 102866875 A CN102866875 A CN 102866875A
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Abstract
The invention discloses a universal multi-operand summator which can be used for achieving synchronous parallel adding of multiple multi-digit binary numbers in the digital arithmetical computation field. The universal multi-operand summator comprises a module 110, a module 120 and a module 130, and the module 110 uses a switching circuit for achieving parallel adding of multiple single-digit binary numbers from structural aspect. Adding of two single-digit numbers and single-digit carry numbers is also achieved by the module 120 through the switching circuit. The module 130 is composed of the module 110, the module 120 and the like, and carry computation and transmission exceeding the operand digital number is completed. Synchronous parallel computation of operand values corresponding to all digit rights is carried out by using the module 110, then according to digit right correspondence, addition numbers are regrouped based on a computation result, the module 110 is used again until that each digit right only has two addition numbers after regrouping, carry generation and transmission are achieved through the module 130, and a final addition sum is acquired by the module 120. The universal multi-operand summator is simple in circuit structure and neat in design, and a large amount of time and hardware cost can be reduced.
Description
Technical field
The invention belongs to electronic technology field and field of computer architecture, be to realize all the bit parallel additions of a plurality of operands, and produce synchronously the adding circuit of each weights position carry and final sum, can be widely used in the arithmetic unit of all kinds of microprocessors, digital signal processor and some special-purposes.
Background technology
Totalizer both can realize that additive operation also can realize subtraction, become the basic building block of multiplier and divider as basic arithmetic operation unit, cost, arithmetic speed and the operational precision etc. of the computing circuits such as multiplier and divider directly affected and determined, and then performance and the cost of the large-scale dedicated system such as all kinds of microprocessors and digital signal processor determined.
In the past few decades, totalizer obtains scholar, scientific research personnel's enough attention and further investigation, also is applied widely.In totalizer family, 2 operand binary adders especially seem important, a large amount of relevant achievements in research occurred.These achievements mainly can be summarized as chain carry totalizer (Ripple-Carry Adder), carry-skip adder (Carry-Skip Adder), carry lookahead adder (Carry-Look-Ahead Adder), conditional-sum adder (Conditional-Sum Adder), carry-select adder (Carry-Select Adder) and carry save adder (Carry-Save Adder) according to project organization, and through various totalizer variants that the improvement of top various totalizers is proposed etc.Moreover, adopt in addition the totalizer of Manchester carry chain, adopt the totalizer of self synchronization circuit, adopt the totalizer of differential cascade switching voltage logic, and adopt totalizer of selecting circuit etc.As: in Chinese invention patent No. 200610127132.6 (publication number CN101140511A), disclosed a kind of " cascaded carry binary adder ".This invention is based on the adding circuit of Ripple structure, revised the carry generating circuit in the carry transmission circuit, and according to odd number and even number data are divided into different units, in order to reduce the time spent that gate circuit progression too much increases with different carry generating circuits.In Chinese invention patent No. 02140712.6 (publication number CN101432907), disclosed a kind of " XOR carry generator and use its condition-selecting adder and method ".This invention is that a kind of condition is selected binary adder, realizes carry select and adds and select by segmentation and selector switch.But aspect carry select, use the low level carry to cause the time spent to increase as alternative condition because existing.In Chinese invention patent No. 200310101005.5 (publication number CN1497428), disclosed a kind of " binary adder circuit and produce the method for use therein carry logic circuits ".This invention generate synchronously the different pieces of information section respectively take 1 and 0 for the low level carry add and, and produce the carry value of each data segment by the carry generating portion, selection finally adds and the result.This invention has reduced the critical path that carry produces, and shortened time-delay, but circuit is still very complicated.In Chinese invention patent 200410064426.X number (publication number CN1614553A), disclosed a kind of " carry save adder and system thereof ".This invention comprises the logical block that is coupled to the high-order full adder, by generate carry in prime rather than previous stage, has reduced the delay of the input position that is input to the high-order full adder, thereby reduces the delay of high-order full adder output summation and carry.This invention exists hardware spending large equally, and time delay is many.
Also current totalizer achievement in research can be divided into numerical value totalizer and symbolic number totalizer according to the numerical value expression form.The structural type totalizer of introducing previously mainly belongs to the numerical value totalizer, and for the symbolic number totalizer, mainly contains redundant symbol and count addition electrical equipment and hybrid digital totalizer etc.They still postpone excessive, and hardware spending is higher.
When people can't find breakthrough from theoretical analysis, computational algorithm and project organization, some researchists also attempted from design technology, wish to find new discovery.So employing ECL technique in succession occurred, static CMOS technique, the totalizer that dynamic CMOS technique and BiCMOS technique etc. are made etc., yet effect and not obvious.
Even to this day, deliver with the paper form and the problems such as the too much hardware spending of fine solution and carry time-delay of all failing with the totalizer of patent form application, cause the totalizer that surpasses 64 losing practical value aspect hardware spending and the time-delay.The present invention also proposes a kind of 2 operand binary adders.This totalizer hardware spending is little, is directly proportional with the addition number figure place; This totalizer is few computing time, only needs the time spent of 3 gate circuits, and is irrelevant with the addition number figure place, is easily extended to 128,256 even higher.Thereby say, the invention solves the problems such as too much hardware spending that current 2 operand binary adders run into and carry time-delay.
For a plurality of operand additions, the main or traditional in twos successively addition of a plurality of numbers of the current scheme of generally using.Although this hardware spending is little, operation time is short,, in case addition number quantity is more, it amounts to the time spent will be very large.For example: even use 2 number parallel synchronous totalizers proposed by the invention cumulative to 256 operands, its total time spent also needs (256-1) * 3=765 gate circuit time spent.As seen, a plurality of numbers in twos successively addition scheme be not ideal selection for more operand addition.
In existing a plurality of operand addition documents, also has the scheme that adopts first compression, rear use 2 number parallel synchronous additions.This scheme not only causes time spent and hardware spending larger because each adopts stage compression device, and on final sum is calculated also because using 2 number parallel synchronous addition Shortcomings.In addition, need partial product is added up in the mlultiplying circuit implementation procedure, this also becomes a kind of approach of separating current a plurality of operand addition development situations.In mlultiplying circuit, the cumulative scheme of partial product mainly is repeat array (Iterative Array is called for short IA), Wallace tree construction and Booth Encoding structure, and their mutation etc.Although IA structure compound with regular structure is easy to layout design, speed is the slowest.The Wallace tree construction mainly is to adopt carry save adder (CSA) computing method and Wallace tree structural texture, compares with the IA structure and has reduced the compression number of plies.Such scheme is counted the multiplication realization because be unsuitable for high bit along with the operand figure place increase meeting exponent increase hardware spending exclusive disjunction time spent.Booth Encoding structure mainly be adopt coding the synchronous calculating section of mode and, but can not accomplish the addition of running simultaneously of all operations number, or need repeatedly loop computation, too much increased operation time.
By upper surface analysis as seen, current multioperand adder also needs further further investigation, needs to form simple and practical design proposal.The present invention not only proposes a plurality of one digit number adding circuits and 2 operand parallel synchronous addition devices, has also proposed general multioperand adder.These inventions have not only solved the parallel synchronous operational problem, reduce hardware spending, reduce and calculate the time spent, also so that circuit structure is regular, are easy to realize etc.
Summary of the invention
The invention discloses a kind of general multioperand adder, is to solve a plurality of multidigit binary numbers cumulative scheme of running simultaneously, and mainly comprises the adder circuit of running simultaneously of the identical weights bit value of multioperand adder circuit, carry synthetic circuit and 2 operands.Wherein, the identical weights bit value of multioperand adder circuit is the totalizer that realizes a plurality of one digit number additions.It at first adopts switch matrix to add up the number of high level in a plurality of one digit numbers (such as " 1 ") or low level (such as " 0 "), and then uses on-off circuit to obtain to add and the result.Whole process only needs the time of 2 basic gate circuits.The adder circuit of running simultaneously of 2 operands is a kind of 2 operand adder, each bit value in 2 operands of addition that can walk abreast, synchronization gain everybody with its all whole issuable carry value of low levels, and finally added simultaneously and circuit.It at first by on-off circuit obtain everybody 2 addition numbers and, and by on-off circuit and the synchronization gain of the carry transmission channel possible carry numerical value to a high position, at last by on-off circuit to everybody 2 number addition one's own department or units and and carry out addition from possible the carry value of low level, obtain simultaneously each finally add with.Whole additive process only needs the time of 3 basic gate circuits.The carry synthetic circuit mainly is comprised of multioperand identical weights bit value adder circuit and the 2 operands adder circuit of running simultaneously, and is used for finishing generation, transmission and addition above all carries of operand figure place, can't introduce extra operation time.
The identical weights bit value of multioperand adder circuit is comprised of statistical circuit and coding circuit.Statistical circuit is added up the numbers of " 0 " and " 1 " in a plurality of input data, coding circuit then can to shape as continuously " 0 " and continuously the statistics of " 1 " composition encode, acquisition one's own department or unit and with high-order carry.
2 operands are run simultaneously adder circuit by statistical coding module, carry generation transport module and are added and select module to form.The statistical coding module is added up high-low level in two numbers of addition and is encoded, obtain one's own department or unit and with accurate carry, and provide addition two number and entirely be not the signal wire of " 0 "; Carry generates transport module and processes accurate carry and low level carry, produces carry when realizing accurate carry for " 1 ", determines whether to transmit carry from low level according to signal wire during for " 0 "; Add and select module to determine final sum by one's own department or unit with the low level carry select.
The carry synthetic circuit has realized surpassing the carry value calculating of operand figure place, the perfect operation independent function of multioperand adder, can adopt flexibly the identical weights bit value of different multioperands adder circuit, the 2 operands adder circuit of running simultaneously in expense situation extra time not introducing, and add and select the circuit such as module.
When for the parallel synchronous addition of n m positional operand, wherein n and m are not less than 1 natural number, totalizer of the present invention is at first carried out parallel addition to the adder circuit of the corresponding value of each power by the identical weights bit value of n operand of n m positional operand, obtain each power and position n numerical value addition and reach
The position carry value, then to all result of calculations of m position according to recombinate each addition number of position power corresponding relation.This moment, addition number had
+ 1.Then, this general totalizer is used
The adder circuit of the identical weights bit value of+1 operand is to this
+ 1 addend walks abreast cumulative again, and to accumulation result again according to recombinate each addition number of position power corresponding relation, so until after the restructuring each power only have 2 operand additions.Simultaneously, for the carry that surpasses the m position, the quantity according to identical bits power addition number after restructuring adopts corresponding a plurality of one digit number adding circuits to reduce addition number.At last, the present invention finishes 2 last operand additions by the adder circuit of running simultaneously of 2 operands, obtain n m positional operand finally cumulative and.
N m positional operand carried out in the parallel synchronous sum operation, repeatedly using a plurality of one digit number totalizers, and operation result is newly being made up according to the position weight, in order to gradually reduce addition number quantity.In addition, the identical weights bit value of multioperand adder circuit is not the totalizer of a fixing operation number, but the general designation of the one column adder that is not less than 2 operands that a class is comprised of statistical circuit and coding circuit.
This general multioperand adder not only is used for a plurality of operand additions, can also be applied in a variety of computing circuits such as complement code addition, subtraction and multiplication.
Based on foregoing invention description of contents and the specific embodiment that provides of accompanying drawing subsequently, compared with prior art, the present invention is owing to adopt Regular Circuit, utilize on-off element, by the interpretative version of running simultaneously, thereby solved a plurality of multi-position action numbers and be difficult to the cumulative problem of running simultaneously, hardware spending and time spent expense have not only been reduced, also increased the extensibility of circuit, cumulative such as 64 64 figure places, both having can be implemented in only increases hardware spending and does not increase that to expand to 65 to 127 64 figure places in the situation of time spent cumulative, also can not increase only increasing hardware spending the cumulative of 64 numbers that realize surpassing 64 in the time spent situation.
By read content of the present invention, in conjunction with innovation pointed in following the description of the drawings and the claims etc., the those skilled in the art can have clearer understanding and understanding to the above-mentioned content relevant with other and target of the present invention, may exist some advantages of the present invention and new application not to provide at this, but still wish to be included in the limited range of the claims of enclosing.
For complete understanding at technology contents of the present invention, be described in further detail below in conjunction with accompanying drawing.
Description of drawings
Fig. 1 is functional-block diagram of the present invention;
Fig. 2 is the identical weights bit value of a plurality of operand of the present invention adder circuit synoptic diagram;
Fig. 3 is the synoptic diagram of selector switch among the present invention;
Fig. 4 is the synoptic diagram of tandem tap among the present invention;
Fig. 5 is the synoptic diagram of two 1 bit adding circuits of the present invention;
Fig. 6 is the run simultaneously synoptic diagram of adding circuit of two multidigit binary numbers of the present invention;
Fig. 7 is a plurality of multi-position action numbers totalizer synoptic diagram of running simultaneously.
Embodiment
Hereinafter, with reference to accompanying drawing the preferred embodiments of the present invention are described in detail.Note that hereinafter described is representative embodiment of the present invention, and should not be limited to following description when of the present invention understanding.
Fig. 1 is functional-block diagram of the present invention.It mainly is comprised of adder Module 120 and the comprehensive module 130 of carry of the adder Module 110 of a plurality of bits, 2 bits.This invention is at first weighed corresponding all operations numerical value to each and is adopted module 110 calculating of running simultaneously, then to all result of calculation according to position power corresponding relation every addition number of recombinating, and reuse module 110, so until rear each power of restructuring only has 2 addition numbers.Simultaneously, realize that by module 130 carry that is higher than the operand figure place processes and transmission, and binding modules 120 processes 2 last operand additions, run simultaneously obtain finally to add and.
Adding up problem when module 110 adopts on-off circuits to solve an a plurality of bit from structure aspects has replaced traditional interpretative version that is made of gate circuit, and its time spent only needs the time spent of 2 gate circuits, and is irrelevant with the addition number number; Its hardware spending also only square is directly proportional with the addition number number, has avoided the higher-index relation.
Fig. 2 is the identical weights bit value of a plurality of operand of the present invention adder circuit specific embodiment, and namely module 110 is directed to the cumulative specific embodiment of 8 one digit numbers.Will note when Understanding Module 110: module 110 is cumulative simultaneously about a plurality of one digit numbers, and it is cumulative not only to represent 8 one digit numbers, and it is cumulative also to represent 2 above one digit numbers.Fig. 2 just adds up 8 one digit numbers and comes the principle of work of specification module 110 as specific embodiment, and not talkative module 110 is exactly the totalizer of 8 one digit numbers, and perhaps the totalizer of 8 one digit numbers is exactly module 110.
As can be seen from Figure 2, these 8 one digit number summation circuits have 8 input end ai_0～ai_7, and 4 output terminal yi_0～yi_3 are divided into module 111 and 112.Module 111 is statistical circuits, is used for the number of statistics summarized information " 0 " and " 1 ".In module 111, when the ai_0 input low level, all selector switch si_00～si_07 selects left side port, and this moment, si_07 selected directly to connect low level, the si_07 output low level, and showing has a low level input among ai_0～ai_7.When the ai_0 input high level, all selector switch si_00～si_07 selects the right port, and this moment, si_00 selected directly to connect high level, and si_00 exports high level, and showing has a high level input among ai_0～ai_7.Be added to simultaneously port ai_0～ai_7 such as one group of input data { 01010101 }, then selector switch si_00～si_07 selects left side port, guarantee that si_07 receives low level, selector switch si_10～si_16 selects the right port, guarantees that si_00 receives high level by si_10.The like, last si_03～si_07 output low level, si_00～si_03 exports high level, has 4 contiguous port output high level, and is corresponding with the input data.Equally, be added to simultaneously port ai_0～ai_7 such as one group of input data { 11010111 }, then si_06 and si_07 output low level, si_00～si_05 export high level, has 6 contiguous ports and exports high level.Obviously, in the input data what " 1 " are arranged, from si_00 to si_07, just have what continuous switches to be simultaneously high level.Si_00 is that low level illustrates that then the input data are low level entirely, and si_07 is that high level illustrates that then the input data are high level entirely.
Be coding circuit in the module 112, can use on-off circuit to encode according to the output level of si_00～si_07.As: guarantee that lowest order yi_0 is " 1 ", must satisfy si_00 and si_01 or si_02 and si_03 or si_04 and si_05 or si_06 and si_07 for " 1 " and " 0 ", odd number " 1 " is namely arranged among si_00～si_07.The tandem tap circuit that the present invention proposes can be realized this function.The switch of " K-" expression Low level effective among the figure, the effective switch of " K+ " expression high level.When si_00 and si_01 or si_02 and si_03 or si_04 and si_05 or si_06 and si_07 are " 1 " and " 0 ", switch conduction, yi_0 directly receives positive source, guarantee to be " 1 ", and it is a pair of when " 1 " and " 0 " when not having in them, switch by, yi_0 is defined as low level " 0 " by pull down resistor.Yi_1 also adopts on-off circuit to realize according to logical relation as yi_0 with yi_2, only has yi_3 directly to adopt si_07 output.This is because only when addition number is 8 " 1 ", and corresponding output encoder is " 1000 ", and it is high level that si_07 exports; For other situation, si_07 output is low level, and yi_3 also is low level.
In Fig. 2, adopted on-off circuit, forming the selection circuit of switch matrix and the tandem tap in the module 112 can make with different materials, requires and applied environment as long as satisfy switch designs, such as atom switch, quantum switch, photon switch, transistor switch and electric switch etc.Fig. 3 and Fig. 4 are respectively specific embodiments selecting circuit and tandem tap, and they have adopted the metal-oxide-semiconductor design, but this does not represent the present invention and only uses this type of switch.As long as can implement inventive concept, no matter use which kind of fret switch all to belong to category of the present invention.The switch that the present invention uses should have following features: in case switch conduction, signal can transmit at a terrific speed, and such as the metal-oxide-semiconductor switch, conducting resistance is infinitely small, and conduction path is as metallic conductor; In case switch disconnects, signal transmission be difficult to by, such as the metal-oxide-semiconductor switch, off resistance is infinitely great, electric current is very little.
In Fig. 3, Q
1And Q
22 metal-oxide-semiconductors for symmetry.When control end ai is low level, Q
2Conducting, port 3 with is connected connection; When control end ai is high level, Q
1Conducting, port 2 with is connected connection.
In Fig. 4, Q
3And Q
42 metal-oxide-semiconductors for symmetry.When control end 1 is low level, Q
4Conducting; When control end 2 is high level, Q
3Conducting.
Here supplementary notes, current semiconductor technology can have been produced between the drain-source utmost point conducting resistance much smaller than the metal-oxide-semiconductor of 1 Ω, between the drain-source utmost point as good conductor.When the metal-oxide-semiconductor grid level changed, grid needed just can reach stable level certain Time Created, and then conducting between the drain-source utmost point is equivalent to conductor path.
Among Fig. 5, be the embodiment of the adding circuit of two 1 bit band carries, generate transport module 122 and add and select module 123 to form by statistical coding module 121, carry.Statistical coding module 121 is at first added up the level among addend ai and the bi by selector switch.Be low level then illustrate to only have a high level in the addend if the output of Si_00 is the output of high level Si_01; If the output of Si_01 and Si_00 all is high level then shows addend and summand all is high level.Like this, the output of Si_00, namely mi is low level, illustrates that then addition two numbers all are low levels; The output of Si_01, namely zi_1 is that high level shows that then addition two numbers all are high level.Then, module 121 by K switch-and K+ encode, obtain one's own department or unit and the zi_0 of two number additions, namely in the middle of and.The carry of two number additions is defined the carry that is as the criterion, and can directly use the output of selector switch Si_01, i.e. zi_1.Can find out that module 121 needs the time of 2 gate circuits namely can finish coding.
2 multidigit addition of binary number implement body embodiment based on module 120 see Fig. 6, and this is aimed at the adder circuit of 2 64 bits.In time spent, 2 addition numbers of all are added to the input end of circuit at the 1st gate circuit, and the output terminal of selection matrix is exported statistics in respective modules 121; At the 2nd gate circuit in the time spent, be that the module 122 of each correspondence produces may carries and to high position transmission on the one hand, be that coding circuit produces coding result in the module 121 on the other hand, i.e. the centre of addition 2 numbers and; At the 3rd gate circuit in the time spent, middle and jointly finally add and the result by selecting circuit to obtain with the low level carry.
For example: two addition numbers are respectively 64 continuous " 1 " and " 0 ", and carry value Cin is " 1 ", the 1st gate circuit after the time spent zi_1 be " 0 ", mi is " 1 ", here i ∈ [0,63]; After time spent, zi_0 is " 1 " at the 2nd gate circuit, simultaneously because zi_1 is " 0 ", mi is " 1 ", simultaneously conductings of all switches on causing from Cin to the Cout path, " 1 " of Cin end are along path to the most significant digit fast transport, and to make every carry all be " 1 "; At the 3rd gate circuit after the time spent, because zi_0 and low level carry value all be " 1 ", thereby output Si is restricted to " 0 " by pull down resistor, and while most significant digit carry value is " 1 ".Like this, result of calculation is exactly 1 " 1 " and 64 continuous " 0 ".
Fig. 6 only is an embodiment, for other not two number additions of isotopic number, only needs increase and decrease module 120 to get final product, and its operation use time also only needs 3 gate circuit times spent, and is irrelevant with the figure place of addition two numbers.
Fig. 7 is the run simultaneously specific embodiment of totalizer of n of the present invention m positional operand.This embodiment selects the addition of running simultaneously of 8 16 bits, has both provided extended mode, has provided again independent addition calculation scheme.This embodiment comprises four working linings, and ground floor is made of 16 modules 110.This module is mainly finished the coding of each 8 addition number, obtains corresponding one's own department or unit and Yi_0 and to 3 carry value Yi_3, Yi_2 and the Yi_1 of high-order carry.The second layer is by 18 module compositions, and they are respectively the module 121 of most significant digit, inferior high-order module 110 and remaining 16 equal modules 110.Low 16 modules 110 and not only structurally to some extent difference of ground floor module 110, also different on function, mainly finish the coding of each 4 addition number, obtain corresponding one's own department or unit and Xi_0 and to 2 carry value Xi_2 and the Xi_1 of high-order carry.The 17th module 110 is also different with low 16 modules 110, mainly finishes the coding of the 17th 3 addition numbers, obtains corresponding one's own department or unit and X16_0 and carry value X16_1.The module 121 of most significant digit is mainly finished the coding of the 18th 2 addition numbers, obtains corresponding one's own department or unit and X17_0 and carry value X17_1.The input number of the second layer, namely every addition number is not only arranged the array one-tenth that obtains by the Output rusults of ground floor according to identical power and position, also has carry digit Y-3_3, the Y-2_3, Y-2_2, Y-1_3, Y-1_2 and the Y-1_1 that are introduced according to expanded function by low level to form.In addition, in order to finish expanded function, 6 output Y13_3, Y14_3, Y14_2, Y15_3, Y15_2 and Y15_1 of ground floor are drawn.
The 3rd layer by 19 module compositions, and they are respectively the identical low level modules 110 with 18 of module 121 of most significant digit.Low 18 modules 110 mainly are to finish the coding of every 3 addition numbers, obtain corresponding one's own department or unit and Ri_0 and carry value Ri_1.The module 121 of most significant digit is mainly finished the coding of the 19th 2 addition numbers, obtains corresponding one's own department or unit and R18_0 and carry value R18_1.The 3rd layer input number, namely every addition number is not only arranged the array one-tenth that obtains by the Output rusults of the second layer according to identical power and position, also has carry digit X-2_2, the X-1_2 and the X-1_1 that are introduced according to expanded function by low level to form.In addition, in order to finish expanded function, 3 output X14_2, X15_2 and the X15_1 of the second layer are drawn.
The 4th layer by 20 module compositions, and they are respectively the identical low level modules 120 with 19 of module 123 of most significant digit.19 low level modules 120 mainly are to finish the addition of every 2 addition numbers and carry value, in order to obtain final sum.The module 123 of most significant digit is used for finishing the addition of time high-order carry value and the 3rd layer of most significant digit carry value.Here why adopt module 123, rather than module 120 or module 110 etc., reason is that the net result of 8 16 figure place additions can not surpass 20, that is to say, addend of the 20th and the carry value addition of low level can not produce carry.The 4th layer input number, namely every addition number is not only arranged the array one-tenth that obtains by the 3rd layer Output rusults according to identical power and position, also has the carry digit R-1_1 that is introduced according to expanded function by low level to form.In addition, in order to finish expanded function, 1 output R15_1 of the 3rd layer is drawn.
For the 4th layer, in order to finish expanded function, increased carry input Cin at lowest order, increased carry output terminal Cout at the 16th.
The present invention considers independent addition calculation demand, namely the totalizer of these 8 16 bits belongs to the most significant digit summation module, its every one deck produces is higher than the 16th carry does not need directly to send, but directly process and export in this inside modules, this treatment circuit is exactly the comprehensive module 130 of carry.Module 130 is comprised of a plurality of modules 110,120,121 and 123 etc., is not increasing each layer carry data addition calculation of finishing in the extra time spent situation more than the 16th.
Fig. 7 shows, needs 2 gate circuit times spent from each working linings of three layers of ground floors to the, and only 3 gate circuit times spent of the 4th layer of needs, as seen, only 9 gate circuit times spent can be finished 8 16 figure place additions.Can release from the present invention, the summarized information figure place in the limited range does not affect the time spent of adding circuit.The circuit time spent of the present invention is only relevant with addition operand number, needs 7 gate circuit times spent such as 4～7 operands, and 8～255 operands need 9 gate circuit times spent, and 256 above operands also only need 11 above gate circuit times spent.Hardware spending of the present invention both was directly proportional with the operand figure place when not considering the comprehensive module 130 of carry, also square was directly proportional with the operand number.
8 16 bits adder circuits of running simultaneously although Fig. 7 provides,, it only is a run simultaneously specific embodiment of totalizer of a plurality of multi-position action number of the present invention.The present invention is not limited in the addition of running simultaneously of 8 16 bits, for the addition of running simultaneously of any n m bit, can adopt flesh and blood of the present invention.
Although the present invention describes a plurality of multi-position action numbers addition implementation of running simultaneously, but it also is applicable in a variety of computing circuits such as complement code addition, subtraction and multiplication, just can realize the function that a lot of the present invention had not mentioned as long as module that the present invention carries is carried out reasonable combination with revising.
Although introduced the present invention by describing specific embodiment of the present invention, should be understood that the people who is proficient in this area still can carry out various modifications on pro forma and the details to the present invention, and does not break away from the spirit and scope of the present invention.
Claims (9)
1. general multioperand adder, it is characterized in that, described totalizer mainly comprises the identical weights bit value of multioperand adder circuit, carry synthetic circuit and the 2 operands adder circuit of running simultaneously, the identical weights bit value of multioperand adder circuit is the totalizer that realizes a plurality of one digit number additions, it at first adopts switch matrix to add up the number of high level " 1 " in a plurality of addition one digit numbers or low level " 0 ", and then use on-off circuit to obtain to add and the result, whole process only needs the time of 2 basic gate circuits, the 2 operands adder circuit of running simultaneously is a kind of 2 operand adder, each bit value in 2 operands of addition can walk abreast, the whole issuable carry value of synchronization gain everybody and all low levels thereof, and finally added simultaneously and circuit, it at first by on-off circuit obtain everybody 2 addition numbers and, and by on-off circuit and the synchronization gain of the carry transmission channel possible carry numerical value to a high position, by on-off circuit everybody 2 number addition one's own department or units are carried out addition with reaching from the possible carry value of low level at last, obtain simultaneously each finally add and, whole additive process only needs the time of 3 basic gate circuits, the carry synthetic circuit mainly is comprised of multioperand identical weights bit value adder circuit and the 2 operands adder circuit of running simultaneously, be used for finishing the generation above all carries of operand figure place, transmission and addition can't be introduced extra operation time.
2. general multioperand adder according to claim 1, it is characterized in that: the identical weights bit value of described multioperand adder circuit is comprised of statistical circuit and coding circuit, statistical circuit is added up the number of " 0 " and " 1 " in a plurality of input data, coding circuit then can to shape as continuously " 0 " and continuously " 1 " statistics of forming encode, acquisition one's own department or unit and with high-order carry.
3. general multioperand adder according to claim 1, it is characterized in that: described 2 operands are run simultaneously adder circuit by statistical coding module, carry generation transport module and are added and select module to form, the statistical coding module is added up high-low level in two numbers of addition and is encoded, obtain one's own department or unit and with accurate carry, and provide addition two number and entirely be not the signal wire of " 0 "; Carry generates transport module and processes accurate carry and low level carry, produces carry when realizing accurate carry for " 1 ", determines whether to transmit carry from low level according to signal wire during for " 0 "; Add and select module to determine final sum by one's own department or unit with the low level carry select.
4. general multioperand adder according to claim 1, it is characterized in that: described carry synthetic circuit has realized surpassing the carry value calculating of operand figure place, the perfect operation independent function of multioperand adder, can adopt flexibly the identical weights bit value of different multioperands adder circuit, the 2 operands adder circuit of running simultaneously in expense situation extra time not introducing, and add and select the circuit such as module.
5. general multioperand adder according to claim 1 is characterized in that having adopted on-off circuit, as long as satisfy the switch that switch designs requires and applied environment just can select different materials to make.
6. general multioperand adder, it is characterized in that, when n m positional operand carried out the parallel synchronous addition, wherein n and m are not less than 1 natural number, general multioperand adder is at first carried out parallel addition to corresponding value of each position power of n m positional operand by the identical weights bit value of n operand adder circuit, obtain each power n numerical value addition and reach
The position carry value, then to all result of calculations of m position according to recombinate each addition number of position power corresponding relation, this moment, addition number had
+ 1, then, this general totalizer is used
The identical weights bit value of+1 operand adder circuit is to this
+ 1 addend walks abreast cumulative again, and to accumulation result again according to recombinate each addition number of position power corresponding relation, so until rear each power of restructuring only has 2 operand additions, simultaneously, for the carry that surpasses the m position, quantity according to identical bits power addition number after restructuring adopts corresponding a plurality of one digit number totalizers to reduce addition number, at last, this general totalizer is finished 2 last operand additions by the adder circuit of running simultaneously of 2 operands, obtain n m positional operand finally cumulative and.
7. general multioperand adder according to claim 6 is characterized in that repeatedly using a plurality of one digit number totalizers, and operation result is newly made up according to the position weight, in order to gradually reduce addition number quantity.
8. general multioperand adder according to claim 6, it is characterized in that the identical weights bit value of multioperand adder circuit is not the totalizer of a fixing operation number, but the general designation of the one column adder that is not less than 2 operands that a class is comprised of statistical circuit and coding circuit.
9. a general multioperand adder is characterized in that, this general multioperand adder not only is used for a plurality of operand additions, can also be applied in a variety of computing circuits such as complement code addition, subtraction and multiplication.
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| CN111694541A (en) * | 2020-05-06 | 2020-09-22 | 常熟理工学院 | Base 32 arithmetic circuit for number theory conversion multiplication |
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| CN113268219A (en) * | 2021-07-19 | 2021-08-17 | 中科南京智能技术研究院 | Adder circuit with binary complement conversion |
| CN113419704A (en) * | 2021-07-23 | 2021-09-21 | 北京源启先进微电子有限公司 | 49-bit adder, implementation method thereof, arithmetic circuit and chip |
| CN113658623A (en) * | 2021-08-20 | 2021-11-16 | 湘潭大学 | Ferroelectric memory array capable of realizing multi-operand memory calculation |
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| CN116149599A (en) * | 2023-03-30 | 2023-05-23 | 杭州雄迈集成电路技术股份有限公司 | Step-by-step carry processing method, system and adder |
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