CN113658623B - Ferroelectric memory array capable of realizing multi-operand memory calculation - Google Patents
Ferroelectric memory array capable of realizing multi-operand memory calculation Download PDFInfo
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Abstract
The invention discloses a ferroelectric memory array capable of realizing multi-operand memory calculation, which comprises a sensing and multi-value calculation unit, a sensing line driver and an address decoder, wherein the sensing and multi-value calculation unit is connected with the memory array, and the memory array is connected with a forwarding line unit; the address decoder is connected with the memory array; the sensing and multi-value calculating unit is connected with the input end of the output buffer, the output end of the output buffer is connected with the first input end of the first data selector, the first input end of the second data selector and the input end of the input buffer, the output end of the first data selector is connected with the forwarding line unit, the output end of the input buffer is connected with the second input end of the second data selector, and the output end of the second data selector is connected with the memory array after passing through the sensing line driver. The invention is applicable to all resistor-based cell designs, which require only N/2 clock cycles for CiM operations with N operands.
Description
Technical Field
The invention relates to the field of circuits, in particular to a ferroelectric memory array capable of realizing multi-operand memory calculation.
Background
The current computational mechanism of the computational architecture only considers the case of computing two operands in one clock cycle. This also means that when a command needs to be executed on N rows, N-1 clock cycles are required to operate. In addition, existing integrated memory architecture implements bitwise logic operations by primarily sensing the resulting current/voltage of the bit lines and comparing it to a reference current/voltage. But multiple operands require more reference currents or voltages, which also incurs high design costs. Therefore, how to efficiently control the number of references when executing multiple operands is an unavoidable issue.
Disclosure of Invention
In order to solve the technical problems, the invention provides a ferroelectric memory array which has a simple structure and a wide application range and can realize multi-operand memory calculation.
The technical scheme for solving the problems is as follows: the ferroelectric memory array capable of realizing multi-operand memory calculation comprises a memory array, a sensing and multi-value calculation unit, a sensing line driver, a forwarding line unit and an address decoder, wherein the sensing and multi-value calculation unit is connected with the memory array, and the memory array is connected with the forwarding line unit; the address decoder is connected with the memory array and is used for selecting a row or a column needing to be operated to carry out bit-wise logic operation and obtaining an operation result in the sensing/multi-value calculation module; the sensing and multi-value calculating unit is connected with the input end of the output buffer, the output end of the output buffer is connected with the first input end of the first data selector, the first input end of the second data selector and the input end of the input buffer, the I/O buffer is connected with the input end of the input buffer and the second input end of the first data selector, the output end of the first data selector is connected with the forwarding line unit, the output end of the input buffer is connected with the second input end of the second data selector, and the output end of the second data selector is connected with the memory array after passing through the sensing line driver.
The sensing and multi-value calculating unit comprises a pre-charging circuit, a current mirror unit and an inverter group.
The ferroelectric memory array capable of realizing multi-operand memory computation comprises a third data selector, a fourth data selector, a fifth data selector, a first switch, a second switch, a third switch, a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a first ferroelectric field effect tube and a second ferroelectric field effect tube, wherein the first input end of the third data selector is used as a first bit line end and is connected with the output end of the fourth data selector, the first input end of the fourth data selector is a grounding end, and the second input end of the fourth data selector is connected with a forwarding line unit; the second input end of the third data selector is used as a second bit line end and is connected with the forwarding line unit after passing through a third switch; the third input end of the third data selector is used as a sensing line end and is connected with the output end of the fifth data selector, the first input end of the fifth data selector is connected with the forwarding line unit, and the second input end of the fifth data selector is a grounding end; the output end of the third data selector is connected with a pre-charging circuit of the sensing and multi-value calculating unit, the current mirror unit of the sensing and multi-value calculating unit is connected with the second bit line end after passing through the first switch, and the inverter group of the sensing and multi-value calculating unit is connected with the sensing line end after passing through the second switch; the grid electrodes of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are all used as control ends, the drain electrode of the first MOS tube is connected with the second bit line end, the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube, the drain electrode of the second MOS tube and the drain electrode of the fourth MOS tube are all connected with the first bit line end, the source electrode of the fourth MOS tube is connected with the source electrode of the third MOS tube, the drain electrode of the third MOS tube is connected with the second bit line end, the grid electrode of the first ferroelectric field effect tube is used as a writing end, the drain electrode of the first ferroelectric field effect tube is connected with the sensing line end, the grid electrode of the second ferroelectric field effect tube is used as a writing end, the drain electrode of the second ferroelectric field effect tube is connected with the source electrode of the third MOS tube, and the source electrode of the second ferroelectric field effect tube is connected with the sensing line end.
The ferroelectric memory array capable of realizing multi-operand memory computation, the forwarding unit comprises a fifth MOS tube, a sixth MOS tube and a TG gate, wherein the grid electrode of the fifth MOS tube is used as a control end, the drain electrode of the fifth MOS tube is connected with the second input end of the fourth data selector, the third switch and the first input end of the fifth data selector, the source electrode of the fifth MOS tube is connected with VDD after passing through the TG gate, the grid electrode of the sixth MOS tube is used as a control end, the drain electrode of the sixth MOS tube is connected with the source electrode of the fifth MOS tube, and the source electrode of the sixth MOS tube is grounded.
The invention has the beneficial effects that: under the condition that no extra reference current is introduced, each MOS tube in the unit is utilized to form a voltage divider, when the bit-wise logic operation is carried out, the logic values stored in the unit are different to influence the voltage change of the sensing line, and the memory calculation result can be output through the deflection inverter.
Drawings
Fig. 1 is a schematic diagram of the present invention.
Fig. 2 is a block diagram of a ferroelectric field effect transistor 3T-based cell according to the present invention.
Fig. 3 is a diagram of the SA architecture of the array provided by the present invention.
Fig. 4 is an equivalent circuit diagram of the present invention implementing OR operation.
Fig. 5 is an equivalent circuit diagram of the present invention for implementing AND operation.
Fig. 6 is an equivalent circuit diagram of the present invention implementing an XOR operation.
Fig. 7 is a block diagram of a forwarding row unit provided in the present invention.
FIG. 8 is an equivalent circuit diagram of the present invention implementing multi-operand A.B.C logic.
FIG. 9 is an equivalent circuit diagram of the present invention implementing multi-operand A+B+C logic.
FIG. 10 is an equivalent circuit diagram of an invention implementing multiple operand A # -B # -C logic.
FIG. 11 is a truth table for implementing multiple operand A #, B #, C logic in accordance with the present invention.
FIG. 12 is an equivalent circuit diagram of the present invention implementing multi-operand AB+C logic.
FIG. 13 is an equivalent circuit diagram of the present invention implementing multi-operand (A+B) C logic.
FIG. 14 is a waveform diagram of the present invention implementing multi-operand A.B.C logic.
FIG. 15 is a waveform diagram of an implementation of the multi-operand A+B+C logic of the present invention.
FIG. 16 is a waveform diagram of a logic implementing multiple operands A #, B #, C in accordance with the present invention.
FIG. 17 is a waveform diagram of an implementation of the multi-operand AB+C logic of the present invention.
FIG. 18 is a waveform diagram of an implementation of multi-operand (A+B) C logic in accordance with the present invention.
Detailed Description
The invention is further described below with reference to the drawings and examples.
As shown in fig. 1, 2 and 3, a ferroelectric memory array capable of implementing multi-operand memory computation includes a memory array, a sensing and multi-value computation unit, a sensing line driver, a forwarding line unit and an address decoder, wherein the sensing and multi-value computation unit is connected with the memory array, and the memory array is connected with the forwarding line unit; the address decoder is connected with the memory array and is used for selecting a row or a column needing to be operated to carry out bit-wise logic operation and obtaining an operation result in the sensing/multi-value calculation module; the sensing and multi-value calculating unit is connected with the input end of the output buffer, the output end of the output buffer is connected with the first input end of the first data selector, the first input end of the second data selector and the input end of the input buffer, the I/O buffer is connected with the input end of the input buffer and the second input end of the first data selector, the output end of the first data selector is connected with the forwarding line unit, the output end of the input buffer is connected with the second input end of the second data selector, and the output end of the second data selector is connected with the memory array after passing through the sensing line driver.
The sensing and multivalue calculation unit comprises a Pre-charging circuit Pre, a current Mirror unit Mirror and an inverter group Invs.
The memory array comprises a third data selector MUX1, a fourth data selector MUX2, a fifth data selector MUX3, a first switch TG1, a second switch TG2, a third switch TG3, a first MOS tube T1, a second MOS tube T2, a third MOS tube T3, a fourth MOS tube T4, a first ferroelectric field effect tube F1 and a second ferroelectric field effect tube F2, wherein the first input end of the third data selector MUX1 is used as a first bit line end and is connected with the output end of the fourth data selector MUX2, the first input end of the fourth data selector MUX2 is a grounding end, and the second input end of the fourth data selector MUX2 is connected with the forwarding line unit; the second input end of the third data selector MUX1 is used as a second bit line end and is connected with the forwarding line unit after passing through a third switch TG 3; the third input end of the third data selector MUX1 is used as a sensing line end and is connected with the output end of the fifth data selector MUX3, the first input end of the fifth data selector MUX3 is connected with the forwarding line unit, and the second input end of the fifth data selector MUX3 is a grounding end; the output end of the third data selector MUX1 is connected with a precharge circuit of a sensing and multi-value calculating unit, a current mirror unit of the sensing and multi-value calculating unit is connected with a second bit line end after passing through a first switch TG1, and an inverter group of the sensing and multi-value calculating unit is connected with a sensing line end after passing through a second switch TG 2; the grid electrodes of the first MOS tube T1, the second MOS tube T2, the third MOS tube T3 and the fourth MOS tube T4 are all used as control ends, the drain electrode of the first MOS tube T1 is connected with the second bit line end, the source electrode of the first MOS tube T1 is connected with the source electrode of the second MOS tube T2, the drain electrode of the second MOS tube T2 and the drain electrode of the fourth MOS tube T4 are both connected with the first bit line end, the source electrode of the fourth MOS tube T4 is connected with the source electrode of the third MOS tube T3, the drain electrode of the third MOS tube T3 is connected with the second bit line end, the grid electrode of the first ferroelectric field effect tube F1 is used as a writing end, the source electrode of the first ferroelectric field effect tube F1 is connected with the sensing end, the grid electrode of the second ferroelectric field effect tube F2 is used as a writing end, the drain electrode of the second ferroelectric field effect tube F2 is connected with the source electrode of the third MOS tube T3, and the source electrode of the second ferroelectric field effect tube F2 is connected with the sensing end.
As shown in fig. 7, the forwarding unit includes a fifth MOS transistor Tf1, a sixth MOS transistor Tf2, and a TG gate, the gate SA-WB of the fifth MOS transistor Tf1 is used as a control end, the drain of the fifth MOS transistor Tf1 is connected to MUX2/TG3/MUX3, the source of the fifth MOS transistor Tf1 is connected to VDD after passing through the TG gate, the gate Ctrl of the sixth MOS transistor Tf2 is used as a control end, the drain of the sixth MOS transistor Tf2 is connected to the source of the fifth MOS transistor Tf1, and the source of the sixth MOS transistor Tf2 is grounded.
Conventional memory calculation:
for the OR operation, as shown in fig. 4:
1. activating MUX1, closing TG1 and TG2, and connecting SL to pre-charge circuit in SA;
2. activating the ground port of MUX2 to make BLD grounded, TG3 and MUX3 are in closed state;
3. activating T2 and T4 can connect A, B two memory units in parallel in a circuit;
4. inputting clock signalsThe port, when the clock is low, the circuit is in operation and the voltage state on SL will be read by both inverters. The OR output is low only when both cells of A, B are in the high impedance state, otherwise high.
For an AND operation, as shown in fig. 5:
1. activating MUX1, closing TG1 and TG2, and enabling BLU to be connected into the pre-charging circuit in SA;
2. activating the ground port of MUX2 to make BLD grounded, TG3 and MUX3 are in closed state;
3. activating T1 and T4 can connect A, B two memory units in series in the circuit;
4. inputting clock signalsThe port, when the clock is low, the circuit is in operation and the voltage state on the BLU will be read by the two inverters. The AND output is high only when both cells A, B are in the low impedance state, AND low otherwise.
For XOR operations, as shown in fig. 6:
1. activating TG1 and TG2, closing MUX1, enabling BLU to connect to current mirror module, SL to connect to capacitor, skewed inverter group module;
2. during execution, capacitor C is precharged to 0.4V;
3. the precharge voltage is removed and enable ports EN, T1 and T4 are briefly opened, at which time current mirrors M1-T1-F2-T4 constitute a simple voltage divider. The logic states stored in the two ferroelectric field effect transistors will affect the magnitude of the voltage value on SL;
4. the capacitor C will maintain the voltage value on SL, turning off T1 and T4, and the set of skewed inverters will read the XOR output.
There are four cases of voltage values on SL in XOR operations: 1) When F1 and F2 are in the high resistance state, SL will remain at the 0.4V precharge voltage. 2) When F1 and F2 are in the low resistance state, SL is maintained around 0.4V due to the voltage divider structure. 3) When F1 is in a high resistance state and F2 is in a low resistance state, SL will discharge to a low level. 4) When F1 is in a low resistance state and F2 is in a high resistance state, SL will be charged to a high level.
When the SL upper voltage is far below 0.4V, the lower skewed inverter INVD group will output a high level, reading out the 01 result (case 3); when the SL upper voltage is much higher than 0.4V, the upper skewed inverter INVU group will output high, reading 10 results (case 4); when the SL up voltage is about 0.4V, both inverter groups output low (cases 1 and 2). The two skewed inverters are connected into the OR gate to read the XOR result.
For ADD operations:
the ADD operation is the same as the XOR operation, and the result may be output together with the XOR result.
1. Activating TG1 and TG2, closing MUX1, enabling BLU to connect to current mirror module, SL to connect to capacitor, skewed inverter group module;
2. during execution, capacitor C is precharged to 0.4V;
3. the precharge voltage is removed and enable ports EN, T1 and T4 are briefly opened and a clock signal is input to the Clk port, and the current mirror will mirror the current flowing through cell a to the sense current amplifier.
4. The sense current amplifier will sense the state stored by cell a when the clock signal of Clk is on the falling edge, with reference current Iref.
5. The following logic equations may be based for full adder operation:
(1)
(2)
adding the peripheral module as shown in fig. 6 outputs the ADD result.
Write-back based multi-operand memory computation:
when performing multi-operand memory computation, the previous data is input into the forwarding line through the output buffer. The transfer line is composed of two MOS transistors and a TG gate, and functions like a memory line, and the structure is shown in FIG. 4. The previous output is sent to SA-WB to control whether Tf1 is turned on or not, and is grounded or grounded to VDD by controlling the pass transistor Tf2 and the pass gate TG control unit.
For a.b.c. operation, as shown in fig. 8, 14:
1. activating MUX1, closing TG1 and TG2, and enabling BLU to be connected into the pre-charging circuit in SA;
2. activating a forwarding line port of the MUX2 to enable the BLD to be connected with the forwarding line unit, wherein TG3 and MUX3 are in a closed state;
3. t1, T4, tf2 are activated and the result is written back into Tf 1. At this time, the A, B forwarding row three units are connected in series in the circuit;
4. inputting clock signalsThe port, when the clock is low, the circuit is in operation and the voltage state on the BLU will be read by the two inverters. The AND output is high only when both cells A, B are in the low impedance state, AND low otherwise.
For the a+b+c operation. As shown in fig. 9 and 15:
1. activating MUX1, closing TG1 and TG2, and connecting SL to pre-charge circuit in SA;
2. activating the ground port of MUX2 to ground the BLD, activating MUX3 to connect the forwarding row unit to the SL;
3. t2, T4, tf2 are activated and the result is written back into Tf 1. At this time, the A, B forwarding row three units are connected in parallel in the circuit;
4. inputting clock signalsThe port, when the clock is low, the circuit is in operation and the voltage state on SL will be read by both inverters. Only when threeThe OR output is low when the cells are all at logic '0', otherwise high.
B C for A. As shown in fig. 10, 11, and 16:
1. activating TG1 and TG2, closing MUX1, enabling BLU to connect to current mirror module, SL to connect to capacitor, skewed inverter group module;
2. activating the ground port of MUX2 to ground the BLD, activating MUX3 to connect the forwarding row unit to the SL;
3. during execution, capacitor C is precharged to 0.4V;
4. the precharge voltage is removed, and enable ports EN, T1, and T4 are briefly opened and a clock signal is input to the Clk port, and the operation state of the transfer line is controlled by the result of the output unit a. When the unit A stores logic '1', tf2 is conducted, and the transmission gate is closed; conversely, tf2 is off and the transfer gate is on.
5. The switching lines T1 and T4 are disconnected, the capacitor C will maintain the voltage value on SL and the set of skewed inverters will read the XOR output. Fig. 11 shows the voltage state and output result at SL for each logic state.
For the a.b+c operation, as shown in fig. 12, 17:
1. activating MUX1, closing TG1 and TG2, and enabling BLU to be connected into the pre-charging circuit in SA;
2. activating TG3 to connect the BLU with the forwarding line unit, and enabling MUX2 and MUX3 to be in a closed state;
3. t1, T4, tf2 are activated and the result is written back into Tf 1. At this time, the A, B units are in a serial state and are connected with the BLU in parallel with the forwarding line;
4. inputting clock signalsThe port, when the clock is low, the circuit is in operation and the voltage state on the BLU will be read by the two inverters.
For (A+B). C operations. As shown in fig. 13 and 18:
1. activating MUX1, closing TG1 and TG2, and connecting SL to pre-charge circuit in SA;
2. activating a forwarding line port of the MUX2 to enable the BLD to be connected with the forwarding line unit, wherein TG3 and MUX3 are in a closed state;
3. t1, T4, tf2 are activated and the result is written back into Tf 1. At this time, the A, B two units are in parallel connection and connected in series with the forwarding line to be connected with the BLD;
4. inputting clock signalsThe port, when the clock is low, the circuit is in operation and the voltage state on SL will be read by both inverters.
The invention can also handle three operand operations with any combination of AND, NAND, OR and NOR logic. For example, for '(a NAND B) NOR C', it is equivalent to '(a AND B) AND NOT (C)', it can be implemented by a three-operand AND operation, where the forwarding row feeds in NOT (C).
Claims (2)
1. The ferroelectric memory array capable of realizing multi-operand memory calculation is characterized by comprising a memory array, a sensing and multi-value calculation unit, a sensing line driver, a forwarding line unit and an address decoder, wherein the sensing and multi-value calculation unit is connected with the memory array, and the memory array is connected with the forwarding line unit; the address decoder is connected with the memory array and is used for selecting a row or a column needing to be operated to carry out bit-wise logic operation and obtaining an operation result in the sensing/multi-value calculation module; the sensing and multi-value calculating unit is connected with the input end of the output buffer, the output end of the output buffer is connected with the first input end of the first data selector, the first input end of the second data selector and the input end of the input buffer, the I/O buffer is connected with the input end of the input buffer and the second input end of the first data selector, the output end of the first data selector is connected with the forwarding line unit, the output end of the input buffer is connected with the second input end of the second data selector, and the output end of the second data selector is connected with the memory array after passing through the sensing line driver;
the sensing and multivalue calculating unit comprises a pre-charging circuit, a current mirror unit and an inverter group;
the memory array comprises a third data selector, a fourth data selector, a fifth data selector, a first switch, a second switch, a third switch, a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a first ferroelectric field effect tube and a second ferroelectric field effect tube, wherein the first input end of the third data selector is used as a first bit line end and is connected with the output end of the fourth data selector, the first input end of the fourth data selector is a grounding end, and the second input end of the fourth data selector is connected with a forwarding line unit; the second input end of the third data selector is used as a second bit line end and is connected with the forwarding line unit after passing through a third switch; the third input end of the third data selector is used as a sensing line end and is connected with the output end of the fifth data selector, the first input end of the fifth data selector is connected with the forwarding line unit, and the second input end of the fifth data selector is a grounding end; the output end of the third data selector is connected with a pre-charging circuit of the sensing and multi-value calculating unit, the current mirror unit of the sensing and multi-value calculating unit is connected with the second bit line end after passing through the first switch, and the inverter group of the sensing and multi-value calculating unit is connected with the sensing line end after passing through the second switch; the grid electrodes of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are all used as control ends, the drain electrode of the first MOS tube is connected with the second bit line end, the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube, the drain electrode of the second MOS tube and the drain electrode of the fourth MOS tube are all connected with the first bit line end, the source electrode of the fourth MOS tube is connected with the source electrode of the third MOS tube, the drain electrode of the third MOS tube is connected with the second bit line end, the grid electrode of the first ferroelectric field effect tube is used as a writing end, the drain electrode of the first ferroelectric field effect tube is connected with the sensing line end, the grid electrode of the second ferroelectric field effect tube is used as a writing end, the drain electrode of the second ferroelectric field effect tube is connected with the source electrode of the third MOS tube, and the source electrode of the second ferroelectric field effect tube is connected with the sensing line end.
2. The ferroelectric memory array according to claim 1, wherein the forwarding unit includes a fifth MOS transistor, a sixth MOS transistor, and a TG gate, the gate of the fifth MOS transistor is used as a control terminal, the drain of the fifth MOS transistor is connected to the second input terminal of the fourth data selector, the third switch, and the first input terminal of the fifth data selector, the source of the fifth MOS transistor is connected to VDD after passing through the TG gate, the gate of the sixth MOS transistor is used as a control terminal, the drain of the sixth MOS transistor is connected to the source of the fifth MOS transistor, and the source of the sixth MOS transistor is grounded.
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