CN106611760B - The circuit arrangement method of compound semiconductor integrated circuit - Google Patents
The circuit arrangement method of compound semiconductor integrated circuit Download PDFInfo
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- CN106611760B CN106611760B CN201510695821.6A CN201510695821A CN106611760B CN 106611760 B CN106611760 B CN 106611760B CN 201510695821 A CN201510695821 A CN 201510695821A CN 106611760 B CN106611760 B CN 106611760B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 326
- 150000001875 compounds Chemical class 0.000 title claims abstract description 315
- 238000000034 method Methods 0.000 title claims abstract description 163
- 239000002184 metal Substances 0.000 claims abstract description 249
- 229910052751 metal Inorganic materials 0.000 claims abstract description 249
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 239000010410 layer Substances 0.000 claims description 398
- 239000002674 ointment Substances 0.000 claims description 54
- 239000003989 dielectric material Substances 0.000 claims description 51
- 239000000463 material Substances 0.000 claims description 33
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 28
- 230000015572 biosynthetic process Effects 0.000 claims description 24
- 230000003321 amplification Effects 0.000 claims description 23
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 23
- 239000011241 protective layer Substances 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229920002577 polybenzoxazole Polymers 0.000 claims description 17
- 230000005669 field effect Effects 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 11
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 9
- 239000004744 fabric Substances 0.000 claims description 9
- 238000010521 absorption reaction Methods 0.000 claims description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims 6
- 239000013078 crystal Substances 0.000 claims 2
- 229910052738 indium Inorganic materials 0.000 claims 2
- 238000000926 separation method Methods 0.000 description 24
- 239000004642 Polyimide Substances 0.000 description 13
- 229920001721 polyimide Polymers 0.000 description 13
- 230000018109 developmental process Effects 0.000 description 12
- 230000005611 electricity Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 239000000126 substance Substances 0.000 description 8
- 230000012447 hatching Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000002708 enhancing effect Effects 0.000 description 5
- UHOVQNZJYSORNB-UHFFFAOYSA-N Benzene Chemical compound C1=CC=CC=C1 UHOVQNZJYSORNB-UHFFFAOYSA-N 0.000 description 3
- -1 benzocyclobutane Alkane Chemical class 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- PMPVIKIVABFJJI-UHFFFAOYSA-N Cyclobutane Chemical compound C1CCC1 PMPVIKIVABFJJI-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 150000003851 azoles Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920006389 polyphenyl polymer Polymers 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of circuit arrangement method of compound semiconductor integrated circuit, comprising: delimit in equitant one first circuit layout in an overlapping region and second circuit layout in the upper surface of a compound semiconductor substrate；One includes overlapping region and its surrounding adjacent regions adjacent to crossover region；One first dielectric regions delimited to overlap in neighbouring crossover region and with least partially overlapped region；A first metal layer is formed in the first circuit layout；One first dielectric bumps are formed in the first dielectric regions or being formed simultaneously the first dielectric bumps in the first dielectric regions and one second dielectric regions of one second dielectric bumps other than the first dielectric regions, wherein the thickness of the second dielectric bumps is not more than and at least partly less than the thickness of the first dielectric bumps；It forms a second metal layer to be laid out in second circuit, the humidity-proof ability of compound semiconductor integrated circuit can be significantly increased, and have many advantages, such as to improve the efficiency of compound semiconductor integrated circuit.
Description
Technical field
A kind of circuit arrangement method of the present invention in relation to compound semiconductor integrated circuit, it is espespecially a kind of that there is raising chemical combination
The circuit arrangement method of the compound semiconductor integrated circuit of the humidity-proof ability of object semiconductor integrated circuit.
Background technique
At a compound semiconductor integrated circuit (compound semiconductor integrated circuits)
In, when neither idiostatic metal layer needs staggeredly bridging (cross-connect), in staggeredly bridging between two metal layers
Region need to carry out isolation.The general prior art is to form the separation layer that is constituted with polyimides (Polyimide) to be isolated
The neither staggeredly bridging of idiostatic metal layer, is usually coated with the imido separation layer of a strata on a bottom metal layer,
A top metal layer is formed on the separation layer of polyimides, wherein bottom metal layer and top metal layer are neither idiostatic
Metal layer.In addition to bottom metal layer and top metal layer interlock bridge overlapping region and its nearby need this polyimides every
Except absciss layer, other regions do not need the imido separation layer of this strata.Since the prior art can't especially go to lose
It carves to remove the separation layer of polyimides, thus there is only bottom metal layers and top metal layer to interlock for the separation layer of polyimides
The overlapping region of bridging, other regions for not needing the separation layer of polyimides are not removed.
However, due to water absorption rate possessed by polyimides itself, so that the presence of the separation layer of polyimides can be to change
The humidity-proof ability for closing object semiconductor integrated circuit causes serious influence.In addition to staggeredly being bridged in bottom metal layer and top metal layer
Overlapping region necessarily have the separation layer of polyimides be isolated neither idiostatic bottom metal layer and top metal layer except,
Other do not need the broad area of the separation layer of polyimides, are to cause the humidity-proof ability of compound semiconductor integrated circuit substantially
Reduced main cause.
In addition, a kind of separation layer necessarily dielectric materials with low-k, neither idiostatic bottom is isolated
Metal layer and top metal layer, and due to the presence of separation layer, especially separation layer must be present in bottom metal layer and top metal
The overlapping region that layer staggeredly bridges, therefore separation layer is for attached in the overlapping region that bottom metal layer and top metal layer staggeredly bridge
The size of an impedance (Impedance) for close compound semiconductor integrated circuit can be influenced.
In view of this, inventor develops a kind of circuit arrangement method of compound semiconductor integrated circuit, can be avoided
The humidity-proof ability of compound semiconductor integrated circuit can be significantly increased in above-mentioned disadvantage, and there is raising compound partly to lead
The advantages that efficiency of body integrated circuit, is considered using elasticity and economy etc. with taking into account, therefore has generation of the invention then.
Summary of the invention
The technical issues of present invention is to be solved has two: if first, other can be effectively removed do not need polyimides
The moisture-resistant energy of compound semiconductor integrated circuit will be significantly increased in the separation layer of the polyimides of the broad area of separation layer
Power.Therefore, a kind of separation layer how is formed so that neither idiostatic bottom metal layer and top metal layer is isolated, and again can be effectively
It removes bottom metal layer and pushes up the separation layer of the broad area other than the overlapping region that metal layer staggeredly bridges, significantly to mention
The humidity-proof ability of high compound semiconductor integrated circuit is first technical problem of the invention to be solved.
If the separation layer for the broad area that other do not need separation layer second, can be effectively removed, in addition to isolation can be reduced
Except influence of the layer to the size of the impedance of compound semiconductor integrated circuit, or even can also exist by being designed adjustment
In bottom metal layer and top metal layer interlock bridge overlapping region near separation layer thickness, area and shape and select
The dielectric constant of the material of separation layer, so that the size of the impedance of compound semiconductor integrated circuit, which is affected to become, to be facilitated
The efficiency superiority and inferiority of compound semiconductor integrated circuit, make instead originally design adjust be unfavorable for compound semiconductor collection
At the influence of the impedance magnitude of circuit, it is transformed into the efficiency for facilitating compound semiconductor integrated circuit.Therefore, how to reduce
The separation layer is present in down payment category by being designed adjustment to the adverse effect of an impedance of compound semiconductor integrated circuit
Layer and top metal layer interlock bridge overlapping region near the separation layer thickness, area and shape and select the isolation
The dielectric constant of the material of layer, and then the efficiency for promoting compound semiconductor integrated circuit is second that the present invention to be solved
Technical problem.
To solve foregoing problems, to reach desired effect, the present invention provides a kind of object semiconductor integrated circuit that closes
Circuit arrangement method, comprising the following steps: A1: a compound semiconductor integrated circuit layout delimited in a compound semiconductor base
The upper surface of plate, wherein the compound semiconductor integrated circuit layout includes one first circuit layout and a second circuit cloth
Office, the region that wherein region of first circuit layout is laid out with the second circuit overlaps in an overlapping region, one adjacent to across
It connects region and is defined as the surrounding adjacent regions comprising the overlapping region and the overlapping region；A2: one first dielectric regions delimited
In the upper surface of the compound semiconductor substrate, wherein first dielectric regions are located at this within crossover region, and this
One dielectric regions overlap at least partly overlapping region, wherein first Jie of the upper surface of the compound semiconductor substrate
Region other than electric region is defined as one second dielectric regions；A3: a first metal layer is formed in the area of first circuit layout
In domain；A4: forming the low dielectric bumps that are made of a dielectric materials, wherein the low dielectric bumps be formed simultaneously in this
In one dielectric regions and second dielectric regions, it is convex that the low dielectric bumps in first dielectric regions are defined as one first dielectric
Block, the low dielectric bumps in second dielectric regions are defined as one second dielectric bumps, wherein the thickness of second dielectric bumps
Degree is not more than the thickness of first dielectric bumps, and the thickness of at least part of second dielectric bumps is convex less than first dielectric
The thickness of block；And A5: a second metal layer is formed in the region that the second circuit is laid out.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, the wherein low dielectric material
Material has a water absorption rate less than 5%.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, the wherein low dielectric material
Material includes at least one selected from following group: polybenzoxazoles (polybenzoxazole, abbreviation PBO) and benzocyclobutane
Alkane (Benzo Cyclobutane, abbreviation BCB).
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein in A4 step, shape
It is at the low dielectric bumps the following steps are included: low in forming one first in first dielectric regions and second dielectric regions simultaneously
Dielectric layer, wherein the thickness of first low dielectric layer is equal to the thickness of second dielectric bumps；And in first dielectric regions
One second low dielectric layer of interior formation, wherein the thickness of second low dielectric layer plus the thickness of first low dielectric layer be equal to this
The thickness of one dielectric bumps.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein in A4 step,
Middle formation low dielectric bumps are the following steps are included: simultaneously in forming one the in first dielectric regions and second dielectric regions
One low dielectric layer, wherein the thickness of first low dielectric layer is equal to the thickness of second dielectric bumps；Simultaneously in first dielectric
Second low dielectric layer is formed in region and second dielectric regions, wherein the thickness of second low dielectric layer is first low plus this
The thickness of dielectric layer is equal to the thickness of first dielectric bumps；And exposure development or etching are to remove in second dielectric regions
Second low dielectric layer.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein in A4 step, shape
At the low dielectric bumps the following steps are included: simultaneously in forming the low dielectric in first dielectric regions and second dielectric regions
Convex block, wherein the thickness of the low dielectric bumps is equal to the thickness of first dielectric bumps；And exposure development or etch this second
The low dielectric bumps in dielectric regions so that the low dielectric bumps in first dielectric regions with a thickness of first dielectric
The thickness of convex block, and the thickness with a thickness of second dielectric bumps of the low dielectric bumps in second dielectric regions.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein in A4 step, shape
At the low dielectric bumps the following steps are included: simultaneously in forming the low dielectric in first dielectric regions and second dielectric regions
Convex block；And exposure development or the low dielectric bumps in first dielectric regions and second dielectric regions are etched, so that should
The thickness with a thickness of first dielectric bumps of the low dielectric bumps in first dielectric regions, and in second dielectric regions
The thickness with a thickness of second dielectric bumps of the low dielectric bumps.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, the wherein overlapping region
Surrounding adjacent regions include region arround the overlapping region within the scope of 50 μm.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, the wherein low dielectric material
The dielectric constant of material is less than 7.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein formed this first
Dielectric bumps are further comprising the steps of: the impedance according to the compound semiconductor integrated circuit near crossover region
Required size determines the thickness, area and the shape that correspond to first dielectric bumps adjacent to crossover region and this is low
One dielectric constant of dielectric material promotes the effect of the compound semiconductor integrated circuit to form first dielectric bumps whereby
Energy.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein further including following
Step: it delimit a power amplifier and be in the layout of in the compound semiconductor integrated circuit layout；A power amplifier is formed in this
In the region of power amplifier layout, wherein the power amplifier includes a first end, a second end and a third end, wherein
One of the first end and the second end are an output end of the power amplifier, wherein the first end and first metal
One of layer and the second metal layer are electrical connected, and the second end and the first metal layer and the second metal layer are wherein
It is another be electrical connected so that the first end and the second end of the power amplifier by first dielectric bumps formed every
From；And according to the output resistance between the first end and the second end of the power amplifier near crossover region
Size needed for anti-, determine to correspond to first dielectric bumps adjacent to crossover region thickness, area and shape and should
One dielectric constant of dielectric materials promotes the compound semiconductor integrated circuit to form first dielectric bumps whereby
Efficiency.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, the wherein power amplification
Device is bipolar transistor or a heteroj unction bipolar transistor, which is a collector, which is an emitter-base bandgap grading,
The third end is a base stage, and wherein the output impedance is the impedance between the collector and the emitter-base bandgap grading of the power amplifier.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, the wherein power amplification
Device is a field-effect transistor, which is a drain electrode, which is a source electrode, which is a grid, and wherein this is defeated
Impedance is the impedance between the drain electrode and the source electrode of the power amplifier out.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein further including following
Step: delimiting a main power amplifier layout and a bias circuit power amplifier is in the layout of the integrated electricity of the compound semiconductor
In the layout of road；A main power amplifier is formed in the region that the main power amplifier is laid out, wherein the main power amplifier packet
A main power amplifier first end, a main power amplifier second end and a main power amplifier third end are included, wherein the master
Power amplifier third end is an input terminal of the main power amplifier；A bias circuit power amplifier is formed in the bias plasma
In the region of road power amplifier layout, wherein the bias circuit power amplifier includes a bias circuit power amplifier first
End, a bias circuit power amplifier second end and a bias circuit power amplifier third end, wherein the bias circuit function
One of rate amplifier first end and the first metal layer and the second metal layer are electrical connected, the main power amplifier
Three ends are electrical connected with the first metal layer and the wherein another of the second metal layer, so that the bias circuit power amplifier
First end and the main power amplifier third end are formed by first dielectric bumps to be isolated；And according to this adjacent to crossover region
Size needed for an impedance between neighbouring bias circuit power amplifier first end and the main power amplifier third end, certainly
Surely correspond to first dielectric bumps adjacent to crossover region thickness, area and shape and the dielectric materials one
Dielectric constant promotes the efficiency of the compound semiconductor integrated circuit, wherein the impedance to form first dielectric bumps whereby
For an input impedance of the main power amplifier.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein the main power is put
Big device and the bias circuit power amplifier are bipolar transistor or a heteroj unction bipolar transistor, the main power
Amplifier first end is a main power amplifier collector, which is a main power amplifier emitter-base bandgap grading, should
Main power amplifier third end is a main power amplifier base stage, which is a bias circuit
Power amplifier collector, the bias circuit power amplifier second end are a bias circuit power amplifier emitter-base bandgap grading, the bias plasma
Road power amplifier third end is a bias circuit power amplifier base stage, and wherein the input impedance is that the bias circuit power is put
Impedance between big device collector and the main power amplifier base stage.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein the main power is put
Big device and the bias circuit power amplifier are a field-effect transistor, which is a main power amplification
Device drain electrode, the main power amplifier second end are a main power amplifier source electrode, which is a main function
Rate amplifier grid, the bias circuit power amplifier first end are bias circuit power amplifier drain electrode, the bias circuit
Power amplifier second end is a bias circuit power amplifier source electrode, which is a bias
Circuit power amplifier grid, wherein the input impedance is bias circuit power amplifier drain electrode and the main power amplification grid
The impedance of interpolar.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein A3 step with
And further include the steps that insulating layer in a formation at least one between A4 step, wherein this at least one insulating layer be formed in the chemical combination
On object semiconductor substrate and on the first metal layer, and this at least one insulating layer be formed in the low dielectric bumps it
Under.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein constituting this at least
The material of insulating layer includes at least one selected from following group: silicon nitride (SiN) and silica (SiO on one2)。
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein in A3 step it
Before further include the steps that a formation at least once insulating layer, wherein this at least once insulating layer is formed in the compound semiconductor base
On plate, and this at least once insulating layer be formed under the first metal layer and the low dielectric bumps under.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein constituting this at least
Once the material of insulating layer includes at least one selected from following group: silicon nitride (SiN) and silica (SiO2)。
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein A5 step it
After further include the steps that an a formation at least protective layer on the compound semiconductor integrated circuit.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein constituting this at least
The material of one protective layer includes at least one selected from following group: silicon nitride (SiN) and silica (SiO2)。
In addition, the present invention also provides a kind of circuit arrangement methods for closing object semiconductor integrated circuit, comprising the following steps:
B1: delimiting a compound semiconductor integrated circuit layout in the upper surface of a compound semiconductor substrate, wherein the compound half
Conductor integrated circuit layout includes that one first circuit layout and a second circuit are laid out, wherein the region of first circuit layout
With the second circuit layout region overlap in an overlapping region, one adjacent to crossover region be defined as comprising the overlapping region with
And the surrounding adjacent regions of the overlapping region；B2: delimiting one first dielectric regions in the upper surface of the compound semiconductor substrate,
Wherein first dielectric regions are located at this within crossover region, and first dielectric regions and at least partly overlapping region
It overlaps, wherein the region other than first dielectric regions of the upper surface of the compound semiconductor substrate is defined as one second Jie
Electric region；B3: a first metal layer is formed in the region of first circuit layout；B4: it is formed by a dielectric materials institute structure
At one first dielectric bumps in first dielectric regions；And B5: it forms a second metal layer and is laid out in the second circuit
Region in.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, the wherein low dielectric material
Material has a water absorption rate less than 5%.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, the wherein low dielectric material
Material includes at least one selected from following group: polybenzoxazoles (polybenzoxazole, abbreviation PBO) and benzocyclobutane
Alkane (Benzo Cyclobutane, abbreviation BCB).
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein in B4 step, shape
At first dielectric bumps the following steps are included: simultaneously in one low Jie of formation in first dielectric regions and second dielectric regions
Electric convex block；And exposure development or etching remove the low dielectric bumps in second dielectric regions, so that first dielectric regime
The thickness with a thickness of first dielectric bumps of the low dielectric bumps in domain, and the low dielectric in second dielectric regions is convex
Block with a thickness of zero.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein in B4 step, shape
At first dielectric bumps the following steps are included: simultaneously in one low Jie of formation in first dielectric regions and second dielectric regions
Electric convex block；And exposure development or the low dielectric bumps in first dielectric regions and second dielectric regions are etched, so that
The thickness with a thickness of first dielectric bumps of the low dielectric bumps in first dielectric regions, and in second dielectric regions
The low dielectric bumps with a thickness of zero.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, the wherein overlapping region
Surrounding adjacent regions include region arround the overlapping region within the scope of 50 μm.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, the wherein low dielectric material
The dielectric constant of material is less than 7.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein formed this first
Dielectric bumps are further comprising the steps of: the impedance according to the compound semiconductor integrated circuit near crossover region
Required size determines the thickness, area and the shape that correspond to first dielectric bumps adjacent to crossover region and this is low
One dielectric constant of dielectric material promotes the effect of the compound semiconductor integrated circuit to form first dielectric bumps whereby
Energy.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein further including following
Step: it delimit a power amplifier and be in the layout of in the compound semiconductor integrated circuit layout；A power amplifier is formed in this
In the region of power amplifier layout, wherein the power amplifier includes a first end, a second end and a third end, wherein
One of the first end and the second end are an output end of the power amplifier, wherein the first end and first metal
One of layer and the second metal layer are electrical connected, and the second end and the first metal layer and the second metal layer are wherein
It is another be electrical connected so that the first end and the second end of the power amplifier by first dielectric bumps formed every
From；And according to the output resistance between the first end and the second end of the power amplifier near crossover region
Size needed for anti-, determine to correspond to first dielectric bumps adjacent to crossover region thickness, area and shape and should
One dielectric constant of dielectric materials promotes the compound semiconductor integrated circuit to form first dielectric bumps whereby
Efficiency.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, the wherein power amplification
Device is bipolar transistor or a heteroj unction bipolar transistor, which is a collector, which is an emitter-base bandgap grading,
The third end is a base stage, and wherein the output impedance is the impedance between the collector and the emitter-base bandgap grading of the power amplifier.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, the wherein power amplification
Device is a field-effect transistor, which is a drain electrode, which is a source electrode, which is a grid, and wherein this is defeated
Impedance is the impedance between the drain electrode and the source electrode of the power amplifier out.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein further including following
Step: delimiting a main power amplifier layout and a bias circuit power amplifier is in the layout of the integrated electricity of the compound semiconductor
In the layout of road；A main power amplifier is formed in the region that the main power amplifier is laid out, wherein the main power amplifier packet
A main power amplifier first end, a main power amplifier second end and a main power amplifier third end are included, wherein the master
Power amplifier third end is an input terminal of the main power amplifier；A bias circuit power amplifier is formed in the bias plasma
In the region of road power amplifier layout, wherein the bias circuit power amplifier includes a bias circuit power amplifier first
End, a bias circuit power amplifier second end and a bias circuit power amplifier third end, wherein the bias circuit function
One of rate amplifier first end and the first metal layer and the second metal layer are electrical connected, the main power amplifier
Three ends are electrical connected with the first metal layer and the wherein another of the second metal layer, so that the bias circuit power amplifier
First end and the main power amplifier third end are formed by first dielectric bumps to be isolated；And according to this adjacent to crossover region
Size needed for an impedance between neighbouring bias circuit power amplifier first end and the main power amplifier third end, certainly
Surely correspond to first dielectric bumps adjacent to crossover region thickness, area and shape and the dielectric materials one
Dielectric constant promotes the efficiency of the compound semiconductor integrated circuit, wherein the impedance to form first dielectric bumps whereby
For an input impedance of the main power amplifier.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein the main power is put
Big device and the bias circuit power amplifier are bipolar transistor or a heteroj unction bipolar transistor, the main power
Amplifier first end is a main power amplifier collector, which is a main power amplifier emitter-base bandgap grading, should
Main power amplifier third end is a main power amplifier base stage, which is a bias circuit
Power amplifier collector, the bias circuit power amplifier second end are a bias circuit power amplifier emitter-base bandgap grading, the bias plasma
Road power amplifier third end is a bias circuit power amplifier base stage, and wherein the input impedance is that the bias circuit power is put
Impedance between big device collector and the main power amplifier base stage.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein the main power is put
Big device and the bias circuit power amplifier are a field-effect transistor, which is a main power amplification
Device drain electrode, the main power amplifier second end are a main power amplifier source electrode, which is a main function
Rate amplifier grid, the bias circuit power amplifier first end are bias circuit power amplifier drain electrode, the bias circuit
Power amplifier second end is a bias circuit power amplifier source electrode, which is a bias
Circuit power amplifier grid, wherein the input impedance is bias circuit power amplifier drain electrode and the main power amplification grid
The impedance of interpolar.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein B3 step with
And further include the steps that insulating layer in a formation at least one between B4 step, wherein this at least one insulating layer be formed in the chemical combination
On object semiconductor substrate and on the first metal layer, and this at least one insulating layer be formed in first dielectric bumps it
Under.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein constituting this at least
The material of insulating layer includes at least one selected from following group: silicon nitride (SiN) and silica (SiO on one2)。
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein B3 step it
Before further include the steps that a formation at least once insulating layer, wherein this at least once insulating layer is formed in the compound semiconductor base
On plate, and this at least once insulating layer be formed under the first metal layer and first dielectric bumps under.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein constituting this at least
Once the material of insulating layer includes at least one selected from following group: silicon nitride (SiN) and silica (SiO2)。
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein B5 step it
After further include the steps that an a formation at least protective layer on the compound semiconductor integrated circuit.
In one embodiment, the circuit arrangement method of compound semiconductor integrated circuit above-mentioned, wherein constituting this at least
The material of one protective layer includes at least one selected from following group: silicon nitride (SiN) and silica (SiO2)。
To further appreciate that the present invention, preferred embodiment is lifted below, cooperates attached drawing, by specific composition content of the invention
And its effect of reached, detailed description are as follows.
Detailed description of the invention
The one of Fig. 1 and Figure 1A respectively a kind of circuit arrangement method of compound semiconductor integrated circuit of the present invention is specific
The top view and sectional view of embodiment；
Figure 1B and Fig. 1 C is respectively a kind of the another of circuit arrangement method of compound semiconductor integrated circuit of the present invention
The top view and sectional view of specific embodiment；
Fig. 1 D and Fig. 1 E are respectively a kind of the another of circuit arrangement method of compound semiconductor integrated circuit of the present invention
The top view and sectional view of specific embodiment；
Fig. 1 F and Fig. 1 G are respectively a kind of the another of circuit arrangement method of compound semiconductor integrated circuit of the present invention
The top view and sectional view of specific embodiment；
Fig. 1 H and Fig. 1 I are respectively a kind of the another of circuit arrangement method of compound semiconductor integrated circuit of the present invention
The top view and sectional view of specific embodiment；
Fig. 1 J and Fig. 1 K are respectively a kind of the another of circuit arrangement method of compound semiconductor integrated circuit of the present invention
The top view and sectional view of specific embodiment；
Fig. 1 L and Fig. 1 M are respectively a kind of the another of circuit arrangement method of compound semiconductor integrated circuit of the present invention
The top view and sectional view of specific embodiment；
Fig. 1 N and Fig. 1 O are respectively a kind of the another of circuit arrangement method of compound semiconductor integrated circuit of the present invention
The top view and sectional view of specific embodiment；
Fig. 1 P is a kind of still another embodiment of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
Top view；
Fig. 1 Q is a kind of still another embodiment of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
Top view；
Fig. 2 is a kind of circuit arrangement method flow chart of compound semiconductor integrated circuit of the present invention；
Fig. 2A is a kind of circuit arrangement method flow chart of compound semiconductor integrated circuit of the present invention；
Fig. 2 B~Fig. 2 G is a kind of specific embodiment of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
Process step diagrammatic cross-section；
Fig. 2 H is a kind of another specific embodiment of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
Sectional view；
Fig. 2 I is a kind of still another embodiment section of compound semiconductor integrated circuit layout method of the present invention
Figure；
Fig. 2 J is a kind of still another embodiment of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
Sectional view；
Fig. 2 K is a kind of another specific embodiment of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
Sectional view；
Fig. 2 L is a kind of still another embodiment of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
Sectional view；
Fig. 2 M is a kind of still another embodiment of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
Sectional view；
Fig. 3 is a kind of vertical view of a specific embodiment of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
Schematic diagram；
Fig. 3 A is a kind of another specific embodiment of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
Schematic top plan view；
Fig. 3 B depicts the schematic diagram of the local circuit of Fig. 3 A；
Fig. 3 C is the diagrammatic cross-section of the vertical cross-section of b-b ' hatching in Fig. 3 B；
Fig. 3 D is a kind of section of the another embodiment of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
The diagrammatic cross-section of structure；
Fig. 4 is a kind of part of a specific embodiment of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
Circuit layout schematic diagram；
Fig. 4 A is the partial circuit diagram of the embodiment corresponded in Fig. 4；
Fig. 4 B is the diagrammatic cross-section of the vertical cross-section of c-c ' hatching in Fig. 4；
Fig. 4 C is the partial enlarged view in the region of V box in Fig. 4 B.
Description of symbols:
Specific embodiment
Please refer to Fig. 1 and Figure 1A, Fig. 1 and Figure 1A are respectively a kind of compound semiconductor integrated circuit of the present invention
Circuit arrangement method a specific embodiment top view and sectional view.One compound semiconductor integrated circuit layout, 1 quilt
It delimit in the upper surface of a compound semiconductor substrate 10, wherein compound semiconductor integrated circuit layout 1 includes one first electricity
Road layout 21 and second circuit layout 22.One the first metal layer 61 is formed in the region of the first circuit layout 21.Wherein
The region of first circuit layout 21 and the region of second circuit layout 22 overlap in an overlapping region 31.A wherein neighbouring bridging
Region 33 includes the surrounding adjacent regions 32 of overlapping region 31 and overlapping region 31.One first dielectric regions, 41 (the thick frame of black
Region) delimited in the upper surface of compound semiconductor substrate 10, wherein the first dielectric regions 41 are located at neighbouring crossover region
Within 33, and the first dielectric regions 41 and least partially overlapped region 31 overlap (in this embodiment, the first dielectric regions 41
Include entire overlapping region 31).Wherein the first dielectric regions of the upper surface of compound semiconductor substrate 10 41 (the thick frame of black
Region) other than region be one second dielectric regions 42.Low 50 being formed in of dielectric bumps that one dielectric materials are constituted
It closes on object semiconductor substrate 10 and on the first metal layer 61.In this embodiment, low dielectric bumps 50 be formed simultaneously in
In first dielectric regions 41 (region of the thick frame of black) and the second dielectric regions 42.It is wherein formed in the first dielectric regions 41
Low dielectric bumps 50 be one first dielectric bumps 51 (region of the thick frame of black), the first dielectric bumps 51 have one first dielectric
The thickness 53 of convex block.Wherein being formed in low dielectric bumps 50 in the second dielectric regions 42 is one second dielectric bumps 52, second
Dielectric bumps 52 have the thickness 54 of one second dielectric bumps, wherein the thickness 54 of the second dielectric bumps is convex no more than the first dielectric
The thickness 53 of block, and the thickness 54 of at least partly the second dielectric bumps less than the first dielectric bumps thickness 53 (such as Figure 1A institute
Show).One second metal layer 62 is formed in the region of second circuit layout 22.In this embodiment, the formation of second metal layer 62
On the first dielectric bumps 51 and on the second dielectric bumps 52.
In schema of the invention, wherein Fig. 1, Figure 1B, Fig. 1 D, Fig. 1 F, Fig. 1 H, Fig. 1 J, Fig. 1 L, Fig. 1 N, Fig. 1 P, figure
In the schemas such as 1Q, Fig. 3 B and Fig. 4, the first metal layer 61 be upper right to lower-left 45 degree of oblique lines block；And second metal layer
The block of 62 45 degree of oblique lines for upper left to bottom right；Upper right is to 45 degree of oblique lines of lower-left and 45 degree of oblique lines two of upper left to bottom right
The staggered block of person is then overlapping region 31；The region of the thick frame of black is the first dielectric regions 41, while being also that the first dielectric is convex
Block 51 is formed by region.In addition, the region of the thick frame of black is also the first dielectric regions 41 in Fig. 3 and Fig. 3 A, it is also simultaneously
First dielectric bumps 51 are formed by region.
Please refer to Figure 1B and Fig. 1 C, Figure 1B and Fig. 1 C is respectively a kind of integrated electricity of compound semiconductor of the present invention
The top view and sectional view of the another specific embodiment of the circuit arrangement method on road.One compound semiconductor integrated circuit layout
1 delimited in the upper surface of a compound semiconductor substrate 10, and wherein compound semiconductor integrated circuit layout 1 includes one first
Circuit layout 21 and second circuit layout 22.One the first metal layer 61 is formed in the region of the first circuit layout 21.Its
In the first circuit layout 21 region and second circuit layout 22 region overlap in an overlapping region 31.Wherein one it is neighbouring across
Connect the surrounding adjacent regions 32 that region 33 includes overlapping region 31 and overlapping region 31.(black is thick for one first dielectric regions 41
The region of frame) it delimited in the upper surface of compound semiconductor substrate 10, wherein the first dielectric regions 41 are located at neighbouring bridging area
Within domain 33, and the first dielectric regions 41 and least partially overlapped region 31 overlap (in this embodiment, the first dielectric regions
41 include entire overlapping region 31).Wherein 41 (the thick frame of black of the first dielectric regions of the upper surface of compound semiconductor substrate 10
Region) other than region be one second dielectric regions 42.The low dielectric bumps 50 that one dielectric materials are constituted are formed in
On compound semiconductor substrate 10 and on the first metal layer 61.In this embodiment, low dielectric bumps 50 are formed only in
It in first dielectric regions 41 (region of the thick frame of black), and is not formed in the second dielectric regions 42, therefore, in this embodiment
In, the second dielectric regions 42 have no the second dielectric bumps 52.The low dielectric bumps 50 being wherein formed in the first dielectric regions 41
For one first dielectric bumps 51 (region of the thick frame of black), the first dielectric bumps 51 have the thickness 53 of one first dielectric bumps.
One second metal layer 62 is formed in the region of second circuit layout 22.In this embodiment, second metal layer 62 is formed in
On one dielectric bumps 51 and on compound semiconductor substrate 10.
In the embodiment of Figure 1B~Fig. 1 C, low dielectric bumps 50 are simultaneously by 51 (the thick frame of black of the first dielectric bumps
Region) and the second dielectric bumps 52 constitute (embodiment of such as Fig. 1 and Figure 1A), or only by the first dielectric bumps 51
(region of the thick frame of black) is constituted and the second dielectric bumps 52 (such as embodiment of Figure 1B and Fig. 1 C) of nothing.First dielectric bumps
51 major function is the first metal layer 61 and second metal layer 62 in isolation different potentials.However, the second dielectric bumps
52 humidity-proof abilities that but will cause compound semiconductor integrated circuit 1 are greatly reduced.Therefore, when the thickness 54 of the second dielectric bumps
No more than the thickness 53 of the first dielectric bumps, and the thickness 54 of at least partly the second dielectric bumps is less than the thickness of the first dielectric bumps
When spending 53, it will help the humidity-proof ability of enhancing compound semiconductor integrated circuit 1.Especially when at least partly the second dielectric bumps
Thickness 54 less than the first dielectric bumps thickness 53 90% or less when, compound semiconductor integrated circuit can be remarkably reinforced
1 humidity-proof ability.And the thickness of the second dielectric bumps 52 is smaller, then to the humidity-proof ability of compound semiconductor integrated circuit 1
Enhancing is more obvious effect.And when the second all dielectric bumps 52 are all removed (namely as shown in Figure 1B and Fig. 1 C
Embodiment, without the second dielectric bumps 52), there is splendid effect to the humidity-proof ability of enhancing compound semiconductor integrated circuit 1.
In all embodiments of the invention, some have the second dielectric bumps 52, and some embodiments then have no second
Dielectric bumps 52.In the embodiment with the second dielectric bumps 52 of the invention, at least partly thickness of the second dielectric bumps
Degree 54 be greater than 0 and less than the thickness of the first dielectric bumps 53 90%, greater than 0 and less than the thickness of the first dielectric bumps 53
85%, greater than 0 and less than the thickness of the first dielectric bumps 53 80%, greater than 0 and less than the thickness of the first dielectric bumps 53
75%, greater than 0 and less than the thickness of the first dielectric bumps 53 70%, greater than 0 and less than the thickness of the first dielectric bumps 53
65%, greater than 0 and less than the thickness of the first dielectric bumps 53 60%, greater than 0 and less than the thickness of the first dielectric bumps 53
55%, greater than 0 and less than the thickness of the first dielectric bumps 53 50%, greater than 0 and less than the thickness of the first dielectric bumps 53
45%, greater than 0 and less than the thickness of the first dielectric bumps 53 40%, greater than 0 and less than the thickness of the first dielectric bumps 53
35%, greater than 0 and less than the thickness of the first dielectric bumps 53 30%, greater than 0 and less than the thickness of the first dielectric bumps 53
25%, greater than 0 and less than the thickness of the first dielectric bumps 53 20%, greater than 0 and less than the thickness of the first dielectric bumps 53
15%, greater than 0 and less than the thickness of the first dielectric bumps 53 12%, greater than 0 and less than the thickness of the first dielectric bumps 53
10%, greater than 0 and less than the thickness of the first dielectric bumps 53 9%, greater than 0 and less than the thickness of the first dielectric bumps 53
8%, greater than 0 and less than the thickness of the first dielectric bumps 53 7%, greater than 0 and less than the thickness of the first dielectric bumps 53
6%, greater than 0 and less than the thickness of the first dielectric bumps 53 5%, greater than 0 and less than the thickness of the first dielectric bumps 53
4%, 3%, 2% greater than 0 and less than the thickness of the first dielectric bumps 53 greater than 0 and less than the thickness of the first dielectric bumps 53
Or 1% greater than 0 and less than the thickness of the first dielectric bumps 53.
In all embodiments of the invention, overlapping region 31 is that the region of the first circuit layout 21 and second circuit are laid out
The equitant region in 22 region.And the surrounding adjacent regions 32 of overlapping region 31 refer to arround overlapping region 31 at least 50 μm
Region within range, the region within the scope of at least 47 μm, the region within the scope of at least 45 μm, at least 43 μm of model
Region within enclosing, the region within the scope of at least 40 μm, the region within the scope of at least 37 μm, at least 35 μm of range
Within region, the region within the scope of at least 33 μm, the region within the scope of at least 30 μm, at least 28 μm of range with
Interior region, the region within the scope of at least 25 μm, the region within the scope of at least 23 μm, within the scope of at least 20 μm
Region, the region within the scope of at least 17 μm, the region within the scope of at least 15 μm, within the scope of at least 12 μm
Region, the region within the scope of at least 10 μm, the region within the scope of at least 9 μm, the area within the scope of at least 8 μm
Domain, the region within the scope of at least 7 μm, the region within the scope of at least 6 μm or the region within the scope of at least 5 μm.
And so-called neighbouring crossover region 33 is made of the surrounding adjacent regions 32 of overlapping region 31 and overlapping region 31.
In addition, the present invention when selecting the material of low dielectric bumps 50, selects the low dielectric bumps 50 with low water absorption,
Wherein the water absorption rate of low dielectric bumps 50 at least below 5%, at least below 4.5%, at least below 4%, at least below 3.5%,
At least below 3%, at least below 2.5% or at least below 2%.
In an embodiment of the present invention, the material of selected low dielectric bumps 50 can be a polybenzoxazoles
(polybenzoxazole, abbreviation PBO) or a benzocyclobutane (Benzo Cyclobutane, abbreviation BCB).Wherein low dielectric
The optimal selection of the material of convex block 50 is the photosensitive polybenzoxazoles (polybenzoxazole, abbreviation PBO) of a tool or a benzene
And cyclobutane (Benzo Cyclobutane, abbreviation BCB).It can be by exposure development or the method for etching, by the second dielectric
Convex block 52 removes.Especially when selection is to have the material of photosensitive polybenzoxazoles or benzocyclobutane as low dielectric bumps 50
Material when, being can easily will be in the second dielectric regions 42 by having photosensitive polybenzoxazoles in the method for exposure development
Or the second dielectric bumps 52 that benzocyclobutane is constituted completely remove, and enhance the anti-of compound semiconductor integrated circuit 1 whereby
Wet ability.
In all embodiments of the invention, its dielectric constant of the material of selected low dielectric bumps 50 be at least below
7, at least below 6.7, at least below 6.3, at least below 6, at least below 5.7, at least below 5.3, at least below 5, to when young
In 4.7, at least below 4.3, at least below 4, at least below 3.7, at least below 3.3, at least below 3, at least below 2.7, extremely
When young in 2.3, at least below 2, at least below 1.7, at least below 1.3 or at least below 1.
The embodiment of Fig. 1 D~Fig. 1 O is please referred to, there is a different overlapping regions 31,1 respectively in these embodiments
The change type of one dielectric bumps 51 (region of the thick frame of black) and one second dielectric bumps 52.From these embodiments, in weight
The case where surrounding adjacent regions 32 in folded region 31 have no other overlapping region 31, by the case where single overlapping region 31 Lai
See that the various change between overlapping region 31, the first dielectric bumps 51 (region of the thick frame of black) and the second dielectric bumps 52 can
It can property.
It is respectively a kind of integrated electricity of compound semiconductor of the present invention please refer to Fig. 1 D and Fig. 1 E, Fig. 1 D and Fig. 1 E
The top view and sectional view of the still another embodiment of the circuit arrangement method on road.Its primary structure and Fig. 1 and Figure 1A institute
The embodiment shown is roughly the same, but, wherein size phase of first dielectric regions 41 (region of the thick frame of black) with overlapping region 31
It overlaps together and completely.
It is respectively a kind of integrated electricity of compound semiconductor of the present invention please refer to Fig. 1 F and Fig. 1 G, Fig. 1 F and Fig. 1 G
The top view and sectional view of the still another embodiment of the circuit arrangement method on road.Its primary structure and Fig. 1 D and Fig. 1 E institute
The embodiment shown is roughly the same, but, wherein low dielectric bumps 50 are formed only in the first dielectric regions 41 (region of the thick frame of black)
It is interior, and low dielectric bumps 50 are had no in the second dielectric regions 42, therefore in this embodiment, only the first dielectric bumps 51
(region of the thick frame of black), and without the second dielectric bumps 52.In this embodiment, it is convex to be formed in the first dielectric for second metal layer 62
On block 51 and on compound semiconductor substrate 10.
It is respectively a kind of integrated electricity of compound semiconductor of the present invention please refer to Fig. 1 H and Fig. 1 I, Fig. 1 H and Fig. 1 I
The top view and sectional view of the another specific embodiment of the circuit arrangement method on road.Its primary structure and Fig. 1 and Figure 1A institute
The embodiment shown is roughly the same, but, wherein the first dielectric regions 41 (region of the thick frame of black) be fully located at overlapping region 31 it
It is interior.
It is respectively a kind of integrated electricity of compound semiconductor of the present invention please refer to Fig. 1 J and Fig. 1 K, Fig. 1 J and Fig. 1 K
The top view and sectional view of the still another embodiment of the circuit arrangement method on road.Its primary structure and Fig. 1 H and Fig. 1 I institute
The embodiment shown is roughly the same, but, wherein low dielectric bumps 50 are formed only in the first dielectric regions 41 (region of the thick frame of black)
It is interior, and low dielectric bumps 50 are had no in the second dielectric regions 42, therefore in this embodiment, only the first dielectric bumps 51
(region of the thick frame of black), and without the second dielectric bumps 52.In this embodiment, it is convex to be formed in the first dielectric for second metal layer 62
On block 51 and on compound semiconductor substrate 10.
It is respectively a kind of integrated electricity of compound semiconductor of the present invention please refer to Fig. 1 L and Fig. 1 M, Fig. 1 L and Fig. 1 M
The top view and sectional view of the still another embodiment of the circuit arrangement method on road.Its primary structure and Fig. 1 and Figure 1A institute
The embodiment shown is roughly the same, but, wherein region 31 is mutually Chong Die with partly overlapping for the first dielectric regions 41 (region of the thick frame of black)
It is folded.
It is respectively a kind of integrated electricity of compound semiconductor of the present invention please refer to Fig. 1 N and Fig. 1 O, Fig. 1 N and Fig. 1 O
The top view and sectional view of the another specific embodiment of the circuit arrangement method on road.Its primary structure and Fig. 1 L and Fig. 1 M institute
The embodiment shown is roughly the same, but, wherein low dielectric bumps 50 are formed only in the first dielectric regions 41 (region of the thick frame of black)
It is interior, and low dielectric bumps 50 are had no in the second dielectric regions 42, therefore in this embodiment, only the first dielectric bumps 51
(region of the thick frame of black), and without the second dielectric bumps 52.In this embodiment, it is convex to be formed in the first dielectric for second metal layer 62
On block 51 and on compound semiconductor substrate 10.
The embodiment of Fig. 1 P and Fig. 1 Q are please referred to again, then there is the multiple heavy of different change types respectively in these embodiments
Folded region 31, and these multiple overlapping regions 31 are apart from all very close.Therefore in these embodiments, each overlapping region 31
Surrounding adjacent regions 32 can cover the surrounding proximities of other overlapping regions 31 and other overlapping region 31 mutually
Domain 32.Thus, it is made of the surrounding adjacent regions 32 of these multiple overlapping regions 31 and these multiple overlapping regions 31
Neighbouring crossover region 33 is a combination zone.Fig. 1 P is first please referred to, Fig. 1 P is a kind of compound semiconductor integrated circuit of the present invention
Circuit arrangement method still another embodiment top view.One compound semiconductor integrated circuit layout 1 delimited in one
The upper surface of 10 (not shown) of compound semiconductor substrate, wherein compound semiconductor integrated circuit layout 1 includes one the
One circuit layout 21 and second circuit layout 22.One the first metal layer 61 is formed in the region of the first circuit layout 21.
Wherein the first circuit layout 21 divides for three regions, therefore the first metal layer 61 is respectively formed as firstth area of the first metal layer
611, the first metal layer secondth area 612 and a first metal layer third area 613.Wherein the region of the first circuit layout 21 with
The region of second circuit layout 22 overlaps in an overlapping region 31, wherein adjacent around overlapping region 31 and overlapping region 31
Near field 32 forms one adjacent to crossover region 33.Overlapping region 31 is divided into three regions, respectively one overlapping in this embodiment
Region the firstth area 311, overlapping region secondth area 312 and an overlapping region third area 313.Due to this three overlapping regions 31
It is very close, therefore this three overlapping regions 31 and its surrounding adjacent regions 32 are to form neighbouring crossover region as shown in the figure
33.In this embodiment, neighbouring crossover region 33 is a combination zone, the combination zone include: the firstth area of overlapping region 311,
The secondth area of overlapping region 312, overlapping region third area 313, the surrounding adjacent regions in the firstth area of overlapping region 311, overlapping region
The surrounding adjacent regions in the second area 312 and the surrounding adjacent regions in overlapping region third area 313.One first dielectric regions 41
(region of the thick frame of black) delimited in the upper surface of 10 (not shown) of compound semiconductor substrate, wherein the first dielectric regime
Domain 41 is located within neighbouring crossover region 33, and the first dielectric regions 41 overlap (herein in fact with least partially overlapped region 31
It applies in example, the first dielectric regions 41 include the firstth area of overlapping region 311, the secondth area of overlapping region 312 and overlapping region third
Area 313).In addition, one second dielectric regions 42 are defined as the of the upper surface of 10 (not shown) of compound semiconductor substrate
Region other than one dielectric regions 41 (region of the thick frame of black).The low formation of dielectric bumps 50 that one dielectric materials are constituted
On 10 (not shown) of compound semiconductor substrate and on the first metal layer 61.In this embodiment, low dielectric
Convex block 50 is formed only in the first dielectric regions 41 (region of the thick frame of black), and has no low dielectric in the second dielectric regions 42
Convex block 50.The low dielectric bumps 50 being wherein formed in the first dielectric regions 41 are one first dielectric bumps 51, wherein first is situated between
Electric convex block 51 has 53 (not shown) of thickness of one first dielectric bumps.Therefore in this embodiment, only the first dielectric bumps
51 (regions of the thick frame of black), and without the second dielectric bumps 52.One second metal layer 62 is formed in the area of second circuit layout 22
In domain.In this embodiment, second metal layer 62 is formed on the first dielectric bumps 51 and compound semiconductor substrate 10
On.In addition, the present embodiment another kind change type embodiment, primary structure is roughly the same with the present embodiment, but, wherein low Jie
Electric convex block 50 is formed simultaneously in the first dielectric regions 41 and in the second dielectric regions 42, wherein being formed in the second dielectric regions
Low dielectric bumps 50 in 42 are one second dielectric bumps 52, wherein the second dielectric bumps 52 have the thickness of one second dielectric bumps
54 (not shown)s are spent, and 54 (not shown) of thickness of wherein at least the second dielectric bumps of part is less than the thickness of the first dielectric bumps
53 (not shown)s.Second metal layer 62 is then formed on the first dielectric bumps 51 and on the second dielectric bumps 52.
Fig. 1 Q is please referred to, Fig. 1 Q is a kind of another tool of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
The top view of body embodiment.In this embodiment, the first circuit layout 21 is divided to for two regions, therefore the first metal layer 61 is distinguished
Be formed as the first metal layer firstth area 611 and secondth area of the first metal layer 612.The wherein region of the first circuit layout 21
It overlaps with the region of second circuit layout 22 in an overlapping region 31, wherein around overlapping region 31 and overlapping region 31
Adjacent domain 32 forms one adjacent to crossover region 33.Overlapping region 31 is divided into two regions, respectively a weight in this embodiment
Folded region the firstth area 311 and the secondth area of an overlapping region 312.Since this two overlapping regions 31 are very close, this two
A overlapping region 31 and its surrounding adjacent regions 32 are to form neighbouring crossover region 33 as shown in the figure.In this embodiment,
Neighbouring crossover region 33 is a combination zone, which includes: the firstth area of overlapping region 311, the secondth area of overlapping region
312, the surrounding adjacent regions in the surrounding adjacent regions in the firstth area of overlapping region 311 and the secondth area of overlapping region 312.One first
Dielectric regions 41 (region of the thick frame of black) delimited in the upper surface of 10 (not shown) of compound semiconductor substrate, wherein
First dielectric regions 41 are located within neighbouring crossover region 33, and the first dielectric regions 41 are mutually Chong Die with least partially overlapped region 31
Folded (in this embodiment, the first dielectric regions 41 include the second area 312 of the firstth area of overlapping region 311 and overlapping region).
Referring to Fig. 2, Fig. 2 is a kind of circuit arrangement method flow chart of compound semiconductor integrated circuit of the present invention.It should
Circuit arrangement method is the following steps are included: (please refer to Fig. 1, Figure 1A, Fig. 1 D, Fig. 1 E, Fig. 1 H, Fig. 1 I, Fig. 1 L and figure
1M) A1: delimiting a compound semiconductor integrated circuit layout 1 in the upper surface of a compound semiconductor substrate 10, wherein chemical combination
Object semiconductor integrated circuit layout 1 includes one first circuit layout 21 and second circuit layout 22, wherein the first circuit cloth
The region of office 21 and the region of second circuit layout 22 overlap in an overlapping region 31, and one is defined as wrapping adjacent to crossover region 33
Surrounding adjacent regions 32 containing overlapping region 31 and overlapping region 31；A2: delimit one first dielectric regions 41 (the thick frame of black
Region) in the upper surface of compound semiconductor substrate 10, wherein the first dielectric regions 41 are located within neighbouring crossover region 33, and
First dielectric regions 41 overlap with least partially overlapped region 31, wherein the first of the upper surface of compound semiconductor substrate 10
Region other than dielectric regions 41 is defined as one second dielectric regions 42；A3: a first metal layer 61 is formed in the first circuit cloth
In the region of office 21；A4: the low dielectric bumps 50 being made of a dielectric materials are formed, wherein low dielectric bumps 50 are simultaneously
It is formed in the low dielectric in the first dielectric regions 41 and the second dielectric regions 42 (such as Fig. 1, Figure 1A), in the first dielectric regions 41
Convex block 50 is defined as one first dielectric bumps 51 (region of the thick frame of black), and the first dielectric bumps 51 have one first dielectric bumps
Thickness 53, the low dielectric bumps 50 in the second dielectric regions 42 are defined as one second dielectric bumps 52, the second dielectric bumps 52
Thickness 54 with one first dielectric bumps, wherein the thickness 54 of the second dielectric bumps is not more than the thickness of the first dielectric bumps
53, and the thickness 54 of at least partly the second dielectric bumps is less than the thickness 53 (such as Fig. 1, Figure 1A) of the first dielectric bumps；And A5:
A second metal layer 62 is formed in the region of second circuit layout 22.Whereby, the anti-of compound semiconductor integrated circuit 1 is improved
Wet ability.
Fig. 2A is please referred to, Fig. 2A is a kind of circuit arrangement method flow chart of compound semiconductor integrated circuit of the present invention.
The circuit arrangement method the following steps are included: (please refer to Figure 1B, Fig. 1 C, Fig. 1 F, Fig. 1 G, Fig. 1 J, Fig. 1 K, Fig. 1 N and
Fig. 1 O) B1: a compound semiconductor integrated circuit layout 1 delimited in the upper surface of a compound semiconductor substrate 10, wherein changing
Closing object semiconductor integrated circuit layout 1 includes one first circuit layout 21 and second circuit layout 22, wherein the first circuit
The region of layout 21 and the region of second circuit layout 22 overlap in an overlapping region 31, and one is defined as adjacent to crossover region 33
Surrounding adjacent regions 32 comprising overlapping region 31 and overlapping region 31；B2: one first dielectric regions, 41 (the thick frame of black delimited
Region) in the upper surface of compound semiconductor substrate 10, wherein the first dielectric regions 41 are located within neighbouring crossover region 33,
And first dielectric regions 41 overlap with least partially overlapped region 31, wherein the of the upper surface of compound semiconductor substrate 10
Region other than one dielectric regions 41 is defined as one second dielectric regions 42；B3: a first metal layer 61 is formed in the first circuit
In the region of layout 21；B4: one first dielectric bumps 50 being made of a dielectric materials are formed in the first dielectric regions 41
Interior (such as Figure 1B, Fig. 1 C, the region of the thick frame of black), the first dielectric bumps 51 have the thickness 53 of one first dielectric bumps；And
B5: a second metal layer 62 is formed in the region of second circuit layout 22.Whereby, compound semiconductor integrated circuit 1 is improved
Humidity-proof ability.
Please referring to Fig. 2 B and Fig. 2 C, Fig. 2 B and Fig. 2 C is respectively a kind of compound semiconductor integrated circuit of the present invention
The process step diagrammatic cross-section of the specific embodiment of circuit arrangement method.In one embodiment, it is wherein formed in A4 step low
Dielectric bumps 50 the following steps are included: (Fig. 2 B) simultaneously in forming one the in the first dielectric regions 41 and the second dielectric regions 42
One low dielectric layer 71, wherein the thickness of the first low dielectric layer 71 is equal to the thickness 54 of the second dielectric bumps；And (Fig. 2 C) in
One second low dielectric layer 72 is formed in one dielectric regions 41, wherein the thickness of the second low dielectric layer 72 is plus the second dielectric bumps
Thickness 54 is equal to the thickness 53 of the first dielectric bumps.Wherein form the material of the first low dielectric layer 71 and the second low dielectric layer 72
It is identical as the dielectric materials for forming low dielectric bumps 50.
It please refers to Fig. 2 B, Fig. 2 C and Fig. 2 D, Fig. 2 B, Fig. 2 C and Fig. 2 D is respectively a kind of compound semiconductor of the present invention
The process step diagrammatic cross-section of the specific embodiment of the circuit arrangement method of integrated circuit.In another embodiment, wherein A4
The step of in form low dielectric bumps 50 the following steps are included: (Fig. 2 B) simultaneously in the first dielectric regions 41 and the second dielectric regime
One first low dielectric layer 71 is formed in domain 42, wherein the thickness of the first low dielectric layer 71 is equal to the thickness 54 of the second dielectric bumps；
(Fig. 2 D) while in forming one second low dielectric layer 72 in the first dielectric regions 41 and the second dielectric regions 42, wherein first is low
The thickness (equal to the thickness 54 of the second dielectric bumps) of dielectric layer 71 is equal to the first dielectric plus the thickness of the second low dielectric layer 72
The thickness 53 of convex block；And (Fig. 2 C) removes the second low dielectric in the second dielectric regions 42 in a manner of exposure development or etching
Layer 72, so that only remaining the first low dielectric layer 71 in the second dielectric regions 42, and the first low dielectric layer in the second dielectric regions 42
71 thickness 54 with a thickness of the second dielectric bumps.Wherein form the material of the first low dielectric layer 71 and the second low dielectric layer 72
It is identical as the dielectric materials for forming low dielectric bumps 50.
Please referring to Fig. 2 E and Fig. 2 F, Fig. 2 E and Fig. 2 F is respectively a kind of compound semiconductor integrated circuit of the present invention
The process step diagrammatic cross-section of the specific embodiment of circuit arrangement method.In another embodiment, wherein A4 the step of in shape
At low dielectric bumps 50 the following steps are included: (Fig. 2 E) is formed in the first dielectric regions 41 and the second dielectric regions 42 simultaneously
Low dielectric bumps 50, wherein the thickness 55 of low dielectric bumps 50 is equal to the thickness 53 of the first dielectric bumps；And (Fig. 2 F) exposure
Develop or etches the low dielectric bumps 50 in the second dielectric regions 42, so that the low dielectric bumps 50 in the first dielectric regions 41
With a thickness of the thickness 53 of the first dielectric bumps, and the low dielectric bumps 50 in the second dielectric regions 42 is convex with a thickness of the second dielectric
The thickness 54 of block.
Fig. 2 E and Fig. 2 F is please referred to, is respectively a kind of circuit layout side of compound semiconductor integrated circuit of the present invention
The process step diagrammatic cross-section of the specific embodiment of method.In another embodiment, it is convex that low dielectric is wherein formed in the step of A4
Block 50 the following steps are included: (Fig. 2 E) simultaneously in forming low dielectric bumps in the first dielectric regions 41 and the second dielectric regions 42
50, wherein the thickness 55 of low dielectric bumps 50 is greater than the thickness 53 of the first dielectric bumps；And (Fig. 2 F) exposure development or etching
Low dielectric bumps 50 in first dielectric regions 41 and the second dielectric regions 42, so that the low dielectric in the first dielectric regions 41
The thickness 53 with a thickness of the first dielectric bumps of convex block 50, and the low dielectric bumps 50 in the second dielectric regions 42 with a thickness of
The thickness 54 of two dielectric bumps.
Please referring to Fig. 2 E and Fig. 2 G, Fig. 2 E and Fig. 2 G is respectively a kind of compound semiconductor integrated circuit of the present invention
The process step diagrammatic cross-section of the specific embodiment of circuit arrangement method.In another embodiment, wherein B4 the step of in shape
At the first dielectric bumps 51 the following steps are included: (Fig. 2 E) is simultaneously in shape in the first dielectric regions 41 and the second dielectric regions 42
At a low dielectric bumps 50, wherein the thickness 55 of low dielectric bumps 50 is equal to the thickness 53 of the first dielectric bumps；And (Fig. 2 G)
Exposure development or etching remove the low dielectric bumps 50 in the second dielectric regions 42, so that the low dielectric in the first dielectric regions 41
The thickness 53 with a thickness of the first dielectric bumps of convex block 50, and the low dielectric bumps 50 in the second dielectric regions 42 with a thickness of
Zero.
Please referring to Fig. 2 E and Fig. 2 G, Fig. 2 E and Fig. 2 G is respectively a kind of compound semiconductor integrated circuit of the present invention
The process step diagrammatic cross-section of the specific embodiment of circuit arrangement method.In another embodiment, wherein B4 the step of in shape
At the first dielectric bumps 51 the following steps are included: (Fig. 2 E) is simultaneously in shape in the first dielectric regions 41 and the second dielectric regions 42
At a low dielectric bumps 50, wherein the thickness 55 of low dielectric bumps 50 is greater than the thickness 53 of the first dielectric bumps；And (Fig. 2 G)
Low dielectric bumps 50 in the first dielectric regions 41 of exposure development or etching, and exposure development or etching remove the second dielectric regions
Low dielectric bumps 50 in 42, so that the thickness with a thickness of the first dielectric bumps of the low dielectric bumps 50 in the first dielectric regions 41
Degree 53, and the low dielectric bumps 50 in the second dielectric regions 42 with a thickness of zero.
Fig. 2 H is please referred to, Fig. 2 H is a kind of another tool of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
The sectional view of body embodiment.Its primary structure is roughly the same with Fig. 1 and embodiment shown in figure 1A, but, wherein further including one
Lower insulating layer 75 is formed on compound semiconductor substrate 10, and lower insulating layer 75 be formed under the first metal layer 61 and
Under low dielectric bumps 50.The material for wherein constituting lower insulating layer 75 includes at least one for being selected from following group: silicon nitride
(SiN) and silica (SiO2).Its main method is roughly the same with embodiment shown in Fig. 2, but, wherein in the A3 the step of it
Before further include the steps that one forms insulating layer 75 so that lower insulating layer 75 is formed on compound semiconductor substrate 10,
And lower insulating layer 75 is formed under the first metal layer 61 and under low dielectric bumps 50.In another embodiment, may include
The structure (not shown) of insulating layer 75 under plural layer.
Fig. 2 I is please referred to, Fig. 2 I is a kind of another tool of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
The sectional view of body embodiment.Its primary structure is roughly the same with embodiment shown in Fig. 2 H, but, wherein 50 shapes of low dielectric bumps
At in the first dielectric regions 41, and low dielectric bumps 50 are had no in the second dielectric regions 42, therefore in this embodiment, only
There are the first dielectric bumps 51, and without the second dielectric bumps 52.It in another embodiment, may include the knot of insulating layer 75 under plural layer
Structure (not shown).Its main method is roughly the same with embodiment shown in Fig. 2A, but, wherein also being wrapped before in the step of B3
The step of including one and form insulating layer 75 so that lower insulating layer 75 is formed on compound semiconductor substrate 10, and it is lower absolutely
Edge layer 75 be formed under the first metal layer 61 and the first dielectric bumps 51 under.
Fig. 2 J is please referred to, Fig. 2 J is a kind of another tool of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
The sectional view of body embodiment.Its primary structure is roughly the same with Fig. 1 and embodiment shown in figure 1A, but, wherein further including one
Upper insulating layer 76 is formed on compound semiconductor substrate 10 and on the first metal layer 61, and upper insulating layer 76 is formed in
Under low dielectric bumps 50.The material for wherein constituting upper insulating layer 76 includes at least one for being selected from following group: silicon nitride
(SiN) and silica (SiO2).Its main method is roughly the same with embodiment shown in Fig. 2, but, wherein in the A3 the step of with
And further include the steps that insulating layer 76 in a formation one between the step of A4, so that upper insulating layer 76 is formed in compound semiconductor
On substrate 10 and on the first metal layer 61, and upper insulating layer 76 is formed under low dielectric bumps 50.In another implementation
It may include the structure (not shown) of insulating layer 76 in plural layer in example.
Fig. 2 K is please referred to, Fig. 2 K is a kind of another tool of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
The sectional view of body embodiment.Its primary structure is roughly the same with embodiment shown in Fig. 2 J, but, wherein 50 shapes of low dielectric bumps
At in the first dielectric regions 41, and low dielectric bumps 50 are had no in the second dielectric regions 42, therefore in this embodiment, only
There are the first dielectric bumps 51, and without the second dielectric bumps 52.It in another embodiment, may include the knot of insulating layer 76 in plural layer
Structure (not shown).Its main method is roughly the same with embodiment shown in Fig. 2A, but, wherein in the B3 the step of and B4
Further include the steps that insulating layer 76 in a formation one between step, so that upper insulating layer 76 is formed in compound semiconductor substrate 10
On and the first metal layer 61 on, and upper insulating layer 76 is formed under the first dielectric bumps 51.
Fig. 2 L is please referred to, Fig. 2 L is a kind of another tool of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
The sectional view of body embodiment.Its primary structure is roughly the same with embodiment shown in Fig. 2 J, but, wherein further including insulating layer
75 are formed on compound semiconductor substrate 10, and lower insulating layer 75 is formed under the first metal layer 61 and low dielectric is convex
Under block 50.The material for wherein constituting lower insulating layer 75 includes at least one for being selected from following group: silicon nitride (SiN) and oxygen
SiClx (SiO2).Its main method is roughly the same with the method for embodiment shown in Fig. 2 J is formed, but, wherein in the A3 the step of it
Before further include the steps that one forms insulating layer 75 so that lower insulating layer 75 is formed on compound semiconductor substrate 10,
And lower insulating layer 75 is formed under the first metal layer 61 and under low dielectric bumps 50.In another embodiment, may include
The structure (not shown) of insulating layer 76 in plural layer.It in another embodiment, may include the knot of insulating layer 75 under plural layer
Structure (not shown).In another embodiment, can structure (not shown) simultaneously comprising insulating layer 76 in plural layer with
And under plural layer insulating layer 75 structure (not shown).
Fig. 2 M is please referred to, Fig. 2 M is a kind of another tool of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
The sectional view of body embodiment.Its primary structure is roughly the same with embodiment shown in Fig. 2 L, but, wherein 50 shapes of low dielectric bumps
At in the first dielectric regions 41, and low dielectric bumps 50 are had no in the second dielectric regions 42, therefore in this embodiment, only
There are the first dielectric bumps 51, and without the second dielectric bumps 52.It in another embodiment, may include the knot of insulating layer 76 in plural layer
Structure (not shown).It in another embodiment, may include the structure (not shown) of insulating layer 75 under plural layer.Another
It can simultaneously include the knot of insulating layer 75 under the structure (not shown) and plural layer of insulating layer 76 in plural layer in embodiment
Structure (not shown).Its main method is roughly the same with the method for embodiment shown in Fig. 2 K is formed, but, wherein in the step of B3
Further include the steps that one forms insulating layer 75 before rapid so that lower insulating layer 75 be formed in compound semiconductor substrate 10 it
On, and lower insulating layer 75 be formed under the first metal layer 61 and the first dielectric bumps 51 under.
Referring to Fig. 3, Fig. 3 is an a kind of specific reality of circuit arrangement method of compound semiconductor integrated circuit of the present invention
Apply the schematic top plan view of example.On the chip of a compound semiconductor integrated circuit 1, at the same it is (black in one first dielectric regions 41
The region of the thick frame of color) and one second dielectric regions 42 in form a low dielectric bumps 50, wherein being formed in the first dielectric regime
Low dielectric bumps 50 in domain 41 are one first dielectric bumps 51 (region of the thick frame of black), are formed in the second dielectric regions 42
Low dielectric bumps 50 be one second dielectric bumps 52, wherein the first dielectric bumps 51 have one first dielectric bumps thickness
53, the second dielectric bumps 52 have the thickness 54 of one second dielectric bumps, and the thickness of wherein at least the second dielectric bumps of part
54 less than the first dielectric bumps thickness 53.In this embodiment, area shared by the second dielectric bumps 52 is situated between relative to first
The ratio of area shared by electric convex block 51 is very big, and therefore, the thickness of the second dielectric bumps 52 is to compound semiconductor integrated circuit 1
Humidity-proof ability have significant impact.When at least partly the second dielectric bumps thickness 54 less than the first dielectric bumps thickness 53
90% or less when, the humidity-proof ability of compound semiconductor integrated circuit 1 can be remarkably reinforced.And the thickness of the second dielectric bumps 52
It spends smaller, then has the effect being more obvious to the enhancing of the humidity-proof ability of compound semiconductor integrated circuit 1.
Fig. 3 A is please referred to, Fig. 3 A is a kind of another tool of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
The schematic top plan view of body embodiment.Its primary structure is roughly the same with embodiment shown in Fig. 3, but, wherein in a compound half
On the chip of conductor integrated circuit 1, low dielectric bumps only are formd in one first dielectric regions 41 (region of the thick frame of black)
50, and the low dielectric bumps for having no low dielectric bumps 50 in the second dielectric regions 42, and being formed in the first dielectric regions 41
50 be one first dielectric bumps 51 (region of the thick frame of black), wherein the first dielectric bumps 51 have the thickness of one first dielectric bumps
Spend 53 (not shown).Therefore in this embodiment, only the first dielectric bumps 51, and without the second dielectric bumps 52.Due to
Embodiment in Fig. 3 A, there is no the second dielectric bumps 52, therefore the first metal layer (not shown) is removed in this embodiment
Outside the region that is covered by the first dielectric bumps 51, there is no by low dielectric for remaining the first metal layer (not shown)
Convex block 50 is covered.This embodiment is also one of highly preferred embodiment of the present invention, is not had due to there was only the first dielectric bumps 51
There are the second dielectric bumps 52, has splendid effect to the humidity-proof ability of enhancing compound semiconductor integrated circuit 1.
Fig. 3 B is please referred to, Fig. 3 B depicts the schematic diagram of the local circuit of Fig. 3 A.One compound semiconductor integrated circuit 1 packet
It includes and forms multiple heteroj unction bipolar transistor (Heterojunction on a compound semiconductor substrate 10
Bipolar Transistor, abbreviation HBT) 80.One the first metal layer 61 is formed on compound semiconductor substrate 10.First
Metal layer 61 contains the first metal layer firstth area 611 and secondth area of the first metal layer 612, wherein the first metal layer
One area 611 and the secondth area of the first metal layer 612 are the blocks being not connected with that is separated from each other.One first dielectric bumps 51 are formed in
In one first dielectric regions 41 (region of the thick frame of black).In this embodiment, the first dielectric bumps of multiple blocks are contained
51 (regions of the thick frame of black), and the second dielectric bumps 52 are then had no in one second dielectric regions 42.First dielectric bumps 51
It is formed on the first metal layer 61.One second metal layer 62 is formed on the first dielectric bumps 51 and compound semiconductor
On substrate 10.Second metal layer 62 contains second metal layer firstth area 621 and secondth area of second metal layer 622,
Wherein the firstth area of second metal layer 621 and the secondth area of second metal layer 622 are the blocks being not connected with that is separated from each other.Please simultaneously
It is the diagrammatic cross-section of the vertical cross-section of b-b ' hatching in Fig. 3 B refering to Fig. 3 C.Multiple heterojunctions are contained in Fig. 3 B
Bipolar transistor 80, wherein each heteroj unction bipolar transistor 80 contains an emitter-base bandgap grading 81 (Emitter), a base stage
82 (Base) and a collector 83 (Collector).Wherein the firstth area of the first metal layer 611 is formed in heteroj unction bipolar crystalline substance
On the emitter-base bandgap grading 81 of body pipe 80, it is electrical connected with emitter-base bandgap grading 81.The secondth area of the first metal layer 612 is formed in heteroj unction bipolar crystalline substance
(not shown) on the base stage 82 of body pipe 80, is electrical connected with base stage 82.First dielectric bumps 51 are formed in the first metal
On the firstth area of floor 611.The firstth area of second metal layer 621 be formed on the collector 83 of heteroj unction bipolar transistor 80 with
And first on dielectric bumps 51, are electrical connected with collector 83.By the first dielectric bumps 51 by the first metal of different potentials
Floor 61 (the first area 611 of the first metal layer) and second metal layer 62 (the first area 621 of second metal layer) isolation.
Fig. 3 D is please referred to, Fig. 3 D is a kind of another reality of the circuit arrangement method of compound semiconductor integrated circuit of the present invention
Apply the diagrammatic cross-section of the cross-section structure of example.In Fig. 3 D, it is double that a heterojunction is formd on a compound semiconductor substrate 10
Polar transistor 80 (HBT), heteroj unction bipolar transistor 80 contain an emitter-base bandgap grading 81 (Emitter), a base stage 82
(Base) and a collector 83 (Collector).Wherein a first metal layer 61 is formed in heteroj unction bipolar transistor 80
Collector 83 on, be electrical connected with collector 83.One first dielectric bumps 51 are formed on the first metal layer 61.One second gold medal
Belong to layer 62 to be formed on the emitter-base bandgap grading 81 of heteroj unction bipolar transistor 80, on the first dielectric bumps 51 and compound half
On conductor substrate 10, and it is electrical connected with emitter-base bandgap grading 81.By the first dielectric bumps 51 by the first metal layer 61 of different potentials
And second metal layer 62 is isolated.
Referring to Fig. 4, Fig. 4 is an a kind of specific reality of circuit arrangement method of compound semiconductor integrated circuit of the present invention
Apply the local circuit schematic layout pattern of example.It is the partial circuit of the embodiment corresponded in Fig. 4 please refer to Fig. 4 A
Figure.One compound semiconductor integrated circuit 1 be included on a compound semiconductor substrate (not shown) formed it is multiple
Heteroj unction bipolar transistor 84 (HBT) and a bias circuit heteroj unction bipolar transistor 88.Wherein each is different
Matter unction bipolar transistors 84 have separately included an emitter-base bandgap grading 85 (Emitter), a base stage 86 (Base) and a collector 87
(Collector).Bias circuit heteroj unction bipolar transistor 88 contains an emitter-base bandgap grading 89 (Emitter), a base stage 90
(Base) and a collector 91 (Collector).One the first metal layer 61 is formed in compound semiconductor substrate and (does not show in figure
Show) on.The first metal layer 61 contains the first metal layer firstth area 611, secondth area of the first metal layer 612 and one
One metal layer third area 613, wherein the firstth area of the first metal layer 611, the secondth area of the first metal layer 612 and the first metal layer
Three areas 613 are the blocks being not connected with that is separated from each other.The firstth area of the first metal layer 611 and heteroj unction bipolar transistor 84
Emitter-base bandgap grading 85 is electrical connected.The secondth area of the first metal layer 612 and the base stage 86 of heteroj unction bipolar transistor 84 are electrical connected.The
One metal layer third area 613 and the base stage 90 of bias circuit heteroj unction bipolar transistor 88 are electrical connected.One first dielectric
Convex block 51 (region of the thick frame of black) is formed in one first dielectric regions 41, wherein the first dielectric bumps 51 include two first
The firstth area of dielectric bumps 511, one first the secondth area of dielectric bumps 512, one first dielectric bumps third area 513 and multiple first
Other areas 514 of dielectric bumps.In this embodiment, the region other than the first dielectric regions 41 is one second dielectric regions 42, the
The second dielectric bumps 52 are had no in two dielectric regions 42.First dielectric bumps 51 are formed on the first metal layer 61.One second
Metal layer 62 is formed on the first dielectric bumps 51 and on compound semiconductor substrate 10.Second metal layer 62 contains
One second metal layer the firstth area 621 and secondth area of second metal layer 622, wherein the firstth area of second metal layer 621 and
Two the secondth area of metal layer 622 are the blocks being not connected with that is separated from each other.The firstth area of second metal layer 621 and heteroj unction bipolar
The collector 87 of transistor 84 is electrical connected.The secondth area of second metal layer 622 and bias circuit heteroj unction bipolar transistor 88
Collector 91 be electrical connected.
The firstth area of two overlapping regions 311 in Fig. 4 and Fig. 4 A is the first metal layer the firstth area 611 and the second gold medal
Belong to the equitant region in the firstth area of floor 621.The firstth area of the firstth area of the first metal layer 611 and second metal layer of different potentials
621 form bridging by first the firstth area of dielectric bumps 511 (region of the thick frame of black), and the firstth area of the first metal layer is isolated whereby
611 and the firstth area of second metal layer 621.However around the firstth area of overlapping region 311 and the firstth area of overlapping region 311
The size of an impedance (Impedance) for the compound semiconductor integrated circuit 1 of adjacent domain is to will receive the first dielectric bumps
One dielectric of the dielectric materials of thickness, area and the shape and first the firstth area of dielectric bumps 511 of formation in the first area 511 is normal
Number etc. factor is influenced.Thus the present inventor also develop, if can greatly utilize the firstth area of overlapping region 311 with
And the impedance of the compound semiconductor integrated circuit 1 of the surrounding adjacent regions in the firstth area of overlapping region 311 will receive the first dielectric
The influence in the firstth area of convex block 511, come be designed adjustment first the firstth area of dielectric bumps 511 thickness, area and shape and
Selection forms the dielectric constant of dielectric materials in first the firstth area of dielectric bumps 511 etc. mode, to produce required size
The impedance (compound semiconductor in the firstth area of overlapping region 311 and the surrounding adjacent regions in the firstth area of overlapping region 311
The impedance of integrated circuit 1), it can will promote whereby the efficiency of compound semiconductor integrated circuit 1.Therefore, a kind of chemical combination of the present invention
The circuit arrangement method of object semiconductor integrated circuit, wherein formed the first dielectric bumps 51 include the steps that it is following: according to adjacent
Size needed for one impedance of the compound semiconductor integrated circuit 1 near nearly crossover region 33, decision correspond to neighbouring bridging
Thickness, area and the shape of first dielectric bumps 51 in region 33 and a dielectric constant of dielectric materials, to form first
Dielectric bumps 51 promote the efficiency of compound semiconductor integrated circuit 1 whereby.
It is heterogeneous with heteroj unction bipolar transistor 84 and bias circuit respectively in the embodiment of Fig. 4 and Fig. 4 A
Unction bipolar transistors 88 are the embodiment of power amplifier (main power amplifier) and bias circuit power amplifier.?
In other embodiments, power amplifier (main power amplifier) and bias circuit power amplifier are not limited to heterojunction
Bipolar transistor can also be bipolar transistor, a field-effect transistor (Field Effect Transistor, abbreviation
) or the power amplifier of other forms FET.In addition, as the difference of Fig. 3 C and Fig. 3 D, in the implementation of Fig. 4 and Fig. 4 A
In example, the emitter-base bandgap grading 85 and collector 87 of heteroj unction bipolar transistor 84 respectively with the (the first metal layer the of the first metal layer 61
One area 611) and second metal layer 62 (the first area 621 of second metal layer) be electrical connected；And in another embodiment, it is heterogeneous to connect
The emitter-base bandgap grading 85 and collector 87 of face bipolar transistor 84 can respectively with second metal layer 62 and the electrical phase of the first metal layer 61
Even.Similarly, in the embodiment of Fig. 4 and Fig. 4 A, the base stage 86 and bias circuit of heteroj unction bipolar transistor 84
The collector 91 of heteroj unction bipolar transistor 88 respectively with the first metal layer 61 (the second area 612 of the first metal layer) and second
Metal layer 62 (the second area 622 of second metal layer) is electrical connected；And in another embodiment, heteroj unction bipolar transistor 84
Base stage 86 and bias circuit heteroj unction bipolar transistor 88 collector 91 can respectively with second metal layer 62 and
One metal layer 61 is electrical connected.
In the embodiment of Fig. 4 and Fig. 4 A, because of the firstth area of the first metal layer 611 and heteroj unction bipolar transistor 84
Emitter-base bandgap grading 85 be electrical connected, and the electrical phase of collector 87 of the firstth area of second metal layer 621 and heteroj unction bipolar transistor 84
Even, therefore it is integrated in the compound semiconductor of the firstth area of overlapping region 311 and the surrounding adjacent regions in the firstth area of overlapping region 311
The impedance of circuit 1 is the output impedance between the collector 87 and emitter-base bandgap grading 85 of heteroj unction bipolar transistor 84.Thus, if energy
Greatly utilizing the output impedance between the collector 87 and emitter-base bandgap grading 85 of heteroj unction bipolar transistor 84, to will receive the first dielectric convex
The influence in the firstth area of block 511 (region of the thick frame of black), come be designed adjustment first the firstth area of dielectric bumps 511 thickness,
Area and shape and selection form the dielectric constant of dielectric materials in first the firstth area of dielectric bumps 511 etc. mode, with
The output impedance between the collector 87 and emitter-base bandgap grading 85 of the heteroj unction bipolar transistor 84 of required size is produced, can be mentioned whereby
Rise the efficiency of the compound semiconductor integrated circuit 1.
Therefore, a kind of circuit arrangement method of compound semiconductor integrated circuit of the present invention, include thes steps that following: drawing
A fixed power amplifier is in the layout of in compound semiconductor integrated circuit layout 1；A power amplifier is formed in power amplifier
In the region of layout, intermediate power amplifier includes a first end, a second end and a third end, wherein first end and second
One of end is an output end of power amplifier.Wherein first end and the first metal layer 61 and second metal layer 62
One of them is electrical connected, and second end is electrical connected with the first metal layer 61 and the wherein another of second metal layer 62, makes
The first end and second end for obtaining power amplifier are formed by the first dielectric bumps 51 is isolated；And according to neighbouring crossover region
Size needed for an output impedance between the first end and second end of power amplifier near 33, decision correspond to it is neighbouring across
Thickness, area and the shape of first dielectric bumps 51 in region 33 and a dielectric constant of dielectric materials are connect, to form
One dielectric bumps 51 promote the efficiency of compound semiconductor integrated circuit 1 whereby.In one embodiment, intermediate power amplifier
For bipolar transistor or a heteroj unction bipolar transistor, first end is a collector, and second end is an emitter-base bandgap grading, third end
For a base stage, wherein the output impedance is the impedance between the collector and emitter-base bandgap grading of power amplifier.In another embodiment, wherein
Power amplifier is a field-effect transistor, and first end is a drain electrode, and second end is a source electrode, and third end is a grid, wherein should
Output impedance is the impedance between the drain electrode and source electrode of power amplifier.
In Fig. 4 and Fig. 4 A, heteroj unction bipolar transistor 84 is a main power amplifier, and bias circuit is heterogeneous
Unction bipolar transistors 88 are a bias circuit power amplifier.Wherein the secondth area of an overlapping region 312 is the first metal layer
The equitant region in second area 612 and the secondth area of second metal layer 622.The secondth area of the first metal layer 612 of different potentials with
And the secondth area of second metal layer 622 by first the firstth area of dielectric bumps 512 (region of the thick frame of black) formed bridging, whereby every
From the secondth area of the first metal layer 612 and the secondth area of second metal layer 622.However in the secondth area of overlapping region 312 and overlapping
The size of one impedance of the compound semiconductor integrated circuit 1 of the surrounding adjacent regions in the secondth area of region 312 is to will receive first
The dielectric materials of thickness, area and the shape and first the firstth area of dielectric bumps 512 of formation in the firstth area of dielectric bumps 512
One dielectric constant etc. factor is influenced.Because of the base stage in the secondth area of the first metal layer 612 and heteroj unction bipolar transistor 84
86 are electrical connected, and the collector 91 of the secondth area of second metal layer 622 and bias circuit heteroj unction bipolar transistor 88 is electrically
It is connected, therefore the compound semiconductor collection in the secondth area of overlapping region 312 and the surrounding adjacent regions in the secondth area of overlapping region 312
Impedance at circuit 1 is the base stage 86 and bias circuit heteroj unction bipolar transistor of heteroj unction bipolar transistor 84
Impedance between 88 collector 91, also an as input impedance of heteroj unction bipolar transistor 84.Thus, if can greatly utilize
The input impedance of heteroj unction bipolar transistor 84 will receive the influence in first the firstth area of dielectric bumps 512, to be designed
Thickness, area and the shape and selection for adjusting first the firstth area of dielectric bumps 512 form first the firstth area of dielectric bumps 512
Dielectric constant of dielectric materials etc. mode, to produce an input of the heteroj unction bipolar transistor 84 of required size
Impedance can promote the efficiency of the compound semiconductor integrated circuit 1 whereby.
Therefore, a kind of circuit arrangement method of compound semiconductor integrated circuit of the present invention, it is further comprising the steps of: to delimit
One main power amplifier layout and a bias circuit power amplifier are in the layout of in compound semiconductor integrated circuit layout 1；
A main power amplifier is formed in the region that main power amplifier is laid out, wherein main power amplifier includes a main power amplification
Device first end, a main power amplifier second end and a main power amplifier third end, wherein main power amplifier third end
For an input terminal of main power amplifier；A bias circuit power amplifier is formed in the area that bias circuit power amplifier is laid out
In domain, wherein bias circuit power amplifier includes a bias circuit power amplifier first end, a bias circuit power amplification
Device second end and a bias circuit power amplifier third end, wherein bias circuit power amplifier first end and the first metal
Layer one of 61 and second metal layer 62 are electrical connected, main power amplifier third end and the first metal layer 61 and the
The wherein another of two metal layers 62 is electrical connected, so that bias circuit power amplifier first end and main power amplifier
Three ends form isolation by the first dielectric bumps 51；And according to the bias circuit power amplifier near neighbouring crossover region 33
The required size of an impedance between first end and main power amplifier third end determines to correspond to neighbouring crossover region 33
Thickness, area and the shape of first dielectric bumps 51 and a dielectric constant of dielectric materials, to form the first dielectric bumps
51, the efficiency of compound semiconductor integrated circuit 1 is promoted whereby, and wherein the impedance is an input impedance of main power amplifier.
In one embodiment, wherein main power amplifier and bias circuit power amplifier are that bipolar transistor or one heterogeneous connect
Face bipolar transistor, main power amplifier first end are a main power amplifier collector, and main power amplifier second end is one
Main power amplifier emitter-base bandgap grading, main power amplifier third end are a main power amplifier base stage, bias circuit power amplifier the
One end is a bias circuit power amplifier collector, and bias circuit power amplifier second end is a bias circuit power amplifier
Emitter-base bandgap grading, bias circuit power amplifier third end are a bias circuit power amplifier base stage, and wherein the input impedance is bias
Impedance between circuit power amplifier collector and main power amplifier base stage.In another embodiment, wherein main power amplification
Device and bias circuit power amplifier are a field-effect transistor, and main power amplifier first end is a main power amplifier leakage
Pole, main power amplifier second end are a main power amplifier source electrode, and main power amplifier third end is a main power amplifier
Grid, bias circuit power amplifier first end are bias circuit power amplifier drain electrode, bias circuit power amplifier the
Two ends are a bias circuit power amplifier source electrode, and bias circuit power amplifier third end is a bias circuit power amplifier
Grid, wherein the input impedance is the impedance between the drain electrode of bias circuit power amplifier and main power amplifier grid.
In Fig. 4 and Fig. 4 A, an overlapping region third area 313 is the first metal layer third area 613 and the second metal
The equitant region in the secondth area of floor 622.The first metal layer third area 613 and the secondth area of second metal layer 622 of different potentials
It is formed and is bridged by the first dielectric bumps third area 513 (region of the thick frame of black), the first metal layer third area 613 is isolated whereby
And the secondth area of second metal layer 622.However it is adjacent around overlapping region third area 313 and overlapping region third area 313
The size of one impedance of the compound semiconductor integrated circuit 1 of near field is to will receive the thickness in the first dielectric bumps third area 513
Degree, area and shape and the dielectric constant of dielectric materials for forming the first dielectric bumps third area 513 etc. factor institute
It influences.Because the first metal layer third area 613 and the base stage 90 of bias circuit heteroj unction bipolar transistor 88 are electrical connected, and
The secondth area of second metal layer 622 and the collector 91 of bias circuit heteroj unction bipolar transistor 88 are electrical connected, therefore are being overlapped
The impedance of the compound semiconductor integrated circuit 1 of the surrounding adjacent regions in region third area 313 and overlapping region third area 313
For the impedance between the base stage 90 and collector 91 of bias circuit heteroj unction bipolar transistor 88, also as bias circuit is heterogeneous
One input impedance of unction bipolar transistors 88.Thus, if bias circuit heteroj unction bipolar transistor can be greatly utilized
88 input impedance will receive the influence in the first dielectric bumps third area 513, to be designed the first dielectric bumps third of adjustment
Thickness, area and the shape in area 513 and selection form the dielectric constant of the dielectric materials in the first dielectric bumps third area 513
Etc. mode can be whereby to produce an input impedance of the bias circuit heteroj unction bipolar transistor 88 of required size
Promote the efficiency of the compound semiconductor integrated circuit 1.
Therefore, a kind of circuit arrangement method of compound semiconductor integrated circuit of the present invention, it is further comprising the steps of: to delimit
One bias circuit power amplifier is in the layout of in compound semiconductor integrated circuit layout 1；Form a bias circuit power amplification
Device is in the region that bias circuit power amplifier is laid out, and wherein bias circuit power amplifier includes that a bias circuit power is put
Big device first end, a bias circuit power amplifier second end and a bias circuit power amplifier third end, wherein bias
One of circuit power amplifier first end and bias circuit power amplifier third end are bias circuit power amplification
One input terminal of device.Wherein bias circuit power amplifier first end and the first metal layer 61 and second metal layer 62 be wherein
One of be electrical connected, bias circuit power amplifier third end and the first metal layer 61 and second metal layer 62 it is wherein another
One is electrical connected, so that bias circuit power amplifier first end and bias circuit power amplifier third end are situated between by first
Electric convex block 51 forms isolation；And according to the bias circuit power amplifier first end and bias near neighbouring crossover region 33
The required size of an input impedance between circuit power amplifier third end determines to correspond to the first of neighbouring crossover region 33
Thickness, area and the shape of dielectric bumps 51 and a dielectric constant of dielectric materials, to form the first dielectric bumps 51, by
This promotes the efficiency of compound semiconductor integrated circuit 1.In one embodiment, wherein bias circuit power amplifier is one bipolar
Property a transistor or heteroj unction bipolar transistor, bias circuit power amplifier first end is a collector, bias circuit function
Rate amplifier second end is an emitter-base bandgap grading, and bias circuit power amplifier third end is a base stage, and wherein the input impedance is bias
Impedance between the collector and base stage of circuit power amplifier.In another embodiment, wherein bias circuit power amplifier is
One field-effect transistor, bias circuit power amplifier first end are a drain electrode, and bias circuit power amplifier second end is a source
Pole, bias circuit power amplifier third end are a grid, and wherein the input impedance is the drain electrode of bias circuit power amplifier
And the impedance between grid.
Please refer to Fig. 4, Fig. 4 A, Fig. 4 B and Fig. 4 C, wherein Fig. 4 B is that the vertical of c-c ' hatching in Fig. 4 is cut
The diagrammatic cross-section in face；Fig. 4 C is the partial enlarged view in the region of V box in Fig. 4 B.Wherein in Fig. 4 B close to V box region,
For the region (namely region above c-c ' hatching) in Fig. 4 close to the c of c-c ' hatching.First metal in Fig. 4 B
Floor 61 includes be separated from each other the firstth area of the first metal layer 611 being not connected with, the first metal layer the secondth area 612 and the first metal
613 3, floor third area block.Second metal layer 62 include be separated from each other the firstth area of second metal layer 621 being not connected with and
622 two, the secondth area of second metal layer block.Wherein the firstth area of the first metal layer 611 of different potentials and second metal layer
One area 621 forms bridging by first the firstth area of dielectric bumps 511, and the firstth area of the first metal layer 611 and second is isolated whereby
The firstth area of metal layer 621.The first metal layer third area 613 and the secondth area of second metal layer 622 of different potentials pass through first
Dielectric bumps third area 513 forms bridging, and the first metal layer third area 613 and the secondth area of second metal layer 622 are isolated whereby.
In Fig. 4 B and Fig. 4 C, once insulating layer 75 is formed on compound semiconductor substrate 10；The first metal layer 61 (includes first
The firstth area of metal layer 611, the secondth area of the first metal layer 612 and the first metal layer third area 613) be formed in insulating layer 75 it
On；Insulating layer 76 is formed on the first metal layer 61 and on compound semiconductor substrate 10 on one；First dielectric bumps
51 (including first dielectric bumps the firstth area 511 and the first dielectric bumps third area 513) are formed in the first dielectric regions 41
On on insulating layer 76；Second metal layer 62 (including the second area 622 of the firstth area of second metal layer 621 and second metal layer)
It is formed on the first dielectric bumps 51 and on upper insulating layer 76；One protective layer 77 is formed on second metal layer 62,
On first dielectric bumps 51 and on upper insulating layer 76.
A kind of circuit arrangement method of compound semiconductor integrated circuit (embodiment as shown in Figure 2) of the present invention, wherein
Further include the steps that an a formation at least protective layer 77 on the compound semiconductor integrated circuit 1 later in the step of A5.
In one embodiment, wherein protective layer 77 is formed on second metal layer 62.In another embodiment, protective layer 77 is also formed
On the second dielectric bumps 52.In another embodiment, protective layer 77 is also formed on the first dielectric bumps 51.Another
In embodiment, protective layer 77 is also formed on the first metal layer 61.In another embodiment, protective layer 77 is also formed in chemical combination
On object semiconductor substrate 10.The material for wherein constituting protective layer 77 includes at least one for being selected from following group: polyphenyl is simultaneously disliked
Azoles (polybenzoxazole, abbreviation PBO), silicon nitride (SiN) and silica (SiO2)。
A kind of circuit arrangement method of compound semiconductor integrated circuit (embodiment as shown in Figure 2 A) of the present invention, wherein
Further include the steps that an a formation at least protective layer 77 on the compound semiconductor integrated circuit 1 later in the step of B5.
In one embodiment, wherein protective layer 77 is formed on second metal layer 62.In another embodiment, protective layer 77 is also formed
On the first dielectric bumps 51.In another embodiment, protective layer 77 is also formed on the first metal layer 61.Another real
It applies in example, protective layer 77 is also formed on compound semiconductor substrate 10.The material for wherein constituting protective layer 77 includes being selected from
At least one of following group: polybenzoxazoles (polybenzoxazole, abbreviation PBO), silicon nitride (SiN) and silica
(SiO2)。
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (38)
1. a kind of circuit arrangement method of compound semiconductor integrated circuit, which comprises the following steps:
A1: a compound semiconductor integrated circuit layout delimited in the upper surface of a compound semiconductor substrate, wherein describedization
Closing object semiconductor integrated circuit layout includes that one first circuit layout and a second circuit are laid out, wherein the first circuit cloth
The region that the region of office is laid out with the second circuit overlaps in an overlapping region, and one is defined as adjacent to crossover region comprising institute
State the surrounding adjacent regions of overlapping region and the overlapping region；
A2: one first dielectric regions delimited in the upper surface of the compound semiconductor substrate, wherein first dielectric regions
Within the neighbouring crossover region, and first dielectric regions overlap at least partly described overlapping region, wherein
Region other than first dielectric regions of the upper surface of the compound semiconductor substrate is defined as one second dielectric regions；
A3: a first metal layer is formed in the region of first circuit layout；
A4: the low dielectric bumps being made of a dielectric materials are formed, wherein the low dielectric bumps are formed simultaneously in institute
It states in the first dielectric regions and second dielectric regions, the low dielectric bumps in first dielectric regions are defined as one
First dielectric bumps, the low dielectric bumps in second dielectric regions are defined as one second dielectric bumps, wherein described
The thickness of second dielectric bumps is not more than the thickness of first dielectric bumps, and at least part of second dielectric bumps
Thickness is less than the thickness of first dielectric bumps；And
A5: a second metal layer is formed in the region that the second circuit is laid out；
It is further comprising the steps of to form first dielectric bumps: according to the compound near the neighbouring crossover region half
Size needed for one impedance of conductor integrated circuit determines first dielectric bumps for corresponding to the neighbouring crossover region
One dielectric constant of thickness, area and shape and the dielectric materials is promoted whereby with forming first dielectric bumps
The efficiency of the compound semiconductor integrated circuit.
2. a kind of circuit arrangement method of compound semiconductor integrated circuit, which comprises the following steps:
A1: a compound semiconductor integrated circuit layout delimited in the upper surface of a compound semiconductor substrate, wherein describedization
Closing object semiconductor integrated circuit layout includes that one first circuit layout and a second circuit are laid out, wherein the first circuit cloth
The region that the region of office is laid out with the second circuit overlaps in an overlapping region, and one is defined as adjacent to crossover region comprising institute
State the surrounding adjacent regions of overlapping region and the overlapping region；
A2: one first dielectric regions delimited in the upper surface of the compound semiconductor substrate, wherein first dielectric regions
Within the neighbouring crossover region, and first dielectric regions overlap at least partly described overlapping region, wherein
Region other than first dielectric regions of the upper surface of the compound semiconductor substrate is defined as one second dielectric regions；
A3: a first metal layer is formed in the region of first circuit layout；
A4: the low dielectric bumps being made of a dielectric materials are formed, wherein the low dielectric bumps are formed simultaneously in institute
It states in the first dielectric regions and second dielectric regions, the low dielectric bumps in first dielectric regions are defined as one
First dielectric bumps, the low dielectric bumps in second dielectric regions are defined as one second dielectric bumps, wherein described
The thickness of second dielectric bumps is not more than the thickness of first dielectric bumps, and at least part of second dielectric bumps
Thickness is less than the thickness of first dielectric bumps；And
A5: a second metal layer is formed in the region that the second circuit is laid out；
It is further comprising the steps of:
A power amplifier delimited to be in the layout of in the compound semiconductor integrated circuit layout；
A power amplifier is formed in the region that the power amplifier is laid out, wherein the power amplifier includes one first
End, a second end and a third end, wherein one of the first end and the second end are the power amplifier
An output end, wherein the first end is electrical connected with one of the first metal layer and the second metal layer,
The second end and the first metal layer and the second metal layer it is therein it is another be electrical connected so that the power is put
The first end and the second end of big device form isolation by first dielectric bumps；And
According to one between the first end and the second end of the power amplifier near the neighbouring crossover region
Size needed for output impedance, determine to correspond to the thickness of first dielectric bumps of the neighbouring crossover region, area and
One dielectric constant of shape and the dielectric materials promotes the compound to form first dielectric bumps whereby
The efficiency of semiconductor integrated circuit.
3. the circuit arrangement method of compound semiconductor integrated circuit according to claim 2, which is characterized in that the function
Rate amplifier be bipolar transistor or a heteroj unction bipolar transistor, the first end be a collector, described second
End is an emitter-base bandgap grading, and the third end is a base stage, wherein the collector and institute of the output impedance for the power amplifier
State the impedance between emitter-base bandgap grading.
4. the circuit arrangement method of compound semiconductor integrated circuit according to claim 2, which is characterized in that the function
Rate amplifier is a field-effect transistor, and the first end is a drain electrode, and the second end is a source electrode, and the third end is a grid
Pole, wherein impedance of the output impedance between the drain electrode and the source electrode of the power amplifier.
5. a kind of circuit arrangement method of compound semiconductor integrated circuit, which comprises the following steps:
A1: a compound semiconductor integrated circuit layout delimited in the upper surface of a compound semiconductor substrate, wherein describedization
Closing object semiconductor integrated circuit layout includes that one first circuit layout and a second circuit are laid out, wherein the first circuit cloth
The region that the region of office is laid out with the second circuit overlaps in an overlapping region, and one is defined as adjacent to crossover region comprising institute
State the surrounding adjacent regions of overlapping region and the overlapping region；
A2: one first dielectric regions delimited in the upper surface of the compound semiconductor substrate, wherein first dielectric regions
Within the neighbouring crossover region, and first dielectric regions overlap at least partly described overlapping region, wherein
Region other than first dielectric regions of the upper surface of the compound semiconductor substrate is defined as one second dielectric regions；
A3: a first metal layer is formed in the region of first circuit layout；
A4: the low dielectric bumps being made of a dielectric materials are formed, wherein the low dielectric bumps are formed simultaneously in institute
It states in the first dielectric regions and second dielectric regions, the low dielectric bumps in first dielectric regions are defined as one
First dielectric bumps, the low dielectric bumps in second dielectric regions are defined as one second dielectric bumps, wherein described
The thickness of second dielectric bumps is not more than the thickness of first dielectric bumps, and at least part of second dielectric bumps
Thickness is less than the thickness of first dielectric bumps；And
A5: a second metal layer is formed in the region that the second circuit is laid out；
It is further comprising the steps of:
It delimit a main power amplifier layout and a bias circuit power amplifier is in the layout of the compound semiconductor and integrates
In circuit layout；
A main power amplifier is formed in the region of the main power amplifier layout, wherein the main power amplifier includes
One main power amplifier first end, a main power amplifier second end and a main power amplifier third end, wherein the master
Power amplifier third end is an input terminal of the main power amplifier；
A bias circuit power amplifier is formed in the region that the bias circuit power amplifier is laid out, wherein the bias
Circuit power amplifier includes a bias circuit power amplifier first end, a bias circuit power amplifier second end and one
Bias circuit power amplifier third end, wherein the bias circuit power amplifier first end and the first metal layer and institute
It states one of second metal layer to be electrical connected, the main power amplifier third end and the first metal layer and described the
The wherein another of two metal layers is electrical connected, so that the bias circuit power amplifier first end and the main power amplification
Device third end forms isolation by first dielectric bumps；And
According to the bias circuit power amplifier first end and the main power amplification near the neighbouring crossover region
Size needed for an impedance between device third end determines the thickness for corresponding to first dielectric bumps of the neighbouring crossover region
One dielectric constant of degree, area and shape and the dielectric materials promotes institute to form first dielectric bumps whereby
The efficiency of compound semiconductor integrated circuit is stated, wherein the impedance is an input impedance of the main power amplifier.
6. the circuit arrangement method of -5 any compound semiconductor integrated circuits according to claim 1, which is characterized in that
The dielectric materials have a water absorption rate less than 5%.
7. the circuit arrangement method of -5 any compound semiconductor integrated circuits according to claim 1, which is characterized in that
The dielectric materials include at least one selected from following group: polybenzoxazoles PBO and benzocyclobutane BCB.
8. the circuit arrangement method of -5 any compound semiconductor integrated circuits according to claim 1, which is characterized in that
In A4 step, form the low dielectric bumps the following steps are included:
Simultaneously in forming one first low dielectric layer in first dielectric regions and second dielectric regions, wherein described first
The thickness of low dielectric layer is equal to the thickness of second dielectric bumps；And
In forming one second low dielectric layer in first dielectric regions, wherein the thickness of second low dielectric layer is plus described
The thickness of first low dielectric layer is equal to the thickness of first dielectric bumps.
9. the circuit arrangement method of -5 any compound semiconductor integrated circuits according to claim 1, which is characterized in that
In A4 step, wherein form the low dielectric bumps the following steps are included:
Simultaneously in forming one first low dielectric layer in first dielectric regions and second dielectric regions, wherein described first
The thickness of low dielectric layer is equal to the thickness of second dielectric bumps；
Simultaneously in forming the second low dielectric layer in first dielectric regions and second dielectric regions, wherein described second is low
The thickness of dielectric layer is equal to the thickness of first dielectric bumps plus the thickness of first low dielectric layer；And
Exposure development or etching are to remove second low dielectric layer in second dielectric regions.
10. the circuit arrangement method of -5 any compound semiconductor integrated circuits, feature exist according to claim 1
In, in A4 step, form the low dielectric bumps the following steps are included:
Simultaneously in forming the low dielectric bumps in first dielectric regions and second dielectric regions, wherein low Jie
The thickness of electric convex block is equal to the thickness of first dielectric bumps；And
The low dielectric bumps in exposure development or etching second dielectric regions, so that in first dielectric regions
The thickness with a thickness of first dielectric bumps of the low dielectric bumps, and the low dielectric in second dielectric regions
The thickness with a thickness of second dielectric bumps of convex block.
11. the circuit arrangement method of -5 any compound semiconductor integrated circuits, feature exist according to claim 1
In, in A4 step, form the low dielectric bumps the following steps are included:
Simultaneously in forming the low dielectric bumps in first dielectric regions and second dielectric regions；And
The low dielectric bumps in exposure development or etching first dielectric regions and second dielectric regions, so that institute
State the thickness with a thickness of first dielectric bumps of the low dielectric bumps in the first dielectric regions, and second dielectric
The thickness with a thickness of second dielectric bumps of the low dielectric bumps in region.
12. the circuit arrangement method of -5 any compound semiconductor integrated circuits, feature exist according to claim 1
In the surrounding adjacent regions of the overlapping region include the region arround the overlapping region within the scope of 50 μm.
13. the circuit arrangement method of -5 any compound semiconductor integrated circuits, feature exist according to claim 1
In the dielectric constant of the dielectric materials is less than 7.
14. the circuit arrangement method of compound semiconductor integrated circuit according to claim 5, which is characterized in that described
Main power amplifier and the bias circuit power amplifier are bipolar transistor or a heteroj unction bipolar crystal
Pipe, the main power amplifier first end are a main power amplifier collector, and the main power amplifier second end is a main function
Rate amplifier emitter-base bandgap grading, the main power amplifier third end are a main power amplifier base stage, the bias circuit power amplification
Device first end is a bias circuit power amplifier collector, and the bias circuit power amplifier second end is a bias circuit function
Rate amplifier emitter-base bandgap grading, the bias circuit power amplifier third end are a bias circuit power amplifier base stage, wherein described
Impedance of the input impedance between the bias circuit power amplifier collector and the main power amplifier base stage.
15. the circuit arrangement method of compound semiconductor integrated circuit according to claim 5, which is characterized in that described
Main power amplifier and the bias circuit power amplifier are a field-effect transistor, and the main power amplifier first end is
One main power amplifier drain electrode, the main power amplifier second end is a main power amplifier source electrode, the main power amplification
Device third end is a main power amplifier grid, and the bias circuit power amplifier first end is a bias circuit power amplification
Device drain electrode, the bias circuit power amplifier second end are a bias circuit power amplifier source electrode, the bias circuit function
Rate amplifier third end is a bias circuit power amplifier grid, wherein the input impedance is that the bias circuit power is put
Impedance between big device drain electrode and the main power amplifier grid.
16. the circuit arrangement method of -5 any compound semiconductor integrated circuits, feature exist according to claim 1
In further including the steps that insulating layer in a formation at least one between A3 step and A4 step, wherein on described at least one absolutely
Edge layer is formed on the compound semiconductor substrate and on the first metal layer, and insulating layer on described at least one
It is formed under the low dielectric bumps.
17. the circuit arrangement method of compound semiconductor integrated circuit according to claim 16, which is characterized in that constitute
The material of insulating layer includes at least one selected from following group: silicon nitride SiN and silicon oxide sio on described at least one2。
18. the circuit arrangement method of -5 any compound semiconductor integrated circuits, feature exist according to claim 1
In further including the steps that a formation at least once insulating layer before A3 step, at least once insulating layer is formed in wherein described
On the compound semiconductor substrate, and it is described at least once insulating layer be formed in it is under the first metal layer and described
Under low dielectric bumps.
19. the circuit arrangement method of compound semiconductor integrated circuit according to claim 18, which is characterized in that constitute
It is described that at least once the material of insulating layer includes at least one for being selected from following group: silicon nitride SiN and silicon oxide sio2。
20. the circuit arrangement method of -5 any compound semiconductor integrated circuits, feature exist according to claim 1
In further including the steps that an a formation at least protective layer on the compound semiconductor integrated circuit after A5 step.
21. the circuit arrangement method of compound semiconductor integrated circuit according to claim 20, which is characterized in that constitute
The material of an at least protective layer include selected from following group at least one: polybenzoxazoles PBO, silicon nitride SiN and
Silicon oxide sio2。
22. a kind of circuit arrangement method of compound semiconductor integrated circuit, which comprises the following steps:
B1: a compound semiconductor integrated circuit layout delimited in the upper surface of a compound semiconductor substrate, wherein describedization
Closing object semiconductor integrated circuit layout includes that one first circuit layout and a second circuit are laid out, wherein the first circuit cloth
The region that the region of office is laid out with the second circuit overlaps in an overlapping region, and one is defined as adjacent to crossover region comprising institute
State the surrounding adjacent regions of overlapping region and the overlapping region；
B2: one first dielectric regions delimited in the upper surface of the compound semiconductor substrate, wherein first dielectric regions
Within the neighbouring crossover region, and first dielectric regions overlap at least partly described overlapping region, wherein
Region other than first dielectric regions of the upper surface of the compound semiconductor substrate is defined as one second dielectric regions；
B3: a first metal layer is formed in the region of first circuit layout；
B4: one first dielectric bumps being made of a dielectric materials are formed in first dielectric regions；And
B5: a second metal layer is formed in the region that the second circuit is laid out；
It is further comprising the steps of to form first dielectric bumps: according to the compound near the neighbouring crossover region half
Size needed for one impedance of conductor integrated circuit determines first dielectric bumps for corresponding to the neighbouring crossover region
One dielectric constant of thickness, area and shape and the dielectric materials is promoted whereby with forming first dielectric bumps
The efficiency of the compound semiconductor integrated circuit.
23. a kind of circuit arrangement method of compound semiconductor integrated circuit, which comprises the following steps:
B1: a compound semiconductor integrated circuit layout delimited in the upper surface of a compound semiconductor substrate, wherein describedization
Closing object semiconductor integrated circuit layout includes that one first circuit layout and a second circuit are laid out, wherein the first circuit cloth
The region that the region of office is laid out with the second circuit overlaps in an overlapping region, and one is defined as adjacent to crossover region comprising institute
State the surrounding adjacent regions of overlapping region and the overlapping region；
B2: one first dielectric regions delimited in the upper surface of the compound semiconductor substrate, wherein first dielectric regions
Within the neighbouring crossover region, and first dielectric regions overlap at least partly described overlapping region, wherein
Region other than first dielectric regions of the upper surface of the compound semiconductor substrate is defined as one second dielectric regions；
B3: a first metal layer is formed in the region of first circuit layout；
B4: one first dielectric bumps being made of a dielectric materials are formed in first dielectric regions；And
B5: a second metal layer is formed in the region that the second circuit is laid out；
It is further comprising the steps of:
A power amplifier delimited to be in the layout of in the compound semiconductor integrated circuit layout；
A power amplifier is formed in the region that the power amplifier is laid out, wherein the power amplifier includes one first
End, a second end and a third end, wherein one of the first end and the second end are the power amplifier
An output end, wherein the first end is electrical connected with one of the first metal layer and the second metal layer,
The second end is electrical connected with the first metal layer and the wherein another of the second metal layer, so that the power is put
The first end and the second end of big device form isolation by first dielectric bumps；And
According to one between the first end and the second end of the power amplifier near the neighbouring crossover region
Size needed for output impedance, determine to correspond to the thickness of first dielectric bumps of the neighbouring crossover region, area and
One dielectric constant of shape and the dielectric materials promotes the compound to form first dielectric bumps whereby
The efficiency of semiconductor integrated circuit.
24. the circuit arrangement method of compound semiconductor integrated circuit according to claim 23, which is characterized in that described
Power amplifier is bipolar transistor or a heteroj unction bipolar transistor, and the first end is a collector, described the
Two ends be an emitter-base bandgap grading, the third end be a base stage, wherein the output impedance be the power amplifier the collector and
Impedance between the emitter-base bandgap grading.
25. the circuit arrangement method of compound semiconductor integrated circuit according to claim 23, which is characterized in that described
Power amplifier is a field-effect transistor, and the first end is a drain electrode, and the second end is a source electrode, and the third end is one
Grid, wherein impedance of the output impedance between the drain electrode and the source electrode of the power amplifier.
26. a kind of circuit arrangement method of compound semiconductor integrated circuit, which comprises the following steps:
B1: a compound semiconductor integrated circuit layout delimited in the upper surface of a compound semiconductor substrate, wherein describedization
Closing object semiconductor integrated circuit layout includes that one first circuit layout and a second circuit are laid out, wherein the first circuit cloth
The region that the region of office is laid out with the second circuit overlaps in an overlapping region, and one is defined as adjacent to crossover region comprising institute
State the surrounding adjacent regions of overlapping region and the overlapping region；
B2: one first dielectric regions delimited in the upper surface of the compound semiconductor substrate, wherein first dielectric regions
Within the neighbouring crossover region, and first dielectric regions overlap at least partly described overlapping region, wherein
Region other than first dielectric regions of the upper surface of the compound semiconductor substrate is defined as one second dielectric regions；
B3: a first metal layer is formed in the region of first circuit layout；
B4: one first dielectric bumps being made of a dielectric materials are formed in first dielectric regions；And
B5: a second metal layer is formed in the region that the second circuit is laid out；
It is further comprising the steps of:
It delimit a main power amplifier layout and a bias circuit power amplifier is in the layout of the compound semiconductor and integrates
In circuit layout；
A main power amplifier is formed in the region of the main power amplifier layout, wherein the main power amplifier includes
One main power amplifier first end, a main power amplifier second end and a main power amplifier third end, wherein the master
Power amplifier third end is an input terminal of the main power amplifier；
A bias circuit power amplifier is formed in the region that the bias circuit power amplifier is laid out, wherein the bias
Circuit power amplifier includes a bias circuit power amplifier first end, a bias circuit power amplifier second end and one
Bias circuit power amplifier third end, wherein the bias circuit power amplifier first end and the first metal layer and institute
It states one of second metal layer to be electrical connected, the main power amplifier third end and the first metal layer and described the
The wherein another of two metal layers is electrical connected, so that the bias circuit power amplifier first end and the main power amplification
Device third end forms isolation by first dielectric bumps；And
According to the bias circuit power amplifier first end and the main power amplification near the neighbouring crossover region
Size needed for an impedance between device third end determines the thickness for corresponding to first dielectric bumps of the neighbouring crossover region
One dielectric constant of degree, area and shape and the dielectric materials promotes institute to form first dielectric bumps whereby
The efficiency of compound semiconductor integrated circuit is stated, wherein the impedance is an input impedance of the main power amplifier.
27. according to the circuit arrangement method of any compound semiconductor integrated circuit of claim 22-26, feature exists
In the dielectric materials have a water absorption rate less than 5%.
28. according to the circuit arrangement method of any compound semiconductor integrated circuit of claim 22-26, feature exists
In the dielectric materials include at least one selected from following group: polybenzoxazoles PBO and benzocyclobutane BCB.
29. according to the circuit arrangement method of any compound semiconductor integrated circuit of claim 22-26, feature exists
In the surrounding adjacent regions of the overlapping region include the region arround the overlapping region within the scope of 50 μm.
30. according to the circuit arrangement method of any compound semiconductor integrated circuit of claim 22-26, feature exists
In the dielectric constant of the dielectric materials is less than 7.
31. the circuit arrangement method of compound semiconductor integrated circuit according to claim 26, which is characterized in that described
Main power amplifier and the bias circuit power amplifier are bipolar transistor or a heteroj unction bipolar crystal
Pipe, the main power amplifier first end are a main power amplifier collector, and the main power amplifier second end is a main function
Rate amplifier emitter-base bandgap grading, the main power amplifier third end are a main power amplifier base stage, the bias circuit power amplification
Device first end is a bias circuit power amplifier collector, and the bias circuit power amplifier second end is a bias circuit function
Rate amplifier emitter-base bandgap grading, the bias circuit power amplifier third end are a bias circuit power amplifier base stage, wherein described
Impedance of the input impedance between the bias circuit power amplifier collector and the main power amplifier base stage.
32. the circuit arrangement method of compound semiconductor integrated circuit according to claim 26, which is characterized in that described
Main power amplifier and the bias circuit power amplifier are a field-effect transistor, and the main power amplifier first end is
One main power amplifier drain electrode, the main power amplifier second end is a main power amplifier source electrode, the main power amplification
Device third end is a main power amplifier grid, and the bias circuit power amplifier first end is a bias circuit power amplification
Device drain electrode, the bias circuit power amplifier second end are a bias circuit power amplifier source electrode, the bias circuit function
Rate amplifier third end is a bias circuit power amplifier grid, wherein the input impedance is that the bias circuit power is put
Impedance between big device drain electrode and the main power amplifier grid.
33. according to the circuit arrangement method of any compound semiconductor integrated circuit of claim 22-26, feature exists
In further including the steps that insulating layer in a formation at least one between B3 step and B4 step, wherein on described at least one absolutely
Edge layer is formed on the compound semiconductor substrate and on the first metal layer, and insulating layer on described at least one
It is formed under first dielectric bumps.
34. the circuit arrangement method of compound semiconductor integrated circuit according to claim 33, which is characterized in that constitute
The material of insulating layer includes at least one selected from following group: silicon nitride SiN and silicon oxide sio on described at least one2。
35. according to the circuit arrangement method of any compound semiconductor integrated circuit of claim 22-26, feature exists
In further including the steps that a formation at least once insulating layer before B3 step, at least once insulating layer is formed in wherein described
On the compound semiconductor substrate, and it is described at least once insulating layer be formed in it is under the first metal layer and described
Under first dielectric bumps.
36. the circuit arrangement method of compound semiconductor integrated circuit according to claim 35, which is characterized in that constitute
It is described that at least once the material of insulating layer includes at least one for being selected from following group: silicon nitride SiN and silicon oxide sio2。
37. according to the circuit arrangement method of any compound semiconductor integrated circuit of claim 22-26, feature exists
In further including the steps that an a formation at least protective layer on the compound semiconductor integrated circuit after B5 step.
38. the circuit arrangement method of compound semiconductor integrated circuit according to claim 37, which is characterized in that constitute
The material of an at least protective layer include selected from following group at least one: polybenzoxazoles PBO, silicon nitride SiN and
Silicon oxide sio2。
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| TW576855B (en) * | 2001-12-10 | 2004-02-21 | Univ Nat Cheng Kung | Method for producing polybenzoxazole/clay nanocomposites |
| CN100533236C (en) * | 2005-11-29 | 2009-08-26 | 中华映管股份有限公司 | Pixel structure |
| US7595523B2 (en) * | 2007-02-16 | 2009-09-29 | Power Integrations, Inc. | Gate pullback at ends of high-voltage vertical transistor structure |
| US9117820B2 (en) * | 2012-08-08 | 2015-08-25 | United Microelectronics Corp. | Conductive line of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6136683A (en) * | 1997-04-15 | 2000-10-24 | Oki Electric Industry Co., Ltd. | Semiconductor device and method for production thereof |
| CN101764123A (en) * | 2008-12-23 | 2010-06-30 | 国际商业机器公司 | Millimeter wave transmission line for slow phase velocity |
| CN103633062A (en) * | 2012-08-24 | 2014-03-12 | 稳懋半导体股份有限公司 | Compound semiconductor integrated circuit |
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| CN109346464B (en) | 2023-11-28 |
| CN109346464A (en) | 2019-02-15 |
| CN106611760A (en) | 2017-05-03 |
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