CN105720087B

CN105720087B - FinFET process devices protection ring

Info

Publication number: CN105720087B
Application number: CN201410725319.0A
Authority: CN
Inventors: 赵劼; 钟汇才
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2014-12-02
Filing date: 2014-12-02
Publication date: 2019-06-14
Anticipated expiration: 2034-12-02
Also published as: CN105720087A

Abstract

A kind of FinFET process devices protection ring, comprising: active area；Multiple fin structures are formed on active area and extend in a first direction distribution；Multiple contact holes are distributed between multiple fin structures, contact active area；Wiring layer is distributed on active area, is electrically connected with multiple contact holes.According to FinFET protection ring of the invention, the fin and contact hole that are arranged alternately only are added in fin extending direction in device periphery locality protection ring, with low cost, expeditiously prevents the latch-up of FinFET.

Description

FinFET process devices protection ring

Technical field

The present invention relates to a kind of semiconductor devices, more particularly to a kind of FinFET process devices protection ring.

Background technique

Traditional MOS transistor is in device operation, since the accuracy limitations of traditional handicraft manufacture make source and drain There are various dead resistances, inductance and around gate dielectric, there are various parasitic electricity between area and substrate other parts Hold, or the npn or pnp transistor of the additional undesirable doped region as caused by impurity diffusion and presence parasitism, these distributions Parasitic parameter and parasitic active/passive device around MOSFET effectively improve the electric property of device can not.It is special Not, existing parasitic transistor can make device leakage current increase between substrate well regions and source-drain area, or even certain Under the conditions of cause the transistor logic state to change, and make transistor by being referred to as " latch (latch-up) effect " Adverse effect.

/ the interference of the outer signals noise at edge latch-up and is further prevented around chip in order to prevent, usually As shown in the top view of Fig. 1, in the one circle protection ring of periphery addition of device.Specifically, in the central area of semiconductor chip, most The rectangle that the alphabetical G at center is occupied represents the gate stack lines of conventional MOS FET (although illustrating only a lines in figure G, but can have parallel, intersection, tortuous a plurality of grid lines in practical devices), generally include first grid technique The high-k gate dielectric lamination of the metal gates and lower section (paper is inwardly) of DOPOS doped polycrystalline silicon or rear grid technique, the edge grid lines G Second direction (left and right directions is first direction in figure, and up and down direction is second direction) has been crossed active as representated by alphabetical A Area, grid lines G along first direction two sides be device source-drain area, the contact hole and source-drain area that source-drain area is represented by letter C The first metal wiring layer electrical contact that the alphabetical M1 of top (paper is outwardly) is represented.In the outer of semiconductor devices or semiconductor chip Enclose region, in order to prevent latch-up, outer signals noise jamming and the defects of further prevent moisture, chip crack to Active area diffusion, has been usually formed protection ring structure as shown in Figure 1.Protection ring is included in semiconductor devices or semiconductor chip The second active area A in peripheral region, the second active area A of etching are until multiple contact hole C for going deep into substrate and be deposited on The first hardware cloth that (can have interlayer dielectric layer ILD or metal intermetallic dielectric layer MID between the two) on second active area A Line layer M1, wherein multiple contact hole C surround semiconductor devices with annular spread in order to enable protecting effect is uniform in all directions Central area or semiconductor chip central area.In this way, the parasitic transistor in active area lower substrate can be in multiple contacts Be intended to be electrically connected to the first wiring layer M1 that active area periphery protection ring is connected under the influence of the C of hole, without generate or The leakage current for flowing to the two sides grid lines G source-drain area is reduced, so that advantageous reduce latch-up.

In existing process for fabrication of semiconductor device and Floorplanning, in order to enable the size of entire device and half Conductor chip occupied area is minimum, and the width of usual protection ring is generally taken as the minimum value of design rule namely the width of protection ring Spend equal and minimum, such as minimum feature size equal to MOSFET single in central area (not overstates in Fig. 1 for clarity The width of big grid lines G).

However, as device size equal proportion is reduced to 22nm technology and hereinafter, such as FinFET (FinFET) and the three-dimensional multi-gate device of three grid (tri-gate) device becomes one of most promising new device technology, these knots Structure enhances grid control ability, inhibits electric leakage and short-channel effect.

FinFET and tri-gate devices are different from planar CMOS device, are three-dimensional (3D) devices.In general, passing through selective dry method Either wet etching forms semiconductor fin in body substrate or SOI substrate, and gate stack is formed then across fin.Three It ties up tri-gate transistors and has been respectively formed on conducting channel in three sides of vertical fin structure, thus provide " fully- depleted " operation Mode.Tri-gate transistors can have the multiple fins connected also to increase total driving capability for higher performance.

However, entering 22nm technology node with FinFET and further reducing, for 3D FinFET, especially It is for SOI FinFET, existing protection ring structure as shown in Figure 1 is dfficult to apply to small size FinFET.This be because For following reason, firstly, FinFET substrate isolation technology needs higher and higher craft precision and increasing complexity, Make the source and drain contact hole on the fin of fin transistors grid two sides also smaller and smaller simultaneously, it is difficult to be aligned between multiple contact holes Degree increases, and which increase the difficulty for realizing small resistance, highly conductive protection ring structure.Secondly, fin is usually battle array in FinFET Column arrangement mode, only when entire array outermost arrangement ring shaped contact hole will cause and cross over multiple FinFET under protecting effect Drop, so that central area is difficult to be effectively protected, however it remains a possibility that local latch-up.

Summary of the invention

From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, the protection ring design of FinFET is improved, With low cost, expeditiously prevent the latch-up of FinFET.

For this purpose, the present invention provides a kind of FinFET process devices protection rings, comprising: active area；Multiple fin structures, shape At on active area and extending in a first direction distribution；Multiple contact holes are distributed between multiple fin structures, are contacted active Area；Wiring layer is distributed on active area, is electrically connected with multiple contact holes.

Wherein, the multiple contact hole is arranged alternately with the multiple fin structure.

Wherein, the multiple contact hole is placed equidistant with the multiple fin structure.

Wherein, the multiple contact hole arrangement is row and/or column.The number of row and/or column is less than or equal to 10.

Wherein, the wiring layer ground connection.

Wherein, there is insulating layer between the active area, multiple fin structures and the wiring layer.

The present invention also provides a kind of semiconductor device, including central area and peripheral region, wrapped in the peripheral region Containing FinFET process devices protection ring as described above, the central area includes multiple MOSFET and/or multiple FinFET.

Wherein, the FinFET process devices protection ring is nested multiple protection rings.

According to FinFET protection ring of the invention, only add in fin extending direction in device periphery locality protection ring Add the fin and contact hole being arranged alternately, with low cost, expeditiously prevents the latch-up of FinFET.

Detailed description of the invention

Carry out the technical solution that the present invention will be described in detail referring to the drawings, in which:

Fig. 1 is the top view of the MOSFET element protection ring of the prior art；And

Fig. 2 is the top view according to FinFET protection ring of the invention.

Specific embodiment

Come the feature and its skill of the present invention will be described in detail technical solution referring to the drawings and in conjunction with schematical embodiment Art effect discloses the semiconductor devices of energy low cost, the latch-up for expeditiously preventing FinFET.It may be noted that It is that similar appended drawing reference indicates similar structure, term " first " use herein, " second ", "upper", "lower" etc. It can be used for modifying various device architectures or manufacturing process.These modification do not imply that unless stated otherwise modified device architecture or Space, order or the hierarchical relationship of manufacturing process.

As shown in Fig. 2, for according to the top view of FinFET protection ring of the invention.Figure center is FinFET Array, although it is practical be it is multiple, illustrate only one of magnification ratio comprising (scheme along first direction with what alphabetical A was indicated Middle left and right directions) multiple fin structures -- namely the active area of device, usually Si etches the parallel fin to form prominent substrate Chip arrays.Multiple (one is only shown in figure) gate stack lines G cross over multiple fins along the second direction perpendicular to first direction Chip architecture forms source-drain area (not shown) in fin structure A of the lines G along the two sides of first direction, (the court on source-drain area To except paper) multiple source and drain contact hole C are formd, it has been electrically connected the first metal line M1.Fig. 2 peripheral region (or For the peripheral region of one or more semiconductor devices, or the peripheral region for entire semiconductor chip) in, form according to Protection ring structure of the invention.In addition, central area other than FinFET, also may include large scale photoetching/etching The traditional thick body MOSFET of formation.

Specifically, in the peripheral region where protection ring, (second is active forming fin structure simultaneously with central area Area) on also together form the multiple fin structure F for extending in a first direction distribution simultaneously.Although only showing F in figure to terminate On protection ring boundary, but in practical devices manufacturing process etched substrate formed fin structure all can in base substrate physics By these narrow join domains leakage phenomenon and possible latch-up can occur for connection under the conditions of particular electrical.For This needs to form multiple contact hole C to be electrically connected the first wiring layer M1 and preferably connected to ground do in periphery to shield other signals It disturbs.But due to FinFET size continual reductions, each contact pore size is also reduced simultaneously, peripheral multiple contact holes it Between be aligned and metal filling rate limits the effect of existing protection ring as shown in Figure 1.For this purpose, present invention take advantage of that protection ring region Multiple fin structure F that domain is formed simultaneously are as align structures, under the guidance of FinFET design rule, only between fin F Multiple contact hole C (etch the substrate of the through two sides of the bottom fin F and fill metal material and form contact plug) is added, so that contact It can be automatically aligned to according to design rule (such as minimum spacing between contact hole and adjacent active regions etc.) before the C of hole, thus Improve the protection ring accuracy of manufacture.Since fin F is only distributed along first direction, and the width of protection ring takes under normal circumstances The minimum value of design rule, therefore adjacent multiple contact hole C arrangements as shown in Figure 2 become a column (between two neighboring fin F An only contact hole C), line is actually only distributed in a second direction, and in other words, multiple contact hole C are distributed only over second party Upwards.Preferably, in an embodiment of the present invention, in order to improve the uniformity of protection ring protecting effect, fin F and contact hole C It is arranged alternately, and is more preferably placed equidistant with.In this way, in FinFET practical work process, substrate and active area it Between the parasitic transistor that constitutes can be electrically connected to the first wiring layer M1 by the contact plug in contact hole C and further connect Ground, so that eliminating various parasitic parameter brings influences.

In other preferred embodiments of the invention, since design requirement can widen.The left and right sides of protection ring in Fig. 2 Adjacent fin F between can increase as multiple contact hole C, arrange as row and/or column, multiple contact hole C are in two neighboring fin When arrangement is 1 row/column between piece F its line it is parallel/perpendicular to fin F extending direction, when arrangement is multirow/multiple row, row Cloth at ranks line equally can it is parallel/perpendicular to fin F extending direction.So can be enhanced protection ring electrical connection can By property and reduce contact resistance.But the considerations of in view of laying out pattern design rule and protection ring occupied area, Duo Gejie The number that contact hole arranges the row and/or column to be formed was less than or equal to for 10 (being more than or equal to 1).

Although illustrating the present invention with reference to one or more exemplary embodiments, those skilled in the art, which could be aware that, to be not necessarily to It is detached from the scope of the invention and various suitable changes and equivalents is made to device architecture.In addition, can by disclosed introduction The modification of particular condition or material can be can be adapted to without departing from the scope of the invention by making many.Therefore, the purpose of the present invention does not exist In being limited to as the disclosed specific embodiment for realizing preferred forms of the invention, and disclosed device architecture And its manufacturing method will include all embodiments fallen within the scope of the present invention.

Claims

1. a kind of FinFET process devices protection ring, comprising:

Active area；

Multiple fin structures are formed on active area and only extend in a first direction distribution；

Multiple contact holes are distributed between multiple fin structures, and the substrate for fin two sides of the bottom of going directly only is divided with contacting active area Cloth is not overlapped in a second direction and with multiple fin structures, does not intersect；

Wiring layer is distributed on active area, is electrically connected with multiple contact holes.

2. FinFET process devices protection ring according to claim 1, wherein the multiple contact hole and the multiple fin Chip architecture is arranged alternately.

3. FinFET process devices protection ring according to claim 2, wherein the multiple contact hole and the multiple fin Chip architecture is placed equidistant with.

4. FinFET process devices protection ring according to claim 1, wherein the multiple contact hole be arranged in rows and/ Or column.

5. FinFET process devices protection ring according to claim 4, wherein the number of row and/or column is less than or equal to 10.

6. FinFET process devices protection ring according to claim 1, wherein the wiring layer ground connection.

7. FinFET process devices protection ring according to claim 1, wherein the active area, multiple fin structures with There is insulating layer between the wiring layer.

8. a kind of semiconductor device, including central area and peripheral region, comprising according to claim 1 extremely in the peripheral region 7 described in any item FinFET process devices protection rings, the central area include multiple MOSFET and/or multiple FinFET.

9. semiconductor device according to claim 8, wherein the FinFET process devices protection ring is the multiple of nesting Protection ring.