CN105720087A

CN105720087A - FinFET technology device protection ring

Info

Publication number: CN105720087A
Application number: CN201410725319.0A
Authority: CN
Inventors: 赵劼; 钟汇才
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2014-12-02
Filing date: 2014-12-02
Publication date: 2016-06-29
Anticipated expiration: 2034-12-02
Also published as: CN105720087B

Abstract

A FinFET technology device protection ring comprises an active region; a plurality of fin structures, formed over the active region and distributed in an extending manner along a first direction; a plurality of contact holes, being distributed among the plurality of fin structures and contacting the active region; and a wiring layer, spread over the active region and electrically connected to the plurality of contact holes. The FinFET technology device protection ring in accordance with the invention efficiently prevents a latch-up effect of the FinFET device at a low cost through alternative arrangement of the fins and the contact holes in the extending direction of the fins in the protection ring of the peripheral region of the device.

Description

FinFET process devices protection ring

Technical field

The present invention relates to a kind of semiconductor device, particularly relate to a kind of FinFET process devices protection ring.

Background technology

Traditional MOS transistor is in device operation, owing to the accuracy limitations of traditional handicraft manufacture makes to there is various dead resistance, inductance between source-drain area and other parts of substrate and there is various parasitic capacitance around gate dielectric, or being spread, by impurity, the extra undesirable doped region caused and there is parasitic npn or pnp transistor, these are distributed in the parasitic parameter around MOSFET and parasitic active/passive device makes the electric property of device to be effectively improved.Especially, the parasitic transistor existed between substrate well regions and source-drain area can make device leakage current increase, cause that transistor logic state changes even under certain conditions, and make transistor be referred to as the harmful effect of " breech lock (latch-up) effect ".

In order to prevent latch-up and prevent the interference of outer signals noise at chip circumference/edge further, generally as shown in the top view of Fig. 1, peripheral at device adds a circle protection ring.Concrete, central area at semiconductor chip, the rectangle that the alphabetical G in bosom occupies represents the gate stack lines of conventional MOS FET (although illustrate only a lines G in figure, but can have parallel in practical devices, intersect, tortuous a plurality of grid lines), the metal gates of its DOPOS doped polycrystalline silicon generally including first grid technique or rear grid technique, and the high-k gate dielectric lamination of lower section (paper is inwardly), (in figure, left and right directions is first direction to grid lines G in a second direction, above-below direction is second direction) cross the active area representated by letter A, grid lines G both sides in the first direction are the source-drain area of device, the first metal wiring layer electrical contact that above the contact hole that source-drain area is represented by letter C and source-drain area, the alphabetical M1 of (paper is outwardly) represents.In the outer peripheral areas of semiconductor device or semiconductor chip, in order to prevent latch-up, outer signals noise jamming and prevent the defect such as dampness, wafer crack from spreading to active area further, it is usually formed protection ring structure as shown in Figure 1.Protection ring includes the second active area A in semiconductor device or semiconductor chip outer peripheral areas, etch the second active area A until multiple contact hole C of going deep in substrate and be deposited on the first metal wiring layer M1 that (can have interlayer dielectric layer ILD or metal intermetallic dielectric layer MID between the two) on the second active area A; wherein so that protected effect is uniform in all directions, multiple contact hole C with annular spread around semiconductor device central area or semiconductor chip central area.So; parasitic transistor in active area lower substrate can trend towards being electrically connected to the first wiring layer M1 that active area periphery protection ring connects under the impact of multiple contact hole C; without producing or reducing the leakage current flowing to grid lines G both sides source-drain area, thus favourable reduces latch-up.

In existing process for fabrication of semiconductor device and Floorplanning; so that the size of whole device and semiconductor chip floor space are minimum; the width of usual protection ring is generally taken as the minima of design rule; namely the width of protection ring is equal and minimum, for instance the minimum feature size (not for clear and that the exaggerate width of grid lines G in Fig. 1) of single MOSFET equal in central area.

But, along with device size equal proportion is reduced to 22nm technology and following, such as the three-dimensional multi-gate device of FinFET (FinFET) and three grid (tri-gate) device becomes one of the most promising new device technology, and these structures enhance grid control ability, inhibit electric leakage and short-channel effect.

FinFET is different from planar CMOS device with tri-gate devices, is three-dimensional (3D) device.Generally, on body substrate or SOI substrate, form semiconductor fin by selectivity dry method or wet etching, form gate stack then across fin.Three-dimensional tri-gate transistors has been respectively formed on conducting channel at three sides of vertical fin structure, thus provides " fully-depleted " operational mode.Tri-gate transistors can also have the multiple fins coupled together to increase the total driving force for higher performance.

But, along with FinFET enters 22nm technology node and reducing further, for 3DFinFET, especially for for SOIFinFET, existing protection ring structure as shown in Figure 1 is dfficult to apply to small size FinFET.This is because following reason; first; FinFET substrate isolation technology needs increasingly higher craft precision and increasing complexity; make the source and drain contact hole on the fin of fin transistors grid both sides also more and more less simultaneously; it is directed at difficulty between multiple contact holes to increase, which increases the difficulty of the protection ring structure realizing small resistor, high connductivity.Secondly; in FinFET, fin is generally array arrangement mode; only when whole array outermost layout ring shaped contact hole can be caused and be crossed over multiple FinFET, protected effect declines so that central area is difficult to be effectively protected, however it remains the probability of local latch-up.

Summary of the invention

From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, improve the protection ring design of FinFET, with low cost, the latch-up preventing FinFET expeditiously.

For this, the invention provides a kind of FinFET process devices protection ring, including active area；Multiple fin structures, are formed on active area and extend in a first direction distribution；Multiple contact holes, are distributed between multiple fin structure, contact active area；Wiring layer, is distributed on active area, electrically connects with multiple contact holes.

Wherein, the plurality of contact hole and the plurality of fin structure are arranged alternately.

Wherein, the plurality of contact hole and the plurality of fin structure are placed equidistant.

Wherein, the arrangement of the plurality of contact hole is row and/or row.The number of row and/or row is less than or equal to 10.

Wherein, described wiring layer ground connection.

Wherein, between described active area, multiple fin structure and described wiring layer, there is insulating barrier.

Present invention also offers a kind of semiconductor device, including central area and outer peripheral areas, comprise FinFET process devices protection ring as above in described outer peripheral areas, described central area comprises multiple MOSFET and/or multiple FinFET.

Wherein, described FinFET process devices protection ring is nested multiple protection rings.

According to the FinFET protection ring of the present invention, in device periphery locality protection ring, only add, at fin bearing of trend, the fin and contact hole that are arranged alternately, with low cost, the latch-up preventing FinFET expeditiously.

Accompanying drawing explanation

Technical scheme is described in detail referring to accompanying drawing, wherein:

Fig. 1 is the top view of the MOSFET element protection ring of prior art；And

Fig. 2 is the top view of the FinFET protection ring according to the present invention.

Detailed description of the invention

Referring to accompanying drawing the feature and the technique effect thereof that describe technical solution of the present invention in conjunction with schematic embodiment in detail, disclose can low cost, prevent the semiconductor device of the latch-up of FinFET expeditiously.It is pointed out that similar accompanying drawing labelling represents similar structure, term " first " use herein, " second ", " on ", D score etc. can be used for modifying various device architecture or manufacturing process.These modifications do not imply that modified device architecture or the space of manufacturing process, order or hierarchical relationship unless stated otherwise.

As in figure 2 it is shown, be the top view of the FinFET protection ring according to the present invention.Figure center is the array of FinFET, although reality is multiple, but illustrate only the one of magnification ratio, it includes with multiple fin structures of letter A (in figure the left and right directions) in the first direction represented--namely the active area of device, it is generally Si etching and forms the parallel fins array of prominent substrate.Multiple (only illustrating one in figure) gate stack lines G crosses over multiple fin structures along the second direction being perpendicular to first direction, the fin structure A of lines G both sides in the first direction defines source-drain area (not shown), source-drain area defines multiple source and drain contact hole C (outside paper), has electrically connected the first metal line M1.In the outer peripheral areas (or be the outer peripheral areas of one or more semiconductor device, or be the outer peripheral areas of whole semiconductor chip) of Fig. 2, define the protection ring structure according to the present invention.Additionally, central area is except FinFET, it is also possible to comprise the traditional thick body MOSFET that large scale photoetching/etching is formed.

Concrete, forming fin structure simultaneously with central area, the outer peripheral areas (the second active area) at protection ring place also defines multiple fin structure F simultaneously all together that extend in a first direction distribution.Although figure only illustrating, F terminates on protection ring border; but the fin structure that in practical devices manufacture process, etched substrate is formed all can in base substrate physical connection, can by these narrow join domain generation leakage phenomenon and possible latch-up when particular electrical.Need for this to form multiple contact hole C to electrically connect the first wiring layer M1 and in periphery preferably connected to ground to shield other signal disturbing.But due to FinFET size continual reductions, each contact hole size is also reduced simultaneously, between peripheral multiple contact holes, alignment and metal filled rate limit the effect of existing protection ring as shown in Figure 1.For this; present invention take advantage of that multiple fin structure F that protection ring region concurrently forms are as align structures; under the guidance of FinFET design rule; between fin F, only add multiple contact hole C (substrate the filler metal material of the through fin F two bottom sides of etching form contact plug); automatically can be directed at according to design rule (such as the minimum spacing etc. between contact hole with adjacent active regions) before making contact hole C, thus improve the protection ring accuracy of manufacture.Owing to fin F is only distributed in the first direction; and the width of protection ring takes the minima of design rule in the ordinary course of things; therefore adjacent multiple contact hole C arrangement as shown in Figure 2 becomes string (only having a contact hole C between adjacent two fin F); its line reality is only distributed in a second direction; in other words, multiple contact hole C are distributed only in second direction.Preferably, in an embodiment of the present invention, in order to improve the uniformity of protection ring protected effect, fin F and contact hole C is arranged alternately, and is more preferably placed equidistant.So, in FinFET practical work process, the parasitic transistor constituted between substrate and active area can be electrically connected to the first wiring layer M1 and further ground connection by the contact plug in contact hole C, thus eliminating the impact that various parasitic parameter brings.

In other preferred embodiments of the present invention, owing to designing requirement can be widened.Multiple contact hole C can be increased in fig. 2 between the adjacent fin F of the left and right sides of protection ring; arrangement is row and/or row; multiple contact hole C arrange between adjacent two fin F when being 1 row/column its line is parallel/it is perpendicular to fin F bearing of trend; when arrangement is for multirow/multiple row, the line of its ranks being arranged into equally possible parallel/be perpendicular to fin F bearing of trend.So can strengthen the reliability of protection ring electrical connection and reduce contact resistance.But in view of the consideration of laying out pattern design rule and protection ring floor space, the row of multiple contact holes arrangement formation and/or the number of row are less than or equal to 10 (be more than or equal to 1).

Although the present invention being described with reference to one or more exemplary embodiments, those skilled in the art could be aware that and device architecture is made without departing from the scope of the invention various suitable change and equivalents.Additionally, many amendments that can be adapted to particular condition or material can be made without deviating from the scope of the invention by disclosed instruction.Therefore, the purpose of the present invention does not lie in and is limited to as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will include all embodiments fallen within the scope of the present invention.

Claims

1. a FinFET process devices protection ring, including:

Active area；

Multiple fin structures, are formed on active area and extend in a first direction distribution；

Multiple contact holes, are distributed between multiple fin structure, contact active area；

Wiring layer, is distributed on active area, electrically connects with multiple contact holes.

2. FinFET process devices protection ring according to claim 1, wherein, the plurality of contact hole and the plurality of fin structure are arranged alternately.

3. FinFET process devices protection ring according to claim 2, wherein, the plurality of contact hole and the plurality of fin structure are placed equidistant.

4. FinFET process devices protection ring according to claim 1, wherein, the plurality of contact hole is arranged in rows and/or arranges.

5. FinFET process devices protection ring according to claim 4, wherein, the number of row and/or row is less than or equal to 10.

6. FinFET process devices protection ring according to claim 1, wherein, described wiring layer ground connection.

7. FinFET process devices protection ring according to claim 1, wherein, has insulating barrier between described active area, multiple fin structure and described wiring layer.

8. a semiconductor device, including central area and outer peripheral areas, comprises the FinFET process devices protection ring according to any one of claim 1 to 7 in described outer peripheral areas, described central area comprises multiple MOSFET and/or multiple FinFET.

9. semiconductor device according to claim 8, wherein, described FinFET process devices protection ring is nested multiple protection rings.