JPH03165049A - Structure for preventing concentration of electric field in semiconductor device and method for forming this structure - Google Patents

Abstract

PURPOSE:To simplify the manufacturing steps by forming a second semiconductor region in a self-aligning mode with a conductive plate as a mask. CONSTITUTION:An n<-> eptixial layer 19 is formed on a p<-> semiconductor substrate 12. A p-type isolating and diffusing region 13 is formed with p-type impurities in the epitaxial substrate wherein an n<+> embedded and diffusing layer 10 is formed. Thus, an island 7 is formed. An n-type diffusing region 11 is formed with n-type impurities, and an n<-> region 8 is formed. An oxide film 20 is formed on the entire surface. After holes 21 are formed, a conducting layer 22 is formed. Then, with a pattern 23 formed on the conducting layer 22 as a mask, conducting plates 17a, 17b and 17c are formed. Then a pattern 24 is formed, and p-type impurities are implanted into a region 7a. After the patterns 23 and 24 are removed, p-type diffusing regions 18a and 18b are formed. Then, an oxide film 25 is attached on the entire surface. Thereafter a hole 26 is opened, and a wiring 15 is formed. Thus the concentration of an electric field in the end part of a semiconductor region can be prevented.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a conductive layer extending above a semiconductor region formed on a semiconductor substrate with pn junction separation and across the edge of the semiconductor region. The present invention relates to a structure and a method for forming the structure to prevent electric field concentration from occurring at the edge of a semiconductor region under a conductive layer due to the influence of an electric field. This is effective when high voltage is applied between semiconductor substrates.

[Conventional technology]

PWM inverter circuits are conventionally known as circuits for driving loads such as brushless motors. Fourth
The figure is a schematic configuration diagram showing one phase of a PWM inverter circuit. Power switching devices such as power MOS transistors 2 and 3 are totem pole connected between the high potential power supply line 1 and the ground. The output of this phase is derived from the connection point of power MOS transistor 2.3 and applied to the load. The upper and lower arm drive circuits 4.5 receive upper and lower arm control signals from a control circuit (not shown), respectively, and drive these control signals respectively.

The lower arm power MO8) is converted into a gate signal for turning on/off the transistors 2 and 3 and is applied to the power MOS transistor 2.3.

FIG. 5 is a sectional view showing the state of insulation separation when the upper and lower arm drive circuits 4.5 are formed on one chip 6. The upper arm drive circuit 4 is formed in a region 8 formed within the island 7, and the lower arm drive circuit 5 is formed in the island 9. The upper arm power MOS transistor 2 operates in a high voltage region,
Since the upper arm drive circuit 4 that drives this power MOS transistor 2 must also operate in a high voltage region,
The potential of the island 7 where the upper arm drive circuit 4 is formed becomes extremely high. Therefore, in order to ensure sufficient breakdown voltage, an n region 8 surrounded by an n buried diffusion region 1o and an n diffusion region 11 is created in the island 7, and an upper arm drive circuit 4 is formed in this region 8. ing.

Island 7 and island 9 are formed on the p-semiconductor substrate 12.
It is formed by separating the epitaxial layer by p-isolation diffusion regions 13.

FIG. 6 is a sectional view showing in detail the vicinity of the region 7a at the end of the high voltage island 7. An insulating film] 4 is formed on a p-semiconductor substrate 12, and an aluminum wiring 15 is formed on this insulating film 14. The aluminum wiring 15 is electrically connected to the n-diffusion region 11 and extends above the high voltage island 7, across the end region 7a of the island 7, and toward the low voltage island 9. In the insulating film 14 under the aluminum wiring 15, conductive plates 16a to 16e made of polysilicon are provided. The conductive plates 16a and 16e at both ends are p isolation diffusion regions 13. Intermediate conductive plates 16b to 16d connected to n-diffusion region 11 are kept electrically floating. The conductive plates 16a to 16e are arranged so that their ends overlap.

The p-semiconductor substrate 12 and the p-isolated diffusion region 13 are at a low potential, and the island 7 separated from them by a pn junction is at a high potential. Therefore, depletion layers extend from the pn junction interface to both sides, and the n- region 7a, which has a particularly low impurity concentration, is completely depleted. Dotted lines in FIG. 6 indicate equipotential lines of depletion layers extending into the island 7 from the pn junction interface on both sides.

Conductive plate 16a is fixed to the low potential of p isolation diffusion region 13, and conductive plate 16e is fixed to the high potential of n diffusion region 11. Conductive plate 16 in floating state
b, 16c, and 16d are fixed at a certain potential by the first capacitance between the conductive plates 168 to 16e and the second capacitance between the aluminum wiring 15 and each of the conductive plates 16a to 16e. Here, the above 1. By optimizing the second capacitance, it is possible to fix the potentials of the conductive plates 16a to 16e so that they change approximately linearly from a low potential to a high potential. By doing so, it is possible to prevent the electric field from concentrating on the end region 7a of the island 7, particularly on the surface thereof, due to the influence of the electric field from the high-potential aluminum wiring 15. As a result, as shown by the dotted line in FIG. 6, the equipotential lines in the depletion layer are not concentrated on the p-isolation diffusion region 13 side on the surface of the n- region 7a, but are distributed with an appropriate spread. In this way, the withstand voltage of the island 7 on which the upper arm drive circuit 4 that operates in a high voltage region is formed is increased.

[Problem to be solved by the invention]

The electric field concentration prevention structure in the conventional semiconductor device is configured as described above, and in order to prevent the influence of the electric field from the high potential aluminum wiring 15, the conductive plates 16a to 16e are
must overlap each other's ends. If there is no overlap, the capacitance between the conductive plates 16a to 16e will be extremely small, and the potential of the floating conductive plates 16b and 16c, which are close to the low potential side, will become too high.
The electric field from the high-potential aluminum wiring 15 comes to directly affect the n-region 7a. As a result, n-
Electric field concentration occurs on the surface of region 7a, and the withstand voltage of island 7 decreases.

In order to overlap the ends of the conductive plates 16a to 16e, the ends of adjacent conductive plates must be formed at different heights, so in the manufacturing process,
It is necessary to perform the process of forming the polysilicon layer for the conductive plate twice. The same applies when aluminum is used as the material for the conductive plates 16a to 16e. Further, the capacitance between the conductive plates 16a to 16e varies due to the influence of mask misalignment during the two times of patterning the polysilicon layer. As described above, the conventional electric field concentration prevention structure in a semiconductor device has the problem of poor stability of characteristics (that is, a large amount of variation) and low yield due to the complexity of the process.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an electric field concentration prevention structure and a method for forming the same, which have a simple manufacturing process and stable characteristics.

[Means to solve the problem]

The present invention includes a first semiconductor region of a second conductivity type formed on a semiconductor substrate of a first conductivity type by pn junction separation, and a first semiconductor region above the first semiconductor region. A method for preventing electric field concentration from occurring at an end of a first semiconductor region under a conductive layer due to the influence of an electric field from the conductive layer in a semiconductor device including a conductive layer extending across an end of the conductive layer. It covers structures and how they are formed.

The electric field concentration prevention structure according to the present invention includes an insulating film formed between the first semiconductor region and the conductive layer at the end of the first semiconductor region, and an electrically floating state in the insulating film. and at least one conductive plate of the first conductivity type formed on the surface of the end of the first semiconductor region such that the conductive plates are arranged alternately and their ends overlap. 2 semiconductor regions.

Further, the method for forming the electric field concentration prevention structure according to the present invention includes:
forming a first insulating film on the edge of the first semiconductor region; forming at least one conductive plate on the first insulating film; and forming the first semiconductor using the conductive plate as a mask. A step of introducing impurities into the region and forming at least one second semiconductor region of the first conductivity type on the surface of the end of the first semiconductor region, which is arranged alternately with the conductive plates and whose ends overlap with each other. and a step of forming a second insulating film on the first insulating film and the conductive plate, and the conductive layer is formed on the second insulating film.

[Effect]

In the electric field concentration prevention structure according to the present invention, capacitive coupling is provided between the conductive plate and the second semiconductor region, between the conductive layer and the conductive plate, and between the conductive layer and the second semiconductor region. The conductive plate and the second semiconductor region are fixed at a potential corresponding to the capacitance of the capacitive coupling, that is, the capacitance between the conductive layer, the conductive plate, and the second semiconductor region. By optimizing these capacities, the first
electric field concentration at the edge of the semiconductor region can be prevented.

Further, in the method for forming an electric field concentration prevention structure according to the present invention, the second semiconductor region is formed in a self-aligned manner using the conductive plate as a mask. Therefore, no misalignment occurs between the two, and a stable capacitance can always be obtained between the conductive plate and the second semiconductor region. Further, the process of forming the conductive plate only needs to be performed once.

〔Example〕

FIG. 1 is a sectional view showing an embodiment of an electric field concentration prevention structure in a semiconductor device according to the present invention.

Islands 7 separated by p-isolation diffusion regions 13 are formed on the p-semiconductor substrate 12 . An n-region 8 surrounded by an n-buried diffusion region 10 and an n-diffusion region 11 is formed within the island 7, and an upper arm drive circuit shown in FIG. 4 is formed, for example. On the surface of the region 7a at the end of the island 7, a p-diffusion region 18a,
18b is formed.

An insulating film 14 is formed on the island 7 and the p-isolated diffusion region 13, and a conductive layer such as an aluminum wiring 15 is formed on this insulating film 14. The aluminum wiring 15 is electrically connected to the n-diffusion region 11 and runs above the high voltage island 7 across the end region 7a of the island 7 to the low voltage island (island 9 in FIG. 5), which is not shown. extending in the direction. In the insulating film 14 under the aluminum wiring 15, conductive plates 17a to 17c made of a conductive material such as polysilicon or aluminum are provided. The conductive plates 17a and 17c at both ends are each p
Separation diffusion region 13. An intermediate conductive plate 17b connected to the n-diffusion region 11 is kept electrically floating. The conductive plates 17a to 17c and the p-diffusion regions 18a and 18b are arranged alternately and aligned so that their ends overlap.

The p-semiconductor substrate 12 and the p-isolated diffusion region 13 are at a low potential, and the island 7 separated from them by a pn junction is at a high potential. Therefore, a depletion layer extends from the pn junction interface to both sides, and the n'''' region 7a, which has a particularly low impurity concentration, is completely depleted. The dotted lines in FIG. 1 represent equipotential lines of depletion layers extending into the island 7 from the pn junction interface on both sides.

The conductive plate 17a is fixed to the low potential of the p isolation diffusion region 13, and the conductive plate 17C is fixed to the high potential of the n diffusion region 11. Conductive plate 17a+ 17b+
17 between each adjacent one of the c and p diffusion regions 18a, 18b, the aluminum wiring 15 and each conductive plate) 17a,
17b and 17c, and between aluminum wiring 15 and each p diffusion region 18a, 18b are capacitively coupled by the capacitance existing between them. Therefore, depending on the capacity of the capacitive coupling, the floating conductive plate 17b and the floating p diffusion regions 18a and 18b are fixed at a certain potential.

Here, by optimizing the capacity of the above capacitive coupling,
conductive plates 17a to 17c and p diffusion region 18a,
It is possible to fix the potential of 18b so that it changes approximately linearly from a low potential to a high potential. By doing so, it is possible to prevent the electric field from concentrating on the end region 7m of the island 7, particularly on its surface, due to the influence of the electric field from the high-potential aluminum wiring 15. As a result, as shown by the dotted line in FIG. 1, the equipotential lines in the depletion layer are not concentrated on the p-isolation diffusion region 13 side on the surface of the n- region 7a, but are distributed with an appropriate spread.

In this way, the breakdown voltage of the island 7 on which the upper arm drive circuit 4 of FIG. 4, which operates in a high voltage region, is formed, for example, can be increased.

2A to 2F are cross-sectional views showing a method of forming the electric field concentration prevention structure of FIG. 1. First, as shown in FIG. 2A, a high concentration of n-type impurities is added to a predetermined region of the p-semiconductor substrate 12, and an n'''' semiconductor is epitaxially grown thereon. An epitaxial substrate is prepared in which an epitaxial layer 19 is formed and an n 2 buried diffusion layer 10 is formed in a predetermined region of the pn junction interface between the two.

Next, as shown in FIG. 2B, islands 7 are formed by forming p-isolation diffusion regions 13 by selectively diffusing p-type impurities. Further, in the island 7, an n-diffusion region 11 is formed by selective diffusion of n-type impurities, thereby forming an n- region 8 surrounded by the n-buried diffusion layer 10 and the n-diffusion region 11.

Then, a silicon oxide film 20 is formed on the island 7 and the p isolation diffusion region 13, and a contact hole 21 is formed by patterning the silicon oxide film 20.

Thereafter, a conductive layer 22 made of a conductor such as polysilicon or aluminum is formed over the entire surface.

Next, as shown in FIG. 2C, a resist pattern 23 is formed on the conductive layer 22, and the conductive layer 22 is etched using the resist pattern 23 as a mask, thereby forming the conductive plates 17a and 17b.

17c is formed. Conductive plates 17a and 17c connect p isolation diffusion regions 13 and n through contact holes 21.
They are connected to the diffusion regions 11, respectively. Then, resist pattern 2 for a mask in the next step of ion implantation.
form 4.

Next, using conductive plates 17a, 17b, and 17c (and resist pattern 23 thereon) and resist pattern 2'4 as masks, p-type impurities such as boron are ion-implanted into n- region 7a. After removing the resist patterns 23 and 24, annealing is performed to form p diffusion regions 18a and 18b in the n- region 7a, as shown in FIG. 2D.

Next, as shown in FIG. 2E, after a passivation oxide film 25 is deposited on the entire surface, the n-diffusion region 1 is formed by photolithography.
A contact hole 26 is made on the top of the contact hole 26. And finally,
Afl-St sputtering is performed to form aluminum wiring 15 on passivation oxide film 25 as shown in FIG. 2F. This aluminum wiring 15 is insulated by an insulating film (corresponding to the insulating film 14 in FIG. 1) consisting of a silicon oxide film 20 and a passivation oxide film 25, except that it is connected to the n-diffusion region 11 through a contact hole 26. There is.

According to the above embodiment, the conductive plates 17a, 17b, 1
The process of forming the conductive layer 22 of polysilicon, aluminum, etc. for forming the conductive layer 7c only requires one step as shown in FIG. 2B. Also, p diffusion region 18a.

18b is a conductive plate 17a + 17b,
Since the conductive plates 17a and 17c are formed in a self-aligned manner using the conductive plates 17a and 17c as a mask, no misalignment occurs and the conductive plates 17a, 17
There is always overlap between adjacent ends of bb, 17c and p diffusion regions 18a, 18b depending on diffusion conditions such as diffusion time. This overlap can be precisely controlled by the diffusion conditions. Therefore, conductive plates 17a, 17b, 17
c and p diffusion regions 18a.

A stable capacitance between the capacitances 18b and 18b can be obtained at all times, and the electric field concentration prevention property also remains stable without variation.

FIG. 3 is a sectional view showing another embodiment of the electric field concentration prevention structure according to the present invention. In this embodiment, conductive plate 1
7 a, 17 b, 17 c and p diffusion region 18
The capacitive coupling structure formed by a and 18b does not reach the high potential n diffusion region 11, but ends in the middle of the n- region 7a. Therefore, the rightmost conductive plate 17C is not connected to the n-diffused region 11 and is in a floating state. However, in this embodiment as well, as in the previous embodiment, by optimizing each capacitance of the capacitive coupling, the conductive plates 17a to 17c and the p diffusion region 18a,
It is possible to fix the potential of 18b so that it changes approximately linearly from a low potential to a high potential.

By doing this, as in the previous embodiment, it is possible to prevent electric field concentration from occurring in the end region 7a of the island 7, particularly on its surface, due to the influence of the electric field from the high potential aluminum wiring 15.

Note that the leftmost conductive plate 17a and the p separation diffusion region 13
If the capacitance between the conductive plate 17a and the conductive plate 17a can be made extremely large and strong capacitive coupling can be achieved between them, the conductive plate 17a may also be placed in a floating state, similar to the conductive plate 17c of the embodiment shown in FIG.

Further, in the above embodiment, the aluminum wiring 15 is connected to the n-diffusion region 11 of the island 7, but regardless of the connection to the island 7,
The present invention is effective in all cases where a conductive layer having the same potential as the island 7 crosses above the end of the island 7.

〔Effect of the invention〕

As explained above, according to the electric field concentration prevention structure of the present invention, at least one conductive plate is provided in the insulating film that insulates the end of the first semiconductor region and the conductive layer, and the first semiconductor region at least one second semiconductor region alternately aligned with the conductive plate on a surface of an end of the conductive plate, and between the conductive plate and the second semiconductor region, between the conductive layer and the conductive plate, and between the conductive layer and the second semiconductor region. By configuring the semiconductor regions to be capacitively coupled, the potentials of the conductive plate and the second semiconductor region are fixed according to each capacitance of the capacitive coupling. Electric field concentration at the end of the first semiconductor region can be prevented.

Further, according to the method for forming an electric field concentration prevention structure of the present invention, the second semiconductor region is formed in a self-aligned manner using the conductive plate as a mask, so that the capacitance between the conductive plate and the second semiconductor region is reduced. A stable product can be obtained at all times, and the process of forming the conductive plate only needs to be performed once.

As a result, it is possible to obtain an electric field concentration prevention structure and a method for forming the same, which have a simple manufacturing process and stable characteristics.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an embodiment of the electric field concentration prevention structure according to the present invention, FIGS. 2A to 2F are cross-sectional views showing the steps for forming the structure of FIG. 1, and FIG. 3 is a cross-sectional view showing an example of the electric field concentration prevention structure according to the present invention. A sectional view showing another example of the prevention structure, FIG. 4 is a conventional PW
A schematic configuration diagram showing one phase of the M inverter circuit, Fig. 5 is a cross-sectional view showing the state of insulation separation between high-potential islands and low-potential islands, and Fig. 6 is a cross-sectional view showing a conventional electric field concentration prevention structure. It is. In the figure, 7 is an island, 12 is a p-semiconductor substrate, and 13 is a p-semiconductor substrate.
Separation diffusion region, 14 insulating film, 15 aluminum wiring, 17
A to 17c are conductive plates, and 18a and 18b are p diffusion regions. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A first semiconductor region of a second conductivity type formed on a semiconductor substrate of a first conductivity type by pn junction separation, and an end portion of the first semiconductor region above the first semiconductor region. In the semiconductor device including a conductive layer extending across the conductive layer, the first conductive layer under the conductive layer is
A structure for preventing electric field concentration from occurring at an end of a semiconductor region, the insulation being formed between the first semiconductor region and the conductive layer at the end of the first semiconductor region. a film; at least one conductive plate formed in an electrically floating state in the insulating film; and at least one conductive plate arranged alternately with the conductive plate on a surface of an end portion of the first semiconductor region and having mutual end portions. At least one
A structure for preventing electric field concentration in a semiconductor device comprising: two second semiconductor regions of a first conductivity type. (2) A first semiconductor region of a second conductivity type formed on a semiconductor substrate of a first conductivity type by pn junction separation, and an end portion of the first semiconductor region above the first semiconductor region. In the semiconductor device including a conductive layer extending across the conductive layer, the first conductive layer under the conductive layer is
A method for forming a structure for preventing electric field concentration from occurring at an end of a semiconductor region, the method comprising: forming a first insulating film on an end of the first semiconductor region; forming at least one conductive plate on one insulating film; and introducing an impurity into the first semiconductor region using the conductive plate as a mask, and introducing the impurity into the surface of the end of the first semiconductor region. forming at least one second semiconductor region of the first conductivity type that is arranged alternately with the conductive plates and whose ends overlap each other; and forming a second insulating film on the first insulating film and the conductive plate. forming an electric field concentration prevention structure in a semiconductor device, the conductive layer being formed on the second insulating film.