CN106611760A

CN106611760A - Circuit layout method for compound semiconductor integration circuit

Info

Publication number: CN106611760A
Application number: CN201510695821.6A
Authority: CN
Inventors: 蔡绪孝; 许荣豪; 刘怡伶; 林正国
Original assignee: WIN Semiconductors Corp
Current assignee: WIN Semiconductors Corp
Priority date: 2015-10-23
Filing date: 2015-10-23
Publication date: 2017-05-03
Anticipated expiration: 2035-10-23
Also published as: CN109346464A; CN106611760B; CN109346464B

Abstract

The invention provides a circuit layout method for a compound semiconductor integration circuit. The method comprises steps: a first circuit layout and a second circuit layout overlapped in an overlapped area are set on the upper surface of a compound semiconductor substrate; an adjacent crossover area comprises the overlapped area and a surrounding adjacent area; a first dielectric area is set to be in the adjacent crossover area and is overlapped with at least part of the overlapped area; a first metal layer is formed on the first circuit layout; a first dielectric convex block is formed in the first dielectric area or the first dielectric convex block is formed in the first dielectric area and a second dielectric convex block is formed in a second dielectric area beyond the first dielectric area at the same time, wherein the thickness of the second dielectric convex block is no larger than and at least partially smaller than that of the first dielectric convex block; and a second metal layer is formed on the second circuit layout. The moisture-resistance ability of the compound semiconductor integration circuit can be greatly improved, and the efficiency of the compound semiconductor integration circuit can be improved.

Description

The circuit arrangement method of compound semiconductor integrated circuit

Technical field

The present invention has about a kind of circuit arrangement method of compound semiconductor integrated circuit, espespecially one kind Improve the circuit layout of the compound semiconductor integrated circuit of the humidity-proof ability of compound semiconductor integrated circuit Method.

Background technology

At a compound semiconductor integrated circuit (compound semiconductor integrated circuits) In, when neither idiostatic metal level needs staggeredly bridging (cross-connect), between two metal levels Isolation need to be carried out in the region of staggeredly bridging.General prior art is formed with polyimides (Polyimide) The sealing coat for being constituted is bridged neither interlocking for idiostatic metal level to isolate, typically in a down payment The imido sealing coat of a strata is coated with category layer, one is formed on the sealing coat of polyimides and is pushed up Metal level, wherein bottom metal layer and top metal level are neither idiostatic metal level.Except belonging in down payment Layer and the top metal level overlapping region for staggeredly bridging and its nearby need this polyimides sealing coat it Outward, other regions and do not need the imido sealing coat of this strata.Because prior art can't be special Do not go to etch to remove the sealing coat of polyimides, thus the sealing coat of polyimides does not only exist down payment category The overlapping region that layer and top metal level are staggeredly bridged, other do not need the region of the sealing coat of polyimides It is not removed.

However, the water absorption rate having due to polyimides itself so that the sealing coat of polyimides is deposited Serious impact can caused to the humidity-proof ability of compound semiconductor integrated circuit.Except in bottom metal layer And the overlapping region that top metal level is staggeredly bridged necessarily has the sealing coat of polyimides different to isolate two Outside the bottom metal layer and top metal level of current potential, other do not need the vast area of the sealing coat of polyimides Domain, is the main cause for causing the humidity-proof ability of compound semiconductor integrated circuit to be greatly reduced.

Additionally, a kind of sealing coat necessarily dielectric materials with low-k, different to isolate two The bottom metal layer and top metal level of current potential, and due to the presence of sealing coat, especially sealing coat must be present In the overlapping region that bottom metal layer and top metal level are staggeredly bridged, therefore sealing coat is in bottom metal layer And an impedance of the compound semiconductor integrated circuit near the overlapping region that staggeredly bridges of top metal level (Impedance) size can affect.

In view of this, inventor develops a kind of circuit arrangement method of compound semiconductor integrated circuit, Above-mentioned shortcoming can be avoided, the humidity-proof ability of compound semiconductor integrated circuit can be significantly increased, with And there is the efficiency for improving compound semiconductor integrated circuit, to take into account using elasticity and economy Etc. considering, therefore there is the generation of the present invention then.

The content of the invention

The technical problem to be solved of the invention has two：If the first, can effectively remove other need not gather The sealing coat of the polyimides of the broad area of imido sealing coat, can be significantly increased compound half The humidity-proof ability of conductor integrated circuit.Therefore, a kind of sealing coat how is formed neither idiostatic to isolate Bottom metal layer and top metal level, and and can effectively remove bottom metal layer and push up metal level staggeredly bridging Overlapping region beyond broad area the sealing coat, so that the integrated electricity of compound semiconductor is significantly increased The humidity-proof ability on road is first technical problem to be solved of the invention.

If the second, can effectively remove the sealing coat of other broad areas for not needing sealing coat, except can Reduce outside impact of the sealing coat to the size of the impedance of compound semiconductor integrated circuit, or even may be used also It is present near the overlapping region that bottom metal layer and top metal level are staggeredly bridged by being designed adjustment The thickness of sealing coat, area and shape and select sealing coat material dielectric constant so that compound The size of the impedance of semiconductor integrated circuit is affected to become contributes to compound semiconductor integrated circuit Efficiency is good and bad, make design originally on the contrary adjustment be unfavorable for compound semiconductor integrated circuit this The impact of impedance magnitude, being transformed into contributes to the efficiency of compound semiconductor integrated circuit.Therefore, how Adverse effect of the sealing coat to an impedance of compound semiconductor integrated circuit is reduced, by being designed Adjustment is present in the thickness of the sealing coat near the overlapping region that bottom metal layer and top metal level are staggeredly bridged Degree, area and shape and select the sealing coat material dielectric constant, and then lift compound and partly lead The efficiency of body integrated circuit is second technical problem to be solved of the invention.

To solve foregoing problems, to reach desired effect, the present invention provides a kind of compound quasiconductor collection Into the circuit arrangement method of circuit, comprise the following steps：A1：Delimit a compound semiconductor integrated circuit The upper surface of a compound semiconductor substrate is in the layout of, wherein the compound semiconductor integrated circuit layout bag Include one first circuit layout and a second circuit layout, wherein the region of first circuit layout with this The region of two circuit layouts overlaps in an overlapping region, and one is defined as comprising the overlap adjacent to crossover region Region and the surrounding adjacent regions of the overlapping region；A2：One first dielectric regions delimited in the compound The upper surface of semiconductor substrate, wherein first dielectric regions are located at this within crossover region, and should First dielectric regions overlap with least part of overlapping region, and wherein the compound semiconductor substrate is upper Region beyond first dielectric regions on surface is defined as one second dielectric regions；A3：Form one first Metal level is in the region of first circuit layout；A4：Form be made up of a dielectric materials low Dielectric bumps, the wherein low dielectric bumps are formed at first dielectric regions and second dielectric regions simultaneously Interior, the low dielectric bumps in first dielectric regions are defined as one first dielectric bumps, second dielectric The low dielectric bumps in region are defined as one second dielectric bumps, the wherein thickness of second dielectric bumps The no more than thickness of first dielectric bumps, and the thickness of at least part of second dielectric bumps is less than should The thickness of the first dielectric bumps；And A5：A second metal layer is formed in the region of the second circuit layout It is interior.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein should Dielectric materials have a water absorption rate less than 5%.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein should Dielectric materials include at least one selected from following group：Polybenzoxazoles (polybenzoxazole, Abbreviation PBO) and benzocyclobutane (Benzo Cyclobutane, abbreviation BCB).

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein A4 In step, form the low dielectric bumps and comprise the following steps：Simultaneously in first dielectric regions and this second One first low dielectric layer is formed in dielectric regions, the wherein thickness of first low dielectric layer is equal to second Jie The thickness of electric projection；And in first dielectric regions formed one second low dielectric layer, wherein this second The thickness of low dielectric layer is equal to the thickness of first dielectric bumps plus the thickness of first low dielectric layer.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein A4 In step, wherein form the low dielectric bumps comprising the following steps：While in first dielectric regions and being somebody's turn to do Form one first low dielectric layer in second dielectric regions, wherein the thickness of first low dielectric layer be equal to this The thickness of two dielectric bumps；Formed in first dielectric regions and second dielectric regions simultaneously this second Low dielectric layer, the wherein thickness of second low dielectric layer plus the thickness of first low dielectric layer be equal to this The thickness of one dielectric bumps；And exposure imaging or etching with remove in second dielectric regions this second Low dielectric layer.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein A4 In step, form the low dielectric bumps and comprise the following steps：Simultaneously in first dielectric regions and this second The low dielectric bumps are formed in dielectric regions, the wherein thickness of the low dielectric bumps is convex equal to first dielectric The thickness of block；And exposure imaging or etch the low dielectric bumps in second dielectric regions so that should The thickness of the low dielectric bumps in the first dielectric regions is the thickness of first dielectric bumps, and this second The thickness of the low dielectric bumps in dielectric regions is the thickness of second dielectric bumps.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein A4 In step, form the low dielectric bumps and comprise the following steps：Simultaneously in first dielectric regions and this second The low dielectric bumps are formed in dielectric regions；And exposure imaging or etch first dielectric regions and this Low dielectric bumps in two dielectric regions so that the thickness of the low dielectric bumps in first dielectric regions Spending the thickness for the low dielectric bumps in the thickness of first dielectric bumps, and second dielectric regions is The thickness of second dielectric bumps.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein should The surrounding adjacent regions of overlapping region include the region within the scope of 50 μm arround the overlapping region.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein should The dielectric constant of dielectric materials is less than 7.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein shape It is further comprising the steps of into first dielectric bumps：According to the compound near crossover region half Size needed for one impedance of conductor integrated circuit, decision corresponds to first Jie adjacent to crossover region One dielectric constant of the thickness, area and shape and the dielectric materials of electric projection, with formed this first Dielectric bumps, thereby lift the efficiency of the compound semiconductor integrated circuit.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein also Comprise the following steps：Delimit a power amplifier to be in the layout of in the compound semiconductor integrated circuit layout； A power amplifier is formed in the region of the power amplifier layout, wherein the power amplifier includes one First end, one second end and one the 3rd end, wherein one of the first end and second end are should One outfan of power amplifier, the wherein first end and the first metal layer and the second metal layer its One of be electrical connected, wherein another electricity of second end and the first metal layer and the second metal layer Property be connected so that the first end of the power amplifier and second end are formed by first dielectric bumps Isolation；And the first end according to the power amplifier near crossover region and this second Size needed for an output impedance between end, it is convex adjacent to first dielectric of crossover region that decision corresponds to this One dielectric constant of the thickness, area and shape and the dielectric materials of block, to form first dielectric Projection, thereby lifts the efficiency of the compound semiconductor integrated circuit.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein should Power amplifier is bipolar transistor or a heteroj unction bipolar transistor, and the first end is a collection Pole, second end is an emitter-base bandgap grading, and the 3rd end is a base stage, and wherein the output impedance is the power amplification Impedance between the collector and the emitter-base bandgap grading of device.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein should Power amplifier is a field-effect transistor, and the first end is a drain electrode, and second end is a source electrode, and this Three ends be a grid, wherein the output impedance be the power amplifier the drain electrode and the source electrode between impedance.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein also Comprise the following steps：Delimit a main power amplifier layout and a bias circuit power amplifier be in the layout of In the compound semiconductor integrated circuit layout；A main power amplifier is formed in the main power amplifier cloth In the region of office, wherein the main power amplifier includes that a main power amplifier first end, a main power are put The big end of device second and the end of a main power amplifier the 3rd, the wherein end of main power amplifier the 3rd is the master One input of power amplifier；A bias circuit power amplifier is formed in the bias circuit power amplification In the region of device layout, wherein the bias circuit power amplifier includes a bias circuit power amplifier the One end, second end of bias circuit power amplifier and the end of a bias circuit power amplifier the 3rd, its In the bias circuit power amplifier first end and one of the first metal layer and the second metal layer Be electrical connected, the end of main power amplifier the 3rd and the first metal layer and the second metal layer wherein it It is another to be electrical connected so that the bias circuit power amplifier first end and the end of main power amplifier the 3rd Isolation is formed by first dielectric bumps；And according to the bias circuit near crossover region Size needed for an impedance between power amplifier first end and the end of main power amplifier the 3rd, determines phase Corresponding to this adjacent to the thickness of first dielectric bumps of crossover region, area and shape and the low dielectric One dielectric constant of material, to form first dielectric bumps, thereby lifts the compound semiconductor integrated The efficiency of circuit, the wherein impedance are an input impedance of the main power amplifier.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein should Main power amplifier and the bias circuit power amplifier are that bipolar transistor or a heterojunction are double Polar transistor, the main power amplifier first end be a main power amplifier collector, the main power amplification The end of device second is a main power amplifier emitter-base bandgap grading, and the end of main power amplifier the 3rd is a main power amplifier Base stage, the bias circuit power amplifier first end be a bias circuit power amplifier collector, the bias The end of circuit power amplifier second be a bias circuit power amplifier emitter-base bandgap grading, the bias circuit power amplification The end of device the 3rd is a bias circuit power amplifier base stage, and wherein the input impedance is the bias circuit power Impedance between amplifier collector and the main power amplifier base stage.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein should Main power amplifier and the bias circuit power amplifier are a field-effect transistor, the main power amplifier First end is a main power amplifier drain electrode, and the end of main power amplifier second is a main power amplifier source Pole, the end of main power amplifier the 3rd be a main power amplifier grid, the bias circuit power amplifier First end is bias circuit power amplifier drain electrode, and the end of bias circuit power amplifier second is one inclined Put for a bias circuit power at volt circuit power amplifier source electrode, the end of bias circuit power amplifier the 3rd Big grid pole, the wherein input impedance are the bias circuit power amplifier drain electrode and the main power amplifier Impedance between grid.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein Between A3 steps and A4 steps also include one formed at least one on insulating barrier the step of, wherein this at least one Upper insulating barrier is formed on the compound semiconductor substrate and on the first metal layer, and this is at least Insulating barrier is formed under the low dielectric bumps on one.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein structure Into on this at least one material of insulating barrier include selected from following group at least one：Silicon nitride (SiN) with And silicon oxide (SiO₂)。

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein in Also include before A3 steps one formed at least once insulating barrier the step of, the wherein at least once insulating barrier shape Into on the compound semiconductor substrate, and this at least once insulating barrier be formed at the first metal layer it Under the lower and low dielectric bumps.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein structure Into this at least once the material of insulating barrier include selected from following group at least one：Silicon nitride (SiN) with And silicon oxide (SiO₂)。

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein Also include a formation at least protective layer on the compound semiconductor integrated circuit after A5 steps Step.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein structure Into an at least protective layer material include selected from following group at least one：Silicon nitride (SiN) and Silicon oxide (SiO₂)。

Additionally, the present invention also provides a kind of circuit arrangement method of compound semiconductor integrated circuit, including with Lower step：B1：A compound semiconductor integrated circuit layout delimited in the upper of a compound semiconductor substrate Surface, wherein the compound semiconductor integrated circuit layout are electric including one first circuit layout and one second The region of road layout, the wherein region of first circuit layout and the second circuit layout is in an overlapping region Overlap, one is defined as comprising neighbouring around the overlapping region and the overlapping region adjacent to crossover region Region；B2：One first dielectric regions delimited in the upper surface of the compound semiconductor substrate, wherein this One dielectric regions are located at this within crossover region, and first dielectric regions are with least partly this is overlap Region overlaps, wherein the area beyond first dielectric regions of the upper surface of the compound semiconductor substrate Domain is defined as one second dielectric regions；B3：A first metal layer is formed in the region of first circuit layout It is interior；B4：One first dielectric bumps that formation is made up of a dielectric materials are in first dielectric regions； And B5：A second metal layer is formed in the region of the second circuit layout.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein B4 In step, form first dielectric bumps and comprise the following steps：Simultaneously in first dielectric regions and this A low dielectric bumps are formed in two dielectric regions；And exposure imaging or etching remove second dielectric regions The interior low dielectric bumps so that the thickness of the low dielectric bumps in first dielectric regions for this first The thickness of the low dielectric bumps in the thickness of dielectric bumps, and second dielectric regions is zero.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein B4 In step, form first dielectric bumps and comprise the following steps：Simultaneously in first dielectric regions and this A low dielectric bumps are formed in two dielectric regions；And exposure imaging or etch first dielectric regions and should Low dielectric bumps in second dielectric regions so that the low dielectric bumps in first dielectric regions Thickness is the thickness of first dielectric bumps, and the thickness of the low dielectric bumps in second dielectric regions It is zero.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein Between B3 steps and B4 steps also include one formed at least one on insulating barrier the step of, wherein this at least one Upper insulating barrier is formed on the compound semiconductor substrate and on the first metal layer, and this is at least Insulating barrier is formed under first dielectric bumps on one.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein Also include before B3 steps one formed at least once insulating barrier the step of, the wherein at least once insulating barrier shape Into on the compound semiconductor substrate, and this at least once insulating barrier be formed at the first metal layer it Under lower and first dielectric bumps.

In one embodiment, the circuit arrangement method of aforesaid compound semiconductor integrated circuit, wherein Also include that one forms step of at least protective layer on the compound semiconductor integrated circuit after B5 steps Suddenly.

To further appreciate that the present invention, preferred embodiment is below lifted, coordinate accompanying drawing, by the tool of the present invention Body constitution content and its effect reached describe in detail as follows.

Description of the drawings

Fig. 1 and Figure 1A are respectively a kind of circuit arrangement method of compound semiconductor integrated circuit of the invention A specific embodiment top view and profile；

Figure 1B and Fig. 1 C are respectively a kind of circuit layout side of compound semiconductor integrated circuit of the invention The top view and profile of the another specific embodiment of method；

Fig. 1 D and Fig. 1 E are respectively a kind of circuit layout side of compound semiconductor integrated circuit of the invention The top view and profile of the still another embodiment of method；

Fig. 1 F and Fig. 1 G are respectively a kind of circuit layout side of compound semiconductor integrated circuit of the invention The top view and profile of the still another embodiment of method；

Fig. 1 H and Fig. 1 I are respectively a kind of circuit arrangement method of compound semiconductor integrated circuit of the invention Another specific embodiment top view and profile；

Fig. 1 J and Fig. 1 K are respectively a kind of circuit arrangement method of compound semiconductor integrated circuit of the invention Still another embodiment top view and profile；

Fig. 1 L and Fig. 1 M are respectively a kind of circuit layout side of compound semiconductor integrated circuit of the invention The top view and profile of the still another embodiment of method；

Fig. 1 N and Fig. 1 O are respectively a kind of circuit layout side of compound semiconductor integrated circuit of the invention The top view and profile of the another specific embodiment of method；

Fig. 1 P are a kind of another concrete reality of the circuit arrangement method of compound semiconductor integrated circuit of the invention Apply the top view of example；

Fig. 1 Q are a kind of the another concrete of the circuit arrangement method of compound semiconductor integrated circuit of the invention The top view of embodiment；

Fig. 2 is a kind of circuit arrangement method flow chart of compound semiconductor integrated circuit of the invention；

Fig. 2A is a kind of circuit arrangement method flow chart of compound semiconductor integrated circuit of the invention；

Fig. 2 B～Fig. 2 G are a kind of tool of the circuit arrangement method of compound semiconductor integrated circuit of the invention The process step generalized section of body embodiment；

Fig. 2 H are a kind of the another concrete of the circuit arrangement method of compound semiconductor integrated circuit of the invention The profile of embodiment；

Fig. 2 I are that a kind of the another of compound semiconductor integrated circuit layout method of the invention is embodied as Example profile；

Fig. 2 J are a kind of another concrete reality of the circuit arrangement method of compound semiconductor integrated circuit of the invention Apply the profile of example；

Fig. 2 K are a kind of the another concrete of the circuit arrangement method of compound semiconductor integrated circuit of the invention The profile of embodiment；

Fig. 2 L are a kind of another concrete reality of the circuit arrangement method of compound semiconductor integrated circuit of the invention Apply the profile of example；

Fig. 2 M are a kind of the another concrete of the circuit arrangement method of compound semiconductor integrated circuit of the invention The profile of embodiment；

Fig. 3 is that the one of the circuit arrangement method of a kind of compound semiconductor integrated circuit of the invention is embodied as The schematic top plan view of example；

Fig. 3 A are a kind of the another concrete of the circuit arrangement method of compound semiconductor integrated circuit of the invention The schematic top plan view of embodiment；

Fig. 3 B depict the schematic diagram of the local circuit of Fig. 3 A；

Fig. 3 C are the generalized section of the vertical cross-section of b-b ' hatchings in Fig. 3 B；

Fig. 3 D are a kind of another enforcement of the circuit arrangement method of compound semiconductor integrated circuit of the invention The generalized section of the cross-section structure of example；

Fig. 4 is that the one of the circuit arrangement method of a kind of compound semiconductor integrated circuit of the invention is embodied as The local circuit schematic layout pattern of example；

Fig. 4 A are the partial circuit diagram for corresponding to the embodiment in Fig. 4；

Fig. 4 B are the generalized section of the vertical cross-section of the c-c ' hatchings in Fig. 4；

Fig. 4 C are the partial enlarged drawing in the region of V square frames in Fig. 4 B.

Description of reference numerals：

Specific embodiment

A kind of compound semiconductor of the invention is respectively please refer to Fig. 1 and Figure 1A, Fig. 1 and Figure 1A The top view and profile of one specific embodiment of the circuit arrangement method of integrated circuit.One compound half Conductor integrated circuit layout 1 delimited in the upper surface of a compound semiconductor substrate 10, wherein compound half Conductor integrated circuit layout 1 includes one first circuit layout 21 and a second circuit layout 22.One first gold medal Category layer 61 is formed in the region of the first circuit layout 21.The wherein region and second of the first circuit layout 21 The region of circuit layout 22 overlaps in an overlapping region 31.Wherein one includes overlapping adjacent to crossover region 33 The surrounding adjacent regions 32 of region 31 and overlapping region 31.One first dielectric regions be 41 (the thick frame of black Region) delimited in the upper surface of compound semiconductor substrate 10, wherein the first dielectric regions 41 are located at neighbour Within nearly crossover region 33, and the first dielectric regions 41 and least partially overlapped region 31 overlap (here In embodiment, the first dielectric regions 41 include whole overlapping region 31).Wherein compound semiconductor substrate Region beyond first dielectric regions 41 (region of the thick frame of black) of 10 upper surface is one second dielectric Region 42.The low dielectric bumps 50 that one dielectric materials are constituted are formed at compound semiconductor substrate 10 On and the first metal layer 61 on.In this embodiment, low dielectric bumps 50 are formed at first simultaneously In dielectric regions 41 (region of the thick frame of black) and the second dielectric regions 42.Wherein it is formed at first Jie Low dielectric bumps 50 in electric region 41 be one first dielectric bumps 51 (region of the thick frame of black), first Dielectric bumps 51 have the thickness 53 of one first dielectric bumps.Wherein it is formed in the second dielectric regions 42 Low dielectric bumps 50 are one second dielectric bumps 52, and the second dielectric bumps 52 have one second dielectric bumps Thickness 54, wherein the thickness 53 of the thickness 54 of the second dielectric bumps no more than the first dielectric bumps, and at least Thickness 53 (as shown in Figure 1A) of the thickness 54 of the dielectric bumps of part second less than the first dielectric bumps.One Second metal layer 62 is formed in the region of second circuit layout 22.In this embodiment, second metal layer 62 are formed on the first dielectric bumps 51 and on the second dielectric bumps 52.

In the schema of the present invention, wherein Fig. 1, Figure 1B, Fig. 1 D, Fig. 1 F, Fig. 1 H, Fig. 1 J, Fig. 1 L, In the schemas such as Fig. 1 N, Fig. 1 P, Fig. 1 Q, Fig. 3 B and Fig. 4, the first metal layer 61 is upper right to lower-left The block of 45 degree of oblique lines；And second metal layer 62 is then the block of 45 degree of oblique lines of upper left to bottom right；Upper right Both 45 degree oblique lines to 45 degree of oblique lines and upper left to the bottom right of lower-left block staggeredly is then overlapping region 31；The region of the thick frame of black is the first dielectric regions 41, while being also that the first dielectric bumps 51 are formed Region.Additionally, the region of the thick frame of black is also the first dielectric regions 41 in Fig. 3 and Fig. 3 A, while It is region that the first dielectric bumps 51 are formed.

Please refer to Figure 1B and Fig. 1 C, Figure 1B and Fig. 1 C are respectively a kind of compound of the invention and partly lead The top view and profile of the another specific embodiment of the circuit arrangement method of body integrated circuit.One chemical combination Thing semiconductor integrated circuit layout 1 delimited in the upper surface of a compound semiconductor substrate 10, wherein chemical combination Thing semiconductor integrated circuit layout 1 includes one first circuit layout 21 and a second circuit layout 22.One One metal level 61 is formed in the region of the first circuit layout 21.Wherein the region of the first circuit layout 21 with The region of second circuit layout 22 overlaps in an overlapping region 31.Wherein one includes adjacent to crossover region 33 The surrounding adjacent regions 32 of overlapping region 31 and overlapping region 31.(black is thick for one first dielectric regions 41 The region of frame) delimited in the upper surface of compound semiconductor substrate 10, wherein the first dielectric regions 41 Within neighbouring crossover region 33, and the first dielectric regions 41 and least partially overlapped region 31 overlap ( In this embodiment, the first dielectric regions 41 include whole overlapping region 31).Wherein compound semiconductor base Region beyond first dielectric regions 41 (region of the thick frame of black) of the upper surface of plate 10 is situated between for one second Electric region 42.The low dielectric bumps 50 that one dielectric materials are constituted are formed at compound semiconductor substrate On 10 and on the first metal layer 61.In this embodiment, low dielectric bumps 50 are formed only in first In dielectric regions 41 (region of the thick frame of black), and it is not formed in the second dielectric regions 42, therefore, In this embodiment, the second dielectric regions 42 have no the second dielectric bumps 52.Wherein it is formed at the first dielectric Low dielectric bumps 50 in region 41 are one first dielectric bumps 51 (region of the thick frame of black), and first is situated between Electric projection 51 has the thickness 53 of one first dielectric bumps.One second metal layer 62 is formed at second circuit cloth In the region of office 22.In this embodiment, second metal layer 62 be formed on the first dielectric bumps 51 with And on compound semiconductor substrate 10.

In the embodiment of Fig. 1～Fig. 1 C, low dielectric bumps 50 are simultaneously by the (black of the first dielectric bumps 51 The region of thick frame) and the second dielectric bumps 52 constitute (such as the embodiment of Fig. 1 and Figure 1A), or Be only be made up of the first dielectric bumps 51 (region of the thick frame of black) and without the second dielectric bumps 52 (such as The embodiment of Figure 1B and Fig. 1 C).The major function of the first dielectric bumps 51 is in isolation different potentials The first metal layer 61 and second metal layer 62.However, the second dielectric bumps 52 can but cause compound half The humidity-proof ability of conductor integrated circuit 1 is greatly reduced.Therefore, when the thickness 54 of the second dielectric bumps is not more than The thickness 53 of the first dielectric bumps, and the thickness 54 of at least part of second dielectric bumps is convex less than the first dielectric During the thickness 53 of block, it will help strengthen the humidity-proof ability of compound semiconductor integrated circuit 1.Especially when extremely When the thickness 54 of the dielectric bumps of small part second is less than less than the 90% of the thickness 53 of the first dielectric bumps, i.e., The humidity-proof ability of compound semiconductor integrated circuit 1 can be remarkably reinforced.And the thickness of the second dielectric bumps 52 is got over It is little, then there is more positive effect to the enhancing of the humidity-proof ability of compound semiconductor integrated circuit 1.And when all The second dielectric bumps 52 (namely the embodiment as shown in Figure 1B and Fig. 1 C, nothing second when being all removed Dielectric bumps 52), the humidity-proof ability to strengthening compound semiconductor integrated circuit 1 has splendid effect.

In all embodiments of the invention, some have the second dielectric bumps 52, and some embodiments are then Have no the second dielectric bumps 52.In the embodiment with the second dielectric bumps 52 of the present invention, it is at least The thickness 54 of the dielectric bumps of part second more than 0 and less than the first dielectric bumps thickness 53 90%, be more than 0 and less than the first dielectric bumps thickness 53 85%, more than 0 and less than the thickness 53 of the first dielectric bumps 80%, more than 0 and less than the first dielectric bumps thickness 53 75%, it is more than 0 and convex less than the first dielectric The thickness 53 of block 70%, more than 0 and less than the first dielectric bumps thickness 53 65%, more than 0 and be less than The thickness 53 of the first dielectric bumps 60%, more than 0 and less than the first dielectric bumps thickness 53 55%, More than 0 and less than the first dielectric bumps thickness 53 50%, more than 0 and less than the thickness of the first dielectric bumps Degree 53 45%, more than 0 and less than the first dielectric bumps thickness 53 40%, more than 0 and less than first be situated between The thickness 53 of electric projection 35%, more than 0 and less than the first dielectric bumps thickness 53 30%, more than 0 And less than the first dielectric bumps thickness 53 25%, more than 0 and less than the thickness 53 of the first dielectric bumps 20%th, more than 0 and less than the first dielectric bumps thickness 53 15%, more than 0 and less than the first dielectric bumps Thickness 53 12%, more than 0 and less than the first dielectric bumps thickness 53 10%, more than 0 and less than The thickness 53 of one dielectric bumps 9%, more than 0 and less than the first dielectric bumps thickness 53 8%, more than 0 And less than the first dielectric bumps thickness 53 7%, more than 0 and less than the thickness 53 of the first dielectric bumps 6%th, more than 0 and less than the first dielectric bumps thickness 53 5%, more than 0 and less than the first dielectric bumps Thickness 53 4%, more than 0 and less than the first dielectric bumps thickness 53 3%, more than 0 and less than first be situated between The 2% of the thickness 53 of electric projection or 1% of the thickness 53 more than 0 and less than the first dielectric bumps.

In all embodiments of the invention, overlapping region 31 is the region and second of the first circuit layout 21 The equitant region in region of circuit layout 22.And the surrounding adjacent regions 32 of overlapping region 31 refer to overlay region Region arround domain 31 within the scope of at least 50 μm, the region within the scope of at least 47 μm, at least Region within the scope of 45 μm, the region within the scope of at least 43 μm, at least 40 μm of scope with Interior region, the region within the scope of at least 37 μm, the region within the scope of at least 35 μm, at least Region within the scope of 33 μm, the region within the scope of at least 30 μm, at least 28 μm of scope with Interior region, the region within the scope of at least 25 μm, the region within the scope of at least 23 μm, at least Region within the scope of 20 μm, the region within the scope of at least 17 μm, at least 15 μm of scope with Interior region, the region within the scope of at least 12 μm, the region within the scope of at least 10 μm, at least Region within the scope of 9 μm, the region within the scope of at least 8 μm, within the scope of at least 7 μm Region, the region within the scope of at least 6 μm or the region within the scope of at least 5 μm.And so-called neighbour Nearly crossover region 33 is made up of the surrounding adjacent regions 32 of overlapping region 31 and overlapping region 31.

Additionally, the present invention is when the material of low dielectric bumps 50 is selected, low Jie with low water absorption is selected Electric projection 50, wherein the water absorption rate of low dielectric bumps 50 is at least below 5%, at least below 4.5%, to when young In 4%, at least below 3.5%, at least below 3%, at least below 2.5% or at least below 2%.

In an embodiment of the present invention, the material of selected low dielectric bumps 50 can be a polybenzoxazoles (polybenzoxazole, abbreviation PBO) or a benzocyclobutane (Benzo Cyclobutane, referred to as BCB).The optimum selection of the material of wherein low dielectric bumps 50 is the photosensitive polybenzoxazoles of a tool (polybenzoxazole, abbreviation PBO) or a benzocyclobutane (Benzo Cyclobutane, referred to as BCB).The method that exposure imaging or etching can be passed through, the second dielectric bumps 52 are removed.Especially When the material for selecting to have photosensitive polybenzoxazoles or benzocyclobutane is as the material of low dielectric bumps 50 It is will to be gathered by tool is photosensitive in the second dielectric regions 42 in the method for exposure imaging easily during material The second dielectric bumps 52 that benzoxazoles or benzocyclobutane are constituted are removed completely, thereby strengthen compound The humidity-proof ability of semiconductor integrated circuit 1.

In all embodiments of the invention, its dielectric constant of the material of selected low dielectric bumps 50 is At least below 7, at least below 6.7, at least below 6.3, at least below 6, at least below 5.7, to when young In 5.3, at least below 5, at least below 4.7, at least below 4.3, at least below 4, at least below 3.7, At least below 3.3, at least below 3, at least below 2.7, at least below 2.3, at least below 2, to when young In 1.7, at least below 1.3 or at least below 1.

The embodiment of Fig. 1 D～Fig. 1 O is referred to, there are a different overlapping regions respectively in these embodiments 31st, the change type of one first dielectric bumps 51 (region of the thick frame of black) and one second dielectric bumps 52. From these embodiments, in the surrounding adjacent regions 32 of overlapping region 31 other overlapping regions 31 are had no Situation, by the overlapping region 31, (black of the first dielectric bumps 51 from the point of view of the situation of single overlapping region 31 The region of thick frame) and the second dielectric bumps 52 between various change probability.

Please refer to Fig. 1 D and Fig. 1 E, Fig. 1 D and Fig. 1 E are respectively a kind of compound of the invention and partly lead The top view and profile of the still another embodiment of the circuit arrangement method of body integrated circuit.Its is main Structure is roughly the same with the embodiment shown in Fig. 1 and Figure 1A, but, wherein the first dielectric regions 41 are (black The region of the thick frame of color) it is identical with the size of overlapping region 31 and overlap completely.

Please refer to Fig. 1 F and Fig. 1 G, Fig. 1 F and Fig. 1 G are respectively a kind of compound of the invention and partly lead The top view and profile of the still another embodiment of the circuit arrangement method of body integrated circuit.Its is main Structure is roughly the same with the embodiment shown in Fig. 1 D and Fig. 1 E, but, wherein low dielectric bumps 50 are only formed In the first dielectric regions 41 (region of the thick frame of black), and low Jie is had no in the second dielectric regions 42 Electric projection 50, therefore in this embodiment, only the first dielectric bumps 51 (region of the thick frame of black), And without the second dielectric bumps 52.In this embodiment, second metal layer 62 is formed at the first dielectric bumps 51 On and compound semiconductor substrate 10 on.

Please refer to Fig. 1 H and Fig. 1 I, Fig. 1 H and Fig. 1 I are respectively a kind of compound of the invention and partly lead The top view and profile of the another specific embodiment of the circuit arrangement method of body integrated circuit.Its is main Structure is roughly the same with the embodiment shown in Fig. 1 and Figure 1A, but, wherein the first dielectric regions 41 are (black The region of the thick frame of color) it is fully located within overlapping region 31.

Please refer to Fig. 1 J and Fig. 1 K, Fig. 1 J and Fig. 1 K are respectively a kind of compound of the invention and partly lead The top view and profile of the still another embodiment of the circuit arrangement method of body integrated circuit.Its is main Structure is roughly the same with the embodiment shown in Fig. 1 H and Fig. 1 I, but, wherein low dielectric bumps 50 are only formed In the first dielectric regions 41 (region of the thick frame of black), and low Jie is had no in the second dielectric regions 42 Electric projection 50, therefore in this embodiment, only the first dielectric bumps 51 (region of the thick frame of black), And without the second dielectric bumps 52.In this embodiment, second metal layer 62 is formed at the first dielectric bumps 51 On and compound semiconductor substrate 10 on.

Please refer to Fig. 1 L and Fig. 1 M, Fig. 1 L and Fig. 1 M are respectively a kind of compound of the invention half The top view and profile of the still another embodiment of the circuit arrangement method of conductor integrated circuit.Its master Want structure roughly the same with the embodiment shown in Fig. 1 and Figure 1A, but, wherein the first dielectric regions 41 are (black The region of the thick frame of color) region 31 overlaps with partly overlapping.

Please refer to Fig. 1 N and Fig. 1 O, Fig. 1 N and Fig. 1 O are respectively a kind of compound of the invention half The top view and profile of the another specific embodiment of the circuit arrangement method of conductor integrated circuit.Its master Want structure roughly the same with the embodiment shown in Fig. 1 L and Fig. 1 M, but, wherein 50 shapes of low dielectric bumps Into in the first dielectric regions 41 (region of the thick frame of black), and have no in the second dielectric regions 42 low Dielectric bumps 50, therefore in this embodiment, only the first dielectric bumps 51 (region of the thick frame of black), And without the second dielectric bumps 52.In this embodiment, second metal layer 62 is formed at the first dielectric bumps 51 On and compound semiconductor substrate 10 on.

The embodiment of Fig. 1 P and Fig. 1 Q is referred to again, then there are different change types respectively in these embodiments Multiple overlapping regions 31, and these multiple overlapping regions 31 are apart from all very close.Therefore in these enforcements In example, the surrounding adjacent regions 32 of each overlapping region 31 can mutually cover other overlapping regions 31 And the surrounding adjacent regions 32 of other overlapping regions 31.Thus, by these multiple overlapping regions 31 with And the neighbouring crossover region 33 that the surrounding adjacent regions 32 of these multiple overlapping regions 31 are constituted, it is one group Close region.Fig. 1 P are first referred to, Fig. 1 P are a kind of circuit cloth of compound semiconductor integrated circuit of the invention The top view of the still another embodiment of office's method.One compound semiconductor integrated circuit layout 1 delimited in The upper surface of the (not shown) of one compound semiconductor substrate 10, the wherein integrated electricity of compound semiconductor Road layout 1 includes one first circuit layout 21 and a second circuit layout 22.One the first metal layer 61 is formed In the region of the first circuit layout 21.21 points of wherein the first circuit layout is three regions, therefore first Metal level 61 be respectively formed as the first metal layer firstth area 611, secondth area of the first metal layer 612 and The area 613 of one the first metal layer the 3rd.The wherein area of the region of the first circuit layout 21 and second circuit layout 22 Domain overlaps in an overlapping region 31, wherein the surrounding adjacent regions of overlapping region 31 and overlapping region 31 32 form one adjacent to crossover region 33.In this embodiment overlapping region 31 is divided into three regions, respectively One overlapping region the firstth area 311, overlapping region secondth area 312 and the area 313 of an overlapping region the 3rd.By It is very close in this three overlapping regions 31, therefore this three overlapping regions 31 and its surrounding adjacent regions 32 form neighbouring crossover region 33 as depicted.In this embodiment, neighbouring crossover region 33 is one Combination zone, the combination zone includes：The firstth area of overlapping region 311, the secondth area of overlapping region 312, weight The area 313 of folded region the 3rd, the surrounding adjacent regions in the firstth area of overlapping region 311, the secondth area of overlapping region 312 Surrounding adjacent regions and the area 313 of overlapping region the 3rd surrounding adjacent regions.One first dielectric regions 41 (region of the thick frame of black) delimited in the upper surface of the (not shown) of compound semiconductor substrate 10, Wherein the first dielectric regions 41 are located within neighbouring crossover region 33, and the first dielectric regions 41 and at least portion Point overlapping region 31 overlaps, and (in this embodiment, the first dielectric regions 41 are comprising the area of overlapping region first 311st, the secondth area of overlapping region 312 and the area 313 of overlapping region the 3rd).In addition, one second dielectric regions First dielectric regions 41 of 42 upper surfaces for being defined as the (not shown) of compound semiconductor substrate 10 are (black The region of the thick frame of color) beyond region.The low dielectric bumps 50 that one dielectric materials are constituted are formed at On the (not shown) of compound semiconductor substrate 10 and on the first metal layer 61.Here is implemented In example, low dielectric bumps 50 are formed only in the first dielectric regions 41 (region of the thick frame of black), and Low dielectric bumps 50 are had no in second dielectric regions 42.Low Jie being wherein formed in the first dielectric regions 41 Electric projection 50 is one first dielectric bumps 51, wherein the first dielectric bumps 51 have one first dielectric bumps The (not shown) of thickness 53.Therefore in this embodiment, only the first dielectric bumps 51 (the thick frame of black Region), and without the second dielectric bumps 52.One second metal layer 62 is formed at the area of second circuit layout 22 In domain.In this embodiment, second metal layer 62 is formed on the first dielectric bumps 51 and compound On semiconductor substrate 10.Additionally, the present embodiment another kind change type embodiment, its primary structure and sheet Embodiment is roughly the same, but, wherein low dielectric bumps 50 be formed at simultaneously in the first dielectric regions 41 and In second dielectric regions 42, wherein the low dielectric bumps 50 being formed in the second dielectric regions 42 are one second Dielectric bumps 52, wherein the second dielectric bumps 52 have the (not shown) of thickness 54 of one second dielectric bumps, And the (not shown) of thickness 54 of the dielectric bumps of wherein at least part second is less than the thickness of the first dielectric bumps 53 (not shown)s.Second metal layer 62 is then formed on the first dielectric bumps 51 and the second dielectric is convex On block 52.

Fig. 1 Q are referred to, Fig. 1 Q are a kind of circuit arrangement method of compound semiconductor integrated circuit of the invention Still another embodiment top view.In this embodiment, 21 points of the first circuit layout is two regions, Therefore the first metal layer 61 is respectively formed as the first metal layer firstth area 611 and a first metal layer the Two areas 612.Wherein the region of the first circuit layout 21 and the region of second circuit layout 22 are in an overlapping region 31 overlap, wherein the surrounding adjacent regions 32 of overlapping region 31 and overlapping region 31 formed one it is neighbouring across Connect region 33.In this embodiment overlapping region 31 is divided into two regions, respectively an overlapping region first The secondth area of 311 and one overlapping region of area 312.Due to this two overlapping regions 31 it is very close, therefore this Two overlapping regions 31 and its surrounding adjacent regions 32 form neighbouring crossover region 33 as depicted. In this embodiment, neighbouring crossover region 33 is a combination zone, and the combination zone includes：Overlapping region First area 311, the secondth area of overlapping region 312, the surrounding adjacent regions in the firstth area of overlapping region 311 and weight The surrounding adjacent regions in the secondth area of folded region 312.One first dielectric regions 41 (region of the thick frame of black) quilt Delimit in the upper surface of the (not shown) of compound semiconductor substrate 10, wherein the first dielectric regions 41 Within neighbouring crossover region 33, and the first dielectric regions 41 overlap with least partially overlapped region 31 (in this embodiment, the first dielectric regions 41 are comprising the firstth area of overlapping region 311 and overlapping region second Area 312).

Fig. 2 is referred to, Fig. 2 is a kind of circuit arrangement method stream of compound semiconductor integrated circuit of the invention Cheng Tu.The circuit arrangement method is comprised the following steps：(please refer to Fig. 1, Figure 1A, Fig. 1 D, figure 1E, Fig. 1 H, Fig. 1 I, Fig. 1 L and Fig. 1 M) A1：Delimit a compound semiconductor integrated circuit layout 1 In the upper surface of a compound semiconductor substrate 10, wherein compound semiconductor integrated circuit layout 1 includes one First circuit layout 21 and a second circuit layout 22, wherein the region and second of the first circuit layout 21 The region of circuit layout 22 overlaps in an overlapping region 31, and one is defined as comprising weight adjacent to crossover region 33 The surrounding adjacent regions 32 of folded region 31 and overlapping region 31；A2：Delimit one first dielectric regions 41 (black The region of the thick frame of color) in the upper surface of compound semiconductor substrate 10, wherein the first dielectric regions 41 are located at Within neighbouring crossover region 33, and the first dielectric regions 41 overlap with least partially overlapped region 31, its Region beyond first dielectric regions 41 of the upper surface of middle compound semiconductor substrate 10 is defined as one second Dielectric regions 42；A3：A first metal layer 61 is formed in the region of the first circuit layout 21；A4：Shape The low dielectric bumps 50 that Cheng Youyi dielectric materials are constituted, wherein low dielectric bumps 50 are formed at simultaneously In first dielectric regions 41 and the second dielectric regions 42 (such as Fig. 1, Figure 1A), the first dielectric regions 41 Interior low dielectric bumps 50 are defined as one first dielectric bumps 51 (region of the thick frame of black), the first dielectric Projection 51 has the thickness 53 of one first dielectric bumps, and the low dielectric bumps 50 in the second dielectric regions 42 are determined Justice is one second dielectric bumps 52, and the second dielectric bumps 52 have the thickness 54 of one first dielectric bumps, its In the second dielectric bumps thickness 54 be not more than the first dielectric bumps thickness 53, and it is at least part of second be situated between Thickness 53 of the thickness 54 of electric projection less than the first dielectric bumps (such as Fig. 1, Figure 1A)；And A5：Shape Into a second metal layer 62 in the region of second circuit layout 22.Thereby, compound semiconductor collection is improved Into the humidity-proof ability of circuit 1.

Fig. 2A is referred to, Fig. 2A is a kind of circuit arrangement method of compound semiconductor integrated circuit of the invention Flow chart.The circuit arrangement method is comprised the following steps：(please refer to Figure 1B, Fig. 1 C, Fig. 1 F, Fig. 1 G, Fig. 1 J, Fig. 1 K, Fig. 1 N and Fig. 1 O) B1：Delimit a compound semiconductor integrated circuit cloth In the upper surface of a compound semiconductor substrate 10, wherein compound semiconductor integrated circuit layout 1 is wrapped for office 1 Include one first circuit layout 21 and a second circuit layout 22, wherein the region of the first circuit layout 21 with The region of second circuit layout 22 overlaps in an overlapping region 31, and one is defined as bag adjacent to crossover region 33 Surrounding adjacent regions 32 containing overlapping region 31 and overlapping region 31；B2：Delimit one first dielectric regions 41 (regions of the thick frame of black) in the upper surface of compound semiconductor substrate 10, wherein the first dielectric regions 41 are located within neighbouring crossover region 33, and the first dielectric regions 41 are mutually overlap with least partially overlapped region 31 Folded, wherein the region beyond the first dielectric regions 41 of the upper surface of compound semiconductor substrate 10 is defined as One second dielectric regions 42；B3：A first metal layer 61 is formed in the region of the first circuit layout 21； B4：One first dielectric bumps 50 that are made up of a dielectric materials of formation in the first dielectric regions 41 (such as Figure 1B, Fig. 1 C, the region of the thick frame of black), the first dielectric bumps 51 have the thickness of one first dielectric bumps Degree 53；And B5：A second metal layer 62 is formed in the region of second circuit layout 22.Thereby, carry The humidity-proof ability of high compound semiconductor integrated circuit 1.

Fig. 2 B and Fig. 2 C are referred to, Fig. 2 B and Fig. 2 C are respectively a kind of compound semiconductor collection of the invention Into the process step generalized section of the specific embodiment of the circuit arrangement method of circuit.In one embodiment, Wherein form low dielectric bumps 50 in A4 steps to comprise the following steps：(Fig. 2 B) is while in the first dielectric regime One first low dielectric layer 71 is formed in the dielectric regions 42 of domain 41 and second, wherein the first low dielectric layer 71 Thickness is equal to the thickness 54 of the second dielectric bumps；And (Fig. 2 C) forms one in the first dielectric regions 41 Second low dielectric layer 72, wherein the thickness of the second low dielectric layer 72 adds thickness 54 of the second dielectric bumps etc. In the thickness 53 of the first dielectric bumps.Wherein form the first low dielectric layer 71 and the second low dielectric layer 72 Material is identical with the dielectric materials for forming low dielectric bumps 50.

Fig. 2 B, Fig. 2 C and Fig. 2 D are referred to, it is a kind of that Fig. 2 B, Fig. 2 C and Fig. 2 D are respectively the present invention The process step section of the specific embodiment of the circuit arrangement method of compound semiconductor integrated circuit is illustrated Figure.In another embodiment, low dielectric bumps 50 are formed in the step of wherein A4 to comprise the following steps：(figure 2B) while forming one first low dielectric layer 71 in the first dielectric regions 41 and the second dielectric regions 42, Wherein the thickness of the first low dielectric layer 71 is equal to the thickness 54 of the second dielectric bumps；(Fig. 2 D) is while in One second low dielectric layer 72 is formed in one dielectric regions 41 and the second dielectric regions 42, wherein first low Jie Thickness etc. of the thickness thickness 54 of the second dielectric bumps (be equal to) of electric layer 71 plus the second low dielectric layer 72 In the thickness 53 of the first dielectric bumps；And (Fig. 2 C) removes second in the way of exposure imaging or etching The second low dielectric layer 72 in dielectric regions 42 so that the first low dielectric layer is only remained in the second dielectric regions 42 The thickness of the first low dielectric layer 71 in 71, and the second dielectric regions 42 is the thickness 54 of the second dielectric bumps. Wherein form the material and the low dielectric bumps 50 of formation of the first low dielectric layer 71 and the second low dielectric layer 72 Dielectric materials are identical.

Fig. 2 E and Fig. 2 F are referred to, Fig. 2 E and Fig. 2 F are respectively a kind of compound semiconductor collection of the invention Into the process step generalized section of the specific embodiment of the circuit arrangement method of circuit.In another embodiment In, the step of wherein A4 in form low dielectric bumps 50 and comprise the following steps：(Fig. 2 E) is while in first Low dielectric bumps 50 are formed in the dielectric regions 42 of dielectric regions 41 and second, wherein low dielectric bumps 50 Thickness 55 is equal to the thickness 53 of the first dielectric bumps；And the second dielectric of (Fig. 2 F) exposure imaging or etching Low dielectric bumps 50 in region 42 so that the thickness of the low dielectric bumps 50 in the first dielectric regions 41 is The thickness of the low dielectric bumps 50 in the thickness 53 of the first dielectric bumps, and the second dielectric regions 42 is second The thickness 54 of dielectric bumps.

Fig. 2 E and Fig. 2 F are referred to, it is respectively a kind of electricity of compound semiconductor integrated circuit of the invention The process step generalized section of the specific embodiment of road layout method.In another embodiment, wherein A4 The step of in form low dielectric bumps 50 and comprise the following steps：(Fig. 2 E) is while in the first dielectric regions 41 And second form low dielectric bumps 50 in dielectric regions 42, wherein the thickness 55 of low dielectric bumps 50 is more than The thickness 53 of the first dielectric bumps；And (Fig. 2 F) exposure imaging or etching the first dielectric regions 41 and Low dielectric bumps 50 in second dielectric regions 42 so that the low dielectric bumps 50 in the first dielectric regions 41 Thickness be the first dielectric bumps thickness 53, and the thickness of the low dielectric bumps 50 in the second dielectric regions 42 Spend the thickness 54 for the second dielectric bumps.

Fig. 2 E and Fig. 2 G are referred to, Fig. 2 E and Fig. 2 G are respectively a kind of compound semiconductor collection of the invention Into the process step generalized section of the specific embodiment of the circuit arrangement method of circuit.In another embodiment In, the step of wherein B4 in form the first dielectric bumps 51 and comprise the following steps：(Fig. 2 E) is while in A low dielectric bumps 50 are formed in one dielectric regions 41 and the second dielectric regions 42, wherein low dielectric bumps 50 thickness 55 is equal to the thickness 53 of the first dielectric bumps；And (Fig. 2 G) exposure imaging or etching are removed Low dielectric bumps 50 in second dielectric regions 42 so that the low dielectric bumps 50 in the first dielectric regions 41 Thickness be the first dielectric bumps thickness 53, and the thickness of the low dielectric bumps 50 in the second dielectric regions 42 Degree is zero.

Fig. 2 E and Fig. 2 G are referred to, Fig. 2 E and Fig. 2 G are respectively a kind of compound semiconductor collection of the invention Into the process step generalized section of the specific embodiment of the circuit arrangement method of circuit.In another embodiment In, the step of wherein B4 in form the first dielectric bumps 51 and comprise the following steps：(Fig. 2 E) is while in A low dielectric bumps 50 are formed in one dielectric regions 41 and the second dielectric regions 42, wherein low dielectric bumps Thickness 53 of 50 thickness 55 more than the first dielectric bumps；And (Fig. 2 G) exposure imaging or etching first Low dielectric bumps 50 in dielectric regions 41, and exposure imaging or etching remove in the second dielectric regions 42 Low dielectric bumps 50 so that the thickness of the low dielectric bumps 50 in the first dielectric regions 41 is that the first dielectric is convex The thickness of the low dielectric bumps 50 in the thickness 53 of block, and the second dielectric regions 42 is zero.

Fig. 2 H are referred to, Fig. 2 H are a kind of circuit arrangement method of compound semiconductor integrated circuit of the invention Another specific embodiment profile.Its primary structure is with the embodiment shown in Fig. 1 and Figure 1A substantially It is identical, but, wherein also include that insulating barrier 75 is formed on compound semiconductor substrate 10, and under Insulating barrier 75 is formed under the first metal layer 61 and under low dielectric bumps 50.Wherein constitute lower insulation The material of layer 75 includes at least one selected from following group：Silicon nitride (SiN) and silicon oxide (SiO₂)。 Its main method is roughly the same with the embodiment shown in Fig. 2, but, wherein also including before the step of A3 One the step of form insulating barrier 75 so that lower insulating barrier 75 be formed at compound semiconductor substrate 10 it On, and lower insulating barrier 75 is formed under the first metal layer 61 and under low dielectric bumps 50.Another In embodiment, the structure (not shown) of insulating barrier 75 under plural layer can be included.

Fig. 2 I are referred to, Fig. 2 I are a kind of circuit arrangement method of compound semiconductor integrated circuit of the invention The profile of still another embodiment.Its primary structure is roughly the same with the embodiment shown in Fig. 2 H, but, Wherein low dielectric bumps 50 are formed only in the first dielectric regions 41, and are had no in the second dielectric regions 42 Low dielectric bumps 50, thus in this embodiment, only the first dielectric bumps 51, and it is convex without the second dielectric Block 52.In another embodiment, the structure (not shown) of insulating barrier 75 under plural layer can be included. Its main method is roughly the same with the embodiment shown in Fig. 2A, but, wherein also including before the step of B3 One the step of form insulating barrier 75 so that lower insulating barrier 75 be formed at compound semiconductor substrate 10 it On, and lower insulating barrier 75 be formed under the first metal layer 61 and the first dielectric bumps 51 under.

Fig. 2 J are referred to, Fig. 2 J are a kind of circuit arrangement method of compound semiconductor integrated circuit of the invention Still another embodiment profile.Its primary structure is with the embodiment shown in Fig. 1 and Figure 1A substantially It is identical, but, wherein also including on one that insulating barrier 76 is formed on compound semiconductor substrate 10 and the On one metal level 61, and upper insulating barrier 76 is formed under low dielectric bumps 50.Insulate on wherein constituting The material of layer 76 includes at least one selected from following group：Silicon nitride (SiN) and silicon oxide (SiO₂)。 Its main method is roughly the same with the embodiment shown in Fig. 2, but, wherein the step of A3 and A4 step The step of also including insulating barrier 76 in a formation one between rapid so that upper insulating barrier 76 is formed at compound half On conductor substrate 10 and on the first metal layer 61, and upper insulating barrier 76 is formed at low dielectric bumps 50 Under.In another embodiment, the structure (not shown) of insulating barrier 76 in plural layer can be included.

Fig. 2 K are referred to, Fig. 2 K are a kind of circuit arrangement method of compound semiconductor integrated circuit of the invention Another specific embodiment profile.Its primary structure is roughly the same with the embodiment shown in Fig. 2 J, but, Wherein low dielectric bumps 50 are formed only in the first dielectric regions 41, and are had no in the second dielectric regions 42 Low dielectric bumps 50, thus in this embodiment, only the first dielectric bumps 51, and it is convex without the second dielectric Block 52.In another embodiment, the structure (not shown) of insulating barrier 76 in plural layer can be included. Its main method is roughly the same with the embodiment shown in Fig. 2A, but, wherein the step of B3 and B4 step The step of also including insulating barrier 76 in a formation one between rapid so that upper insulating barrier 76 is formed at compound half On conductor substrate 10 and on the first metal layer 61, and upper insulating barrier 76 is formed at the first dielectric bumps Under 51.

Fig. 2 L are referred to, Fig. 2 L are a kind of circuit arrangement method of compound semiconductor integrated circuit of the invention Still another embodiment profile.Its primary structure is roughly the same with the embodiment shown in Fig. 2 J, but, Wherein also include that insulating barrier 75 is formed on compound semiconductor substrate 10, and the shape of lower insulating barrier 75 Into under the first metal layer 61 and under low dielectric bumps 50.Wherein constitute the material of lower insulating barrier 75 Including selected from following group at least one：Silicon nitride (SiN) and silicon oxide (SiO₂).Its is main Method is roughly the same with the method for forming the embodiment shown in Fig. 2 J, but, wherein before the step of A3 also The step of insulating barrier 75 being formed including one so that lower insulating barrier 75 is formed at compound semiconductor substrate On 10, and lower insulating barrier 75 is formed under the first metal layer 61 and under low dielectric bumps 50. In another embodiment, the structure (not shown) of insulating barrier 76 in plural layer can be included.In another reality In applying example, the structure (not shown) of insulating barrier 75 under plural layer can be included.In another embodiment, Insulating barrier 75 under structure (not shown) that can be simultaneously comprising insulating barrier 76 in plural layer and plural layer Structure (not shown).

Fig. 2 M are referred to, Fig. 2 M are a kind of circuit layout side of compound semiconductor integrated circuit of the invention The profile of the still another embodiment of method.Its primary structure is roughly the same with the embodiment shown in Fig. 2 L, But, wherein low dielectric bumps 50 are formed only in the first dielectric regions 41, and in the second dielectric regions 42 Have no low dielectric bumps 50, therefore in this embodiment, only the first dielectric bumps 51, and be situated between without second Electric projection 52.In another embodiment, the structure (not shown) of insulating barrier 76 in plural layer can be included. In another embodiment, the structure (not shown) of insulating barrier 75 under plural layer can be included.Another In embodiment, the structure (not shown) and plural layer of insulating barrier 76 in plural layer can be simultaneously included The structure (not shown) of lower insulating barrier 75.Its main method and the embodiment shown in formation Fig. 2 K Method is roughly the same, but, wherein the step of also forming insulating barrier 75 including one before the step of B3, So that lower insulating barrier 75 is formed on compound semiconductor substrate 10, and lower insulating barrier 75 is formed at first Under metal level 61 and under the first dielectric bumps 51.

Fig. 3 is referred to, Fig. 3 is a kind of circuit arrangement method of compound semiconductor integrated circuit of the invention The schematic top plan view of one specific embodiment.On the chip of a compound semiconductor integrated circuit 1, while in It is low one to be defined in one first dielectric regions 41 (region of the thick frame of black) and one second dielectric regions 42 Dielectric bumps 50, wherein the low dielectric bumps 50 being formed in the first dielectric regions 41 are that one first dielectric is convex Block 51 (region of the thick frame of black), it is one the to be formed at low dielectric bumps 50 in the second dielectric regions 42 Two dielectric bumps 52, wherein the first dielectric bumps 51 have the thickness 53 of one first dielectric bumps, second is situated between Electric projection 52 has the thickness 54 of one second dielectric bumps, and the thickness of the dielectric bumps of wherein at least part second Thickness 53 of the degree 54 less than the first dielectric bumps.In this embodiment, the face shared by the second dielectric bumps 52 Product is very big relative to the ratio of the area shared by the first dielectric bumps 51, therefore, the second dielectric bumps 52 Thickness has significant impact to the humidity-proof ability of compound semiconductor integrated circuit 1.As at least part of second Jie When the thickness 54 of electric projection is less than less than the 90% of the thickness 53 of the first dielectric bumps, you being remarkably reinforced The humidity-proof ability of compound semiconductor integrated circuit 1.And the thickness of the second dielectric bumps 52 is less, then to chemical combination The enhancing of the humidity-proof ability of thing semiconductor integrated circuit 1 has more obvious effect.

Fig. 3 A are referred to, Fig. 3 A are a kind of circuit arrangement method of compound semiconductor integrated circuit of the invention Another specific embodiment schematic top plan view.Its primary structure is roughly the same with the embodiment shown in Fig. 3, But, wherein on the chip of a compound semiconductor integrated circuit 1, it is only (black in one first dielectric regions 41 The region of the thick frame of color) in define low dielectric bumps 50, and have no low dielectric in the second dielectric regions 42 Projection 50, and it is (black for one first dielectric bumps 51 to be formed at the low dielectric bumps 50 in the first dielectric regions 41 The region of the thick frame of color), wherein the first thickness 53 of the dielectric bumps 51 with one first dielectric bumps is (in figure Do not show).Therefore in this embodiment, only the first dielectric bumps 51, and without the second dielectric bumps 52. Due to the embodiment in Fig. 3 A, not the second dielectric bumps 52, therefore the first metal in this embodiment Layer (not shown) in addition to the region covered by the first dielectric bumps 51, remaining first gold medal Category layer (not shown) is not covered by low dielectric bumps 50.This embodiment is also the present invention One of most preferred embodiment, due to there was only the first dielectric bumps 51 without the second dielectric bumps 52, to increasing The humidity-proof ability of reinforcing compound semiconductor integrated circuit 1 has splendid effect.

Fig. 3 B are referred to, Fig. 3 B depict the schematic diagram of the local circuit of Fig. 3 A.One compound semiconductor collection It is included on a compound semiconductor substrate 10 into circuit 1 and forms multiple heteroj unction bipolar transistors (Heterojunction Bipolar Transistor, abbreviation HBT) 80.Being formed in of one the first metal layer 61 On compound semiconductor substrate 10.The first metal layer 61 contains firstth area of the first metal layer 611 and The secondth area of the first metal layer 612, wherein the firstth area of the first metal layer 611 and the secondth area of the first metal layer 612 It is the block being not connected with that is separated from each other.One first dielectric bumps 51 are formed in one first dielectric regions 41 (region of the thick frame of black).In this embodiment, the first dielectric bumps 51 for containing multiple blocks are (black The region of the thick frame of color), and then have no the second dielectric bumps 52 in one second dielectric regions 42.First is situated between Electric projection 51 is formed on the first metal layer 61.One second metal layer 62 is formed at the first dielectric bumps 51 On and compound semiconductor substrate 10 on.Second metal layer 62 contains a second metal layer first The secondth area of second metal layer 622 of area 621 and, wherein second metal layer the firstth area 621 and the second metal The secondth area of floor 622 is the block being not connected with that is separated from each other.Please refer to Fig. 3 C, it is b-b ' in Fig. 3 B The generalized section of the vertical cross-section of hatching.Multiple heteroj unction bipolar transistors are contained in Fig. 3 B 80, each of which heteroj unction bipolar transistor 80 contains an emitter-base bandgap grading 81 (Emitter), a base Pole 82 (Base) and a collector 83 (Collector).Wherein the firstth area of the first metal layer 611 is formed in On the emitter-base bandgap grading 81 of heteroj unction bipolar transistor 80, it is electrical connected with emitter-base bandgap grading 81.The first metal layer Two areas 612 are formed in (not shown) on the base stage 82 of heteroj unction bipolar transistor 80, with base Pole 82 is electrical connected.First dielectric bumps 51 are formed on the firstth area of the first metal layer 611.Second metal The firstth area of floor 621 is formed on the collector 83 of heteroj unction bipolar transistor 80 and the first dielectric is convex On block 51, it is electrical connected with collector 83.By the first dielectric bumps 51 by the first metal of different potentials Floor 61 (area 611 of the first metal layer first) and second metal layer 62 (area 621 of second metal layer first) Isolation.

Fig. 3 D are referred to, Fig. 3 D are a kind of circuit arrangement method of compound semiconductor integrated circuit of the invention Another embodiment cross-section structure generalized section.In Fig. 3 D, a compound semiconductor substrate 10 it On define a heteroj unction bipolar transistor 80 (HBT), heteroj unction bipolar transistor 80 is wrapped An emitter-base bandgap grading 81 (Emitter), a base stage 82 (Base) and a collector 83 (Collector) are contained.Its In a first metal layer 61 be formed on the collector 83 of heteroj unction bipolar transistor 80, with collector 83 It is electrical connected.One first dielectric bumps 51 are formed on the first metal layer 61.The shape of one second metal layer 62 Into on the emitter-base bandgap grading 81 of heteroj unction bipolar transistor 80, on the first dielectric bumps 51 and chemical combination On thing semiconductor substrate 10, and it is electrical connected with emitter-base bandgap grading 81.Will be different electric by the first dielectric bumps 51 The first metal layer 61 and second metal layer 62 of position is isolated.

Fig. 4 is referred to, Fig. 4 is a kind of circuit arrangement method of compound semiconductor integrated circuit of the invention The local circuit schematic layout pattern of one specific embodiment.Please refer to Fig. 4 A, it is to correspond to Fig. 4 In embodiment partial circuit diagram.One compound semiconductor integrated circuit 1 is included in a compound semiconductor On substrate (not shown) formed multiple heteroj unction bipolar transistors 84 (HBT) and One bias circuit heteroj unction bipolar transistor 88.Each of which heteroj unction bipolar transistor 84 An emitter-base bandgap grading 85 (Emitter), a base stage 86 (Base) and a collector 87 (Collector) are contained respectively. Bias circuit heteroj unction bipolar transistor 88 contains an emitter-base bandgap grading 89 (Emitter), a base stage 90 And a collector 91 (Collector) (Base).One the first metal layer 61 is formed in compound semiconductor base On plate (not shown).The first metal layer 61 contains firstth area of the first metal layer 611,1 One metal level the secondth area 612 and the area 613 of a first metal layer the 3rd, the wherein area of the first metal layer first 611st, the secondth area of the first metal layer 612 and the area 613 of the first metal layer the 3rd are separated from each other and are not connected with Block.The firstth area of the first metal layer 611 is electrical connected with the emitter-base bandgap grading 85 of heteroj unction bipolar transistor 84. The secondth area of the first metal layer 612 is electrical connected with the base stage 86 of heteroj unction bipolar transistor 84.First gold medal The category area 613 of floor the 3rd is electrical connected with the base stage 90 of bias circuit heteroj unction bipolar transistor 88.One One dielectric bumps 51 (region of the thick frame of black) are formed in one first dielectric regions 41, wherein first is situated between Electric projection 51 includes two first the firstth areas of dielectric bumps 511, one first the secondth area of dielectric bumps 512, The area 513 of first dielectric bumps the 3rd and other areas 514 of multiple first dielectric bumps.In this embodiment, Region beyond first dielectric regions 41 is one second dielectric regions 42, and the is had no in the second dielectric regions 42 Two dielectric bumps 52.First dielectric bumps 51 are formed on the first metal layer 61.One second metal layer 62 It is formed on the first dielectric bumps 51 and on compound semiconductor substrate 10.Second metal layer 62 is wrapped Second metal layer firstth area 621 and secondth area of second metal layer 622, wherein second metal layer are contained First area 621 and the secondth area of second metal layer 622 are the blocks being not connected with that is separated from each other.Second metal The firstth area of floor 621 is electrical connected with the collector 87 of heteroj unction bipolar transistor 84.Second metal layer second Area 622 is electrical connected with the collector 91 of bias circuit heteroj unction bipolar transistor 88.

The firstth area of two overlapping regions 311 in Fig. 4 and Fig. 4 A be the firstth area of the first metal layer 611 with And the equitant region in the firstth area of second metal layer 621.Firstth area of the first metal layer 611 of different potentials with And the firstth area of second metal layer 621 passes through the first the firstth area of dielectric bumps 511 (region of the thick frame of black) shape Into bridging, thereby isolate the firstth area of the first metal layer 611 and the firstth area of second metal layer 621.But The compound semiconductor of the surrounding adjacent regions in the firstth area of overlapping region 311 and the firstth area of overlapping region 311 The size of one impedance (Impedance) of integrated circuit 1 can be subject to first the firstth area of dielectric bumps 511 One dielectric of thickness, area and shape and the dielectric materials for forming first the firstth area of dielectric bumps 511 is normal Number etc. factor is affected.Thus the present inventor also develops, if can greatly utilize in overlay region The integrated electricity of compound semiconductor of the surrounding adjacent regions in the firstth area of domain 311 and the firstth area of overlapping region 311 The impedance on road 1 can be affected to be designed the first dielectric of adjustment by first the firstth area of dielectric bumps 511 The thickness in the firstth area of projection 511, area and shape and select to form first the firstth area of dielectric bumps 511 Dielectric constant of dielectric materials etc. mode, to produce the impedance of required size (in overlapping region The compound semiconductor integrated circuit of the surrounding adjacent regions in the first area 311 and the firstth area of overlapping region 311 1 impedance), can will thereby lift the efficiency of compound semiconductor integrated circuit 1.Therefore, the present invention one The circuit arrangement method of compound semiconductor integrated circuit is planted, wherein form the first dielectric bumps 51 also including Below step：According to an impedance institute of the compound semiconductor integrated circuit 1 near neighbouring crossover region 33 Size, decision is needed to correspond to thickness, area and the shape of the first dielectric bumps 51 of neighbouring crossover region 33 One dielectric constant of shape and dielectric materials, to form the first dielectric bumps 51, thereby lifts compound The efficiency of semiconductor integrated circuit 1.

In the embodiment of Fig. 4 and Fig. 4 A, respectively with heteroj unction bipolar transistor 84 and bias Circuit heteroj unction bipolar transistor 88 is power amplifier (main power amplifier) and bias circuit The embodiment of power amplifier.In other embodiments, power amplifier (main power amplifier) and Bias circuit power amplifier is not limited to heteroj unction bipolar transistor, and alternatively bipolar is brilliant The power of body pipe, a field-effect transistor (Field Effect Transistor, abbreviation FET) or other forms Amplifier.Additionally, as the difference of Fig. 3 C and Fig. 3 D, in the embodiment of Fig. 4 and Fig. 4 A, The emitter-base bandgap grading 85 and collector 87 of heteroj unction bipolar transistor 84 respectively with (the first gold medal of the first metal layer 61 Category floor first area 611) and second metal layer 62 (area 621 of second metal layer first) be electrical connected；And In another embodiment, the emitter-base bandgap grading 85 and collector 87 of heteroj unction bipolar transistor 84 can respectively with Two metal levels 62 and the first metal layer 61 are electrical connected.Similarly, in the embodiment of Fig. 4 and Fig. 4 A In, the base stage 86 and bias circuit heteroj unction bipolar transistor of heteroj unction bipolar transistor 84 88 collector 91 respectively with the first metal layer 61 (area 612 of the first metal layer second) and second metal layer 62 (area 622 of second metal layer second) is electrical connected；And in another embodiment, heteroj unction bipolar is brilliant The base stage 86 of body pipe 84 and the collector 91 of bias circuit heteroj unction bipolar transistor 88 can respectively with Two metal levels 62 and the first metal layer 61 are electrical connected.

In the embodiment of Fig. 4 and Fig. 4 A, because of the firstth area of the first metal layer 611 and heteroj unction bipolar The emitter-base bandgap grading 85 of transistor 84 is electrical connected, and the firstth area of second metal layer 621 and heteroj unction bipolar crystal The collector 87 of pipe 84 is electrical connected, therefore in the firstth area of overlapping region 311 and the firstth area of overlapping region 311 The impedance of the compound semiconductor integrated circuit 1 of surrounding adjacent regions is heteroj unction bipolar transistor 84 Collector 87 and emitter-base bandgap grading 85 between an output impedance.Thus, if heteroj unction bipolar can be greatly utilized Output impedance between the collector 87 and emitter-base bandgap grading 85 of transistor 84 can be subject to first the firstth area of dielectric bumps 511 The impact in (region of the thick frame of black) come be designed adjustment first the firstth area of dielectric bumps 511 thickness, The dielectric constant of area and shape and the dielectric materials for selecting to form first the firstth area of dielectric bumps 511 Etc. mode, to produce the collector 87 and emitter-base bandgap grading of the heteroj unction bipolar transistor 84 of required size Output impedance between 85, can thereby lift the efficiency of the compound semiconductor integrated circuit 1.

Therefore, the circuit arrangement method of a kind of compound semiconductor integrated circuit of the invention, also including following The step of：Delimit a power amplifier to be in the layout of in compound semiconductor integrated circuit layout 1；Form a work( Rate amplifier in the region of power amplifier layout, its intermediate power amplifier include a first end, one the Two ends and one the 3rd end, wherein one of first end and the second end for power amplifier an output End.Wherein first end is electrical connected with one of the first metal layer 61 and second metal layer 62, the Two ends are electrical connected with the first metal layer 61 and the wherein another of second metal layer 62 so that power is put The first end of big device and the second end form isolation by the first dielectric bumps 51；And according to neighbouring bridging Size needed for an output impedance between the first end of the power amplifier near region 33 and the second end, certainly Surely thickness, area and shape and low Jie of the first dielectric bumps 51 of neighbouring crossover region 33 are corresponded to One dielectric constant of electric material, to form the first dielectric bumps 51, thereby lifts compound semiconductor integrated The efficiency of circuit 1.In one embodiment, its intermediate power amplifier is that bipolar transistor or one heterogeneous connect Face bipolar transistor, first end is a collector, and the second end is an emitter-base bandgap grading, and the 3rd end is a base stage, its In the output impedance for power amplifier collector and emitter-base bandgap grading between impedance.In another embodiment, its Intermediate power amplifier be a field-effect transistor, first end be one drain electrode, the second end be a source electrode, the 3rd end For a grid, wherein the output impedance for power amplifier drain electrode and source electrode between impedance.

In Fig. 4 and Fig. 4 A, heteroj unction bipolar transistor 84 is a main power amplifier, and inclined Volt circuit heteroj unction bipolar transistor 88 is a bias circuit power amplifier.A wherein overlapping region Second area 312 is the equitant region in the secondth area of the first metal layer 612 and the secondth area of second metal layer 622. Secondth area of the first metal layer 612 and the secondth area of second metal layer 622 of different potentials is convex by the first dielectric The firstth area of block 512 (region of the thick frame of black) forms bridging, thereby isolates the secondth area of the first metal layer 612 And the secondth area of second metal layer 622.But in the secondth area of overlapping region 312 and the area of overlapping region second The size of one impedance of the compound semiconductor integrated circuit 1 of 312 surrounding adjacent regions is to be subject to first The thickness in the firstth area of dielectric bumps 512, area and shape and form first the firstth area of dielectric bumps 512 One dielectric constant of dielectric materials etc. factor is affected.Because the secondth area of the first metal layer 612 connects with heterogeneous The base stage 86 of face bipolar transistor 84 is electrical connected, and the secondth area of second metal layer 622 is different with bias circuit The collector 91 of matter unction bipolar transistors 88 is electrical connected, therefore in the secondth area of overlapping region 312 and overlaps The impedance of the compound semiconductor integrated circuit 1 of the surrounding adjacent regions in the secondth area of region 312 is heterojunction Between the base stage 86 of bipolar transistor 84 and the collector 91 of bias circuit heteroj unction bipolar transistor 88 Impedance, an also as input impedance of heteroj unction bipolar transistor 84.Thus, if can be apt to plus profit The shadow in first the firstth area of dielectric bumps 512 can be subject to the input impedance of heteroj unction bipolar transistor 84 Ring the thickness to be designed first the firstth area of dielectric bumps 512 of adjustment, area and shape and select shape The dielectric constant of dielectric materials into first the firstth area of dielectric bumps 512 etc. mode, with needed for producing One input impedance of the heteroj unction bipolar transistor 84 of size, can thereby lift the compound semiconductor The efficiency of integrated circuit 1.

Therefore, the circuit arrangement method of a kind of compound semiconductor integrated circuit of the invention, also including following Step：Delimit a main power amplifier layout and a bias circuit power amplifier be in the layout of compound half In conductor integrated circuit layout 1；A main power amplifier is formed in the region of main power amplifier layout, Wherein main power amplifier include a main power amplifier first end, second end of main power amplifier and The end of one main power amplifier the 3rd, wherein based on the end of main power amplifier the 3rd power amplifier an input End；A bias circuit power amplifier is formed in the region of bias circuit power amplifier layout, wherein Bias circuit power amplifier includes that a bias circuit power amplifier first end, a bias circuit power are put The big end of device second and the end of a bias circuit power amplifier the 3rd, wherein bias circuit power amplifier the One end is electrical connected with one of the first metal layer 61 and second metal layer 62, main power amplifier 3rd end is electrical connected with the first metal layer 61 and the wherein another of second metal layer 62 so that bias Circuit power amplifier first end and the end of main power amplifier the 3rd by the first dielectric bumps 51 formed every From；And according to the bias circuit power amplifier first end and main power near neighbouring crossover region 33 The required size of the impedance between the end of amplifier the 3rd, decision corresponds to the first of neighbouring crossover region 33 One dielectric constant of the thickness, area and shape and dielectric materials of dielectric bumps 51, to form first Dielectric bumps 51, thereby lift the efficiency of compound semiconductor integrated circuit 1, wherein power based on the impedance One input impedance of amplifier.In one embodiment, wherein main power amplifier and bias circuit power Amplifier is bipolar transistor or a heteroj unction bipolar transistor, main power amplifier first end For a main power amplifier collector, the end of main power amplifier second is a main power amplifier emitter-base bandgap grading, main work( The end of rate amplifier the 3rd is a main power amplifier base stage, and bias circuit power amplifier first end is one inclined Volt circuit power amplifier collector, the end of bias circuit power amplifier second is a bias circuit power amplification Device emitter-base bandgap grading, the end of bias circuit power amplifier the 3rd is a bias circuit power amplifier base stage, wherein should Input impedance is the impedance between bias circuit power amplifier collector and main power amplifier base stage.Another In one embodiment, wherein main power amplifier and bias circuit power amplifier are a field-effect transistor, Main power amplifier first end is a main power amplifier drain electrode, and the end of main power amplifier second is a main work( Rate amplifier source electrode, the end of main power amplifier the 3rd be a main power amplifier grid, bias circuit power Amplifier first end is bias circuit power amplifier drain electrode, and the end of bias circuit power amplifier second is One bias circuit power amplifier source electrode, the end of bias circuit power amplifier the 3rd is a bias circuit power Amplifier grid, the wherein input impedance are that bias circuit power amplifier drains and main power amplifier Impedance between grid.

In Fig. 4 and Fig. 4 A, the area 313 of an overlapping region the 3rd be the area 613 of the first metal layer the 3rd and The equitant region in the secondth area of second metal layer 622.The area 613 of the first metal layer the 3rd of different potentials and The secondth area of second metal layer 622 is formed by the area 513 (region of the thick frame of black) of the first dielectric bumps the 3rd Bridging, thereby isolates the area 613 of the first metal layer the 3rd and the secondth area of second metal layer 622.But in weight The compound semiconductor collection of the surrounding adjacent regions in the area 313 of folded region the 3rd and the area 313 of overlapping region the 3rd Size into an impedance of circuit 1 is to be subject to the thickness in the area 513 of the first dielectric bumps the 3rd, area and shape One dielectric constant of dielectric materials in shape and formation the first dielectric bumps the 3rd area 513 etc. factor institute Affect.Because of the area 613 of the first metal layer the 3rd and the base stage 90 of bias circuit heteroj unction bipolar transistor 88 It is electrical connected, and the collection of the secondth area of second metal layer 622 and bias circuit heteroj unction bipolar transistor 88 Pole 91 is electrical connected, therefore neighbouring around the area 313 of overlapping region the 3rd and the area 313 of overlapping region the 3rd The impedance of the compound semiconductor integrated circuit 1 in region is bias circuit heteroj unction bipolar transistor 88 Base stage 90 and collector 91 between impedance, also as bias circuit heteroj unction bipolar transistor 88 One input impedance.Thus, if the input of bias circuit heteroj unction bipolar transistor 88 can be greatly utilized Impedance can be affected to be designed the first dielectric bumps of adjustment the by the area 513 of the first dielectric bumps the 3rd The low dielectric of the thickness, area and shape and selection formation the first dielectric bumps the 3rd area 513 in three areas 513 Dielectric constant of material etc. mode, it is brilliant with the bias circuit heteroj unction bipolar for producing required size One input impedance of body pipe 88, can thereby lift the efficiency of the compound semiconductor integrated circuit 1.

Therefore, the circuit arrangement method of a kind of compound semiconductor integrated circuit of the invention, also including following Step：Delimit a bias circuit power amplifier to be in the layout of in compound semiconductor integrated circuit layout 1；Shape Into a bias circuit power amplifier in the region of bias circuit power amplifier layout, wherein bias plasma Road power amplifier includes a bias circuit power amplifier first end, a bias circuit power amplifier the Two ends and the end of a bias circuit power amplifier the 3rd, wherein bias circuit power amplifier first end with And one of the end of bias circuit power amplifier the 3rd is an input of bias circuit power amplifier End.Wherein bias circuit power amplifier first end and the first metal layer 61 and second metal layer 62 its One of be electrical connected, the end of bias circuit power amplifier the 3rd and the metal of the first metal layer 61 and second The wherein another of layer 62 is electrical connected so that bias circuit power amplifier first end and bias circuit The end of power amplifier the 3rd forms isolation by the first dielectric bumps 51；And according to neighbouring crossover region 33 Between neighbouring bias circuit power amplifier first end and the end of bias circuit power amplifier the 3rd one is defeated Enter the required size of impedance, decision correspond to the first dielectric bumps 51 of neighbouring crossover region 33 thickness, One dielectric constant of area and shape and dielectric materials, to form the first dielectric bumps 51, thereby carries Rise the efficiency of compound semiconductor integrated circuit 1.In one embodiment, wherein bias circuit power amplifier For bipolar transistor or a heteroj unction bipolar transistor, bias circuit power amplifier first end For a collector, the end of bias circuit power amplifier second is an emitter-base bandgap grading, bias circuit power amplifier the 3rd Hold as a base stage, wherein the input impedance for bias circuit power amplifier collector and base stage between resistance It is anti-.In another embodiment, wherein bias circuit power amplifier be a field-effect transistor, bias circuit Power amplifier first end be one drain electrode, the end of bias circuit power amplifier second be a source electrode, bias plasma The end of road power amplifier the 3rd is a grid, and wherein the input impedance is the leakage of bias circuit power amplifier Impedance between pole and grid.

Please refer to Fig. 4, Fig. 4 A, Fig. 4 B and Fig. 4 C, wherein Fig. 4 B are the c-c ' sections in Fig. 4 The generalized section of the vertical cross-section of line；Fig. 4 C are the partial enlarged drawing in the region of V square frames in Fig. 4 B.Its It is that the region of c in Fig. 4 near c-c ' hatchings is (namely close near the region of V square frames in middle Fig. 4 B Region above c-c ' hatchings).The first metal layer 61 is not connected with comprising being separated from each other in Fig. 4 B the One the firstth area of metal level 611, the secondth area of the first metal layer 612 and area of 613 3, the 3rd area of the first metal layer Block.Second metal layer 62 includes second metal layer the firstth area 621 and the second gold medal being not connected with that be separated from each other 622 two, the secondth area of category floor block.Wherein the first metal layer firstth area 611 of different potentials and the second gold medal The firstth area of category floor 621 forms bridging by first the firstth area of dielectric bumps 511, thereby isolates the first metal layer First area 611 and the firstth area of second metal layer 621.The area 613 of the first metal layer the 3rd of different potentials and The secondth area of second metal layer 622 forms bridging by the first the 3rd area of dielectric bumps 513, thereby isolates first The area 613 of metal level the 3rd and the secondth area of second metal layer 622.In Fig. 4 B and Fig. 4 C, once insulating barrier 75 are formed on compound semiconductor substrate 10；The first metal layer 61 (includes the area of the first metal layer first 611st, the secondth area of the first metal layer 612 and the area 613 of the first metal layer the 3rd) it is formed on insulating barrier 75； Insulating barrier 76 is formed on the first metal layer 61 and on compound semiconductor substrate 10 on one；First Dielectric bumps 51 (comprising first dielectric bumps the firstth area 511 and the area 513 of the first dielectric bumps the 3rd) shape Into in the first dielectric regions 41 on insulating barrier 76；Second metal layer 62 (includes second metal layer First area 621 and the area 622 of second metal layer second) it is formed on the first dielectric bumps 51 and upper exhausted On edge layer 76；One protective layer 77 is formed on second metal layer 62, on the first dielectric bumps 51 with And on upper insulating barrier 76.

A kind of circuit arrangement method (enforcement as shown in Figure 2 of compound semiconductor integrated circuit of the present invention Example), wherein also including that one forms an at least protective layer 77 in the compound semiconductor after the step of A5 The step of on integrated circuit 1.In one embodiment, wherein protective layer 77 is formed at second metal layer 62 On.In another embodiment, protective layer 77 is also formed on the second dielectric bumps 52.In another reality In applying example, protective layer 77 is also formed on the first dielectric bumps 51.In another embodiment, protective layer 77 are also formed on the first metal layer 61.In another embodiment, protective layer 77 is also formed in compound On semiconductor substrate 10.The material of wherein composition protective layer 77 includes at least one selected from following group： Polybenzoxazoles (polybenzoxazole, abbreviation PBO), silicon nitride (SiN) and silicon oxide (SiO₂)。

A kind of circuit arrangement method (enforcement as shown in Figure 2 A of compound semiconductor integrated circuit of the present invention Example), wherein also including that one forms an at least protective layer 77 in the compound semiconductor after the step of B5 The step of on integrated circuit 1.In one embodiment, wherein protective layer 77 is formed at second metal layer 62 On.In another embodiment, protective layer 77 is also formed on the first dielectric bumps 51.In another reality In applying example, protective layer 77 is also formed on the first metal layer 61.In another embodiment, protective layer 77 It is also formed on compound semiconductor substrate 10.Wherein constituting the material of protective layer 77 is included selected from following At least one of group：Polybenzoxazoles (polybenzoxazole, abbreviation PBO), silicon nitride (SiN) And silicon oxide (SiO₂)。

Finally it should be noted that：Various embodiments above is only illustrating technical scheme rather than right Its restriction；Although being described in detail to the present invention with reference to foregoing embodiments, this area it is common Technical staff should be understood：It still can modify to the technical scheme described in foregoing embodiments, Either equivalent is carried out to which part or all technical characteristic；And these modifications or replacement, and The scope of the essence disengaging various embodiments of the present invention technical scheme of appropriate technical solution is not made.

Claims

1. a kind of circuit arrangement method of compound semiconductor integrated circuit, it is characterised in that including following Step：

A1：A compound semiconductor integrated circuit layout delimited in the upper table of a compound semiconductor substrate Face, wherein the compound semiconductor integrated circuit layout is electric including one first circuit layout and one second Road layout, wherein the region of first circuit layout is Chong Die one with the region of the second circuit layout Region overlaps, and one is defined as comprising the overlapping region and the overlapping region adjacent to crossover region Surrounding adjacent regions；

A2：One first dielectric regions delimited in the upper surface of the compound semiconductor substrate, wherein described First dielectric regions are located within the neighbouring crossover region, and first dielectric regions with it is at least part of The overlapping region overlaps, wherein first dielectric of the upper surface of the compound semiconductor substrate Region beyond region is defined as one second dielectric regions；

A3：A first metal layer is formed in the region of first circuit layout；

A4：The low dielectric bumps that formation is made up of a dielectric materials, wherein the low dielectric bumps It is formed in first dielectric regions and second dielectric regions, in first dielectric regions simultaneously Described low dielectric bumps be defined as one first dielectric bumps, described low Jie in second dielectric regions Electric projection is defined as one second dielectric bumps, wherein the thickness of second dielectric bumps is not more than described The thickness of one dielectric bumps, and the thickness of at least part of second dielectric bumps is less than described first Jie The thickness of electric projection；And

A5：A second metal layer is formed in the region of the second circuit layout.

2. the circuit arrangement method of compound semiconductor integrated circuit according to claim 1, it is special Levy and be, the dielectric materials have a water absorption rate less than 5%.

3. the circuit arrangement method of compound semiconductor integrated circuit according to claim 1, it is special Levy and be, the dielectric materials include at least one selected from following group：Polybenzoxazoles PBO with And benzocyclobutane BCB.

4. the circuit arrangement method of compound semiconductor integrated circuit according to claim 1, it is special Levy and be, in A4 steps, form the low dielectric bumps and comprise the following steps：

Form one first low dielectric layer in first dielectric regions and second dielectric regions simultaneously, The thickness of wherein described first low dielectric layer is equal to the thickness of second dielectric bumps；And

One second low dielectric layer is formed in first dielectric regions, wherein second low dielectric layer Thickness is equal to the thickness of first dielectric bumps plus the thickness of first low dielectric layer.

5. the circuit arrangement method of compound semiconductor integrated circuit according to claim 1, it is special Levy and be, in A4 steps, wherein form the low dielectric bumps comprising the following steps：

Form one first low dielectric layer in first dielectric regions and second dielectric regions simultaneously, The thickness of wherein described first low dielectric layer is equal to the thickness of second dielectric bumps；

Form the described second low dielectric in first dielectric regions and second dielectric regions simultaneously Layer, wherein the thickness of second low dielectric layer is equal to described the plus the thickness of first low dielectric layer The thickness of one dielectric bumps；And

Exposure imaging etches to remove second low dielectric layer in second dielectric regions.

6. the circuit arrangement method of compound semiconductor integrated circuit according to claim 1, it is special Levy and be, in A4 steps, form the low dielectric bumps and comprise the following steps：

Simultaneously the low dielectric bumps are formed in first dielectric regions and second dielectric regions, The thickness of wherein described low dielectric bumps is equal to the thickness of first dielectric bumps；And

Described low dielectric bumps in exposure imaging or etching second dielectric regions so that described first The thickness of the described low dielectric bumps in dielectric regions is the thickness of first dielectric bumps, and described The thickness of the described low dielectric bumps in two dielectric regions is the thickness of second dielectric bumps.

7. the circuit arrangement method of compound semiconductor integrated circuit according to claim 1, it is special Levy and be, in A4 steps, form the low dielectric bumps and comprise the following steps：

Form the low dielectric bumps in first dielectric regions and second dielectric regions simultaneously； And

Exposure imaging etches first dielectric regions and the described low dielectric in second dielectric regions Projection so that the thickness of the described low dielectric bumps in first dielectric regions is that first dielectric is convex The thickness of the described low dielectric bumps in the thickness of block, and second dielectric regions is second dielectric The thickness of projection.

8. the circuit arrangement method of compound semiconductor integrated circuit according to claim 1, it is special Levy and be, the surrounding adjacent regions of the overlapping region include 50 μm arround the overlapping region of scope Within region.

9. the circuit arrangement method of compound semiconductor integrated circuit according to claim 1, it is special Levy and be, the dielectric constant of the dielectric materials is less than 7.

10. the circuit layout of the compound semiconductor integrated circuit according to any one of claim 1 to 9 Method, it is characterised in that form first dielectric bumps further comprising the steps of：According to described neighbouring Size needed for one impedance of the compound semiconductor integrated circuit near crossover region, determines corresponding Thickness, area and shape and low Jie in first dielectric bumps of the neighbouring crossover region One dielectric constant of electric material, to form first dielectric bumps, thereby lifts the compound and partly leads The efficiency of body integrated circuit.

The circuit layout of the 11. compound semiconductor integrated circuits according to any one of claim 1 to 9 Method, it is characterised in that further comprising the steps of：

Delimit a power amplifier to be in the layout of in the compound semiconductor integrated circuit layout；

A power amplifier is formed in the region of the power amplifier layout, wherein the power amplification Device includes a first end, one second end and one the 3rd end, wherein the first end and second end One of them is an outfan of the power amplifier, wherein the first end and the first metal layer And one of the second metal layer is electrical connected, second end and the first metal layer and institute State the therein another of second metal layer to be electrical connected so that the first end of the power amplifier and Second end forms isolation by first dielectric bumps；And

According to the first end and described the of the power amplifier near the neighbouring crossover region Size needed for an output impedance between two ends, decision corresponds to described the first of the neighbouring crossover region One dielectric constant of the thickness, area and shape and the dielectric materials of dielectric bumps, to be formed The first dielectric bumps are stated, the efficiency of the compound semiconductor integrated circuit is thereby lifted.

The circuit arrangement method of 12. compound semiconductor integrated circuits according to claim 11, its It is characterised by, the power amplifier is bipolar transistor or a heteroj unction bipolar transistor, The first end is a collector, and second end is an emitter-base bandgap grading, and the 3rd end is a base stage, wherein institute State the impedance between the collector and the emitter-base bandgap grading that output impedance is the power amplifier.

The circuit arrangement method of 13. compound semiconductor integrated circuits according to claim 11, its It is characterised by, the power amplifier is a field-effect transistor, the first end is one to drain, described the Two ends are a source electrode, and the 3rd end is a grid, wherein the output impedance is the power amplifier The drain electrode and the source electrode between impedance.

The circuit layout of the 14. compound semiconductor integrated circuits according to any one of claim 1 to 9 Method, it is characterised in that further comprising the steps of：

Delimit a main power amplifier layout and a bias circuit power amplifier be in the layout of the compound In semiconductor integrated circuit layout；

A main power amplifier is formed in the region of the main power amplifier layout, wherein the main work( Rate amplifier includes a main power amplifier first end, second end of main power amplifier and a main power The end of amplifier the 3rd, wherein the end of main power amplifier the 3rd is an input of the main power amplifier End；

A bias circuit power amplifier is formed in the region of the bias circuit power amplifier layout, Wherein described bias circuit power amplifier includes a bias circuit power amplifier first end, a bias plasma The end of road power amplifier second and the end of a bias circuit power amplifier the 3rd, wherein the bias circuit Power amplifier first end and the electrical phase of one of the first metal layer and the second metal layer Even, the end of main power amplifier the 3rd and the first metal layer and the second metal layer wherein it It is another to be electrical connected so that the bias circuit power amplifier first end and the main power amplifier Three ends form isolation by first dielectric bumps；And

According to the bias circuit power amplifier first end near the neighbouring crossover region and described Size needed for an impedance between the end of main power amplifier the 3rd, decision corresponds to the neighbouring crossover region First dielectric bumps thickness, area and shape and the dielectric materials a dielectric constant, To form first dielectric bumps, the efficiency of the compound semiconductor integrated circuit is thereby lifted, its Described in impedance be the main power amplifier an input impedance.

The circuit arrangement method of 15. compound semiconductor integrated circuits according to claim 14, its It is characterised by, the main power amplifier and the bias circuit power amplifier are bipolar crystal Pipe or a heteroj unction bipolar transistor, the main power amplifier first end is a main power amplifier Collector, the end of main power amplifier second be a main power amplifier emitter-base bandgap grading, the main power amplifier 3rd end is a main power amplifier base stage, and the bias circuit power amplifier first end is a bias plasma Road power amplifier collector, the end of bias circuit power amplifier second is a bias circuit power amplification Device emitter-base bandgap grading, the end of bias circuit power amplifier the 3rd is a bias circuit power amplifier base stage, its Described in input impedance be between the bias circuit power amplifier collector and the main power amplifier base stage Impedance.

The circuit arrangement method of 16. compound semiconductor integrated circuits according to claim 14, its It is characterised by, the main power amplifier and the bias circuit power amplifier are a field-effect transistor, The main power amplifier first end is that a main power amplifier drains, the end of main power amplifier second For a main power amplifier source electrode, the end of main power amplifier the 3rd is a main power amplifier grid, The bias circuit power amplifier first end is bias circuit power amplifier drain electrode, the bias plasma The end of road power amplifier second be a bias circuit power amplifier source electrode, the bias circuit power amplification The end of device the 3rd is a bias circuit power amplifier grid, wherein the input impedance is the bias circuit Impedance between power amplifier drain electrode and the main power amplifier grid.

The circuit arrangement method of 17. compound semiconductor integrated circuits according to claim 1, it is special Levy and be, between A3 steps and A4 steps also include one formed at least one on insulating barrier the step of, its Described at least one insulating barrier be formed on the compound semiconductor substrate and first metal On layer, and insulating barrier is formed under the low dielectric bumps on described at least one.

The circuit arrangement method of 18. compound semiconductor integrated circuits according to claim 17, its Be characterised by, constitute the material of insulating barrier on described at least include being selected from following group at least one： Silicon nitride SiN and silicon oxide sio₂。

The circuit arrangement method of 19. compound semiconductor integrated circuits according to claim 1, it is special Levy and be, before A3 steps also include one formed at least insulating barrier once the step of, wherein it is described at least Once insulating barrier is formed on the compound semiconductor substrate, and described at least once insulating barrier is formed Under the first metal layer and under the low dielectric bumps.

The circuit arrangement method of 20. compound semiconductor integrated circuits according to claim 19, its It is characterised by, constitutes that described at least once the material of insulating barrier includes being selected from least one of following group： Silicon nitride SiN and silicon oxide sio₂。

The circuit arrangement method of 21. compound semiconductor integrated circuits according to claim 1, it is special Levy and be, also include that a formation at least protective layer is integrated in the compound semiconductor after A5 steps The step of on circuit.

The circuit arrangement method of 22. compound semiconductor integrated circuits according to claim 21, its It is characterised by, the material of an at least protective layer described in composition includes at least one selected from following group：It is poly- Benzoxazoles PBO, silicon nitride SiN and silicon oxide sio₂。

A kind of 23. circuit arrangement methods of compound semiconductor integrated circuit, it is characterised in that include with Lower step：

B1：A compound semiconductor integrated circuit layout delimited in the upper surface of a compound semiconductor substrate, Wherein described compound semiconductor integrated circuit layout includes one first circuit layout and a second circuit cloth Office, wherein the region of the region of first circuit layout and the second circuit layout is in an overlapping region Overlap, one is defined as comprising around the overlapping region and the overlapping region adjacent to crossover region Adjacent domain；

B2：One first dielectric regions delimited in the upper surface of the compound semiconductor substrate, wherein described First dielectric regions are located within the neighbouring crossover region, and first dielectric regions with it is at least part of The overlapping region overlaps, wherein first dielectric of the upper surface of the compound semiconductor substrate Region beyond region is defined as one second dielectric regions；

B3：A first metal layer is formed in the region of first circuit layout；

B4：One first dielectric bumps that formation is made up of a dielectric materials are in first dielectric regions It is interior；And

B5：A second metal layer is formed in the region of the second circuit layout.

The circuit arrangement method of 24. compound semiconductor integrated circuits according to claim 23, its It is characterised by, the dielectric materials have a water absorption rate less than 5%.

The circuit arrangement method of 25. compound semiconductor integrated circuits according to claim 23, its It is characterised by, the dielectric materials include at least one selected from following group：Polybenzoxazoles PBO And benzocyclobutane BCB.

The circuit arrangement method of 26. compound semiconductor integrated circuits according to claim 23, its It is characterised by, in B4 steps, forms first dielectric bumps and comprise the following steps：

Form a low dielectric bumps in first dielectric regions and second dielectric regions simultaneously；With And

Exposure imaging or etching remove the described low dielectric bumps in second dielectric regions so that described The thickness of the described low dielectric bumps in the first dielectric regions is the thickness of first dielectric bumps, and institute The thickness for stating the described low dielectric bumps in the second dielectric regions is zero.

The circuit arrangement method of 27. compound semiconductor integrated circuits according to claim 23, its It is characterised by, in B4 steps, forms first dielectric bumps and comprise the following steps：

Exposure imaging etches first dielectric regions and the described low dielectric in second dielectric regions Projection so that the thickness of the described low dielectric bumps in first dielectric regions is that first dielectric is convex The thickness of the described low dielectric bumps in the thickness of block, and second dielectric regions is zero.

The circuit arrangement method of 28. compound semiconductor integrated circuits according to claim 23, its It is characterised by, the surrounding adjacent regions of the overlapping region include 50 μm arround the overlapping region of model Region within enclosing.

The circuit arrangement method of 29. compound semiconductor integrated circuits according to claim 23, its It is characterised by, the dielectric constant of the dielectric materials is less than 7.

The circuit layout of the 30. compound semiconductor integrated circuits according to any one of claim 1 to 29 Method, it is characterised in that form first dielectric bumps further comprising the steps of：According to described neighbouring Size needed for one impedance of the compound semiconductor integrated circuit near crossover region, determines corresponding Thickness, area and shape and low Jie in first dielectric bumps of the neighbouring crossover region One dielectric constant of electric material, to form first dielectric bumps, thereby lifts the compound and partly leads The efficiency of body integrated circuit.

The circuit layout of the 31. compound semiconductor integrated circuits according to any one of claim 1 to 29 Method, wherein further comprising the steps of：

A power amplifier is formed in the region of the power amplifier layout, wherein the power amplification Device includes a first end, one second end and one the 3rd end, wherein the first end and second end One of them is an outfan of the power amplifier, wherein the first end and the first metal layer And one of the second metal layer is electrical connected, second end and the first metal layer and institute State the wherein another of second metal layer to be electrical connected so that the first end of the power amplifier and Second end forms isolation by first dielectric bumps；And

The circuit arrangement method of 32. compound semiconductor integrated circuits according to claim 31, its It is characterised by, the power amplifier is bipolar transistor or a heteroj unction bipolar transistor, The first end is a collector, and second end is an emitter-base bandgap grading, and the 3rd end is a base stage, wherein institute State the impedance between the collector and the emitter-base bandgap grading that output impedance is the power amplifier.

The circuit arrangement method of 33. compound semiconductor integrated circuits according to claim 31, its It is characterised by, the power amplifier is a field-effect transistor, the first end is one to drain, described the Two ends are a source electrode, and the 3rd end is a grid, wherein the output impedance is the power amplifier The drain electrode and the source electrode between impedance.

The circuit layout of the 34. compound semiconductor integrated circuits according to any one of claim 1 to 29 Method, it is characterised in that further comprising the steps of：

The circuit arrangement method of 35. compound semiconductor integrated circuits according to claim 34, its It is characterised by, the main power amplifier and the bias circuit power amplifier are bipolar crystal Pipe or a heteroj unction bipolar transistor, the main power amplifier first end is a main power amplifier Collector, the end of main power amplifier second be a main power amplifier emitter-base bandgap grading, the main power amplifier 3rd end is a main power amplifier base stage, and the bias circuit power amplifier first end is a bias plasma Road power amplifier collector, the end of bias circuit power amplifier second is a bias circuit power amplification Device emitter-base bandgap grading, the end of bias circuit power amplifier the 3rd is a bias circuit power amplifier base stage, its Described in input impedance be between the bias circuit power amplifier collector and the main power amplifier base stage Impedance.

The circuit arrangement method of 36. compound semiconductor integrated circuits according to claim 34, its It is characterised by, the main power amplifier and the bias circuit power amplifier are a field-effect transistor, The main power amplifier first end is that a main power amplifier drains, the end of main power amplifier second For a main power amplifier source electrode, the end of main power amplifier the 3rd is a main power amplifier grid, The bias circuit power amplifier first end is bias circuit power amplifier drain electrode, the bias plasma The end of road power amplifier second be a bias circuit power amplifier source electrode, the bias circuit power amplification The end of device the 3rd is a bias circuit power amplifier grid, wherein the input impedance is the bias circuit Impedance between power amplifier drain electrode and the main power amplifier grid.

The circuit arrangement method of 37. compound semiconductor integrated circuits according to claim 23, its Be characterised by, between B3 steps and B4 steps also include one formed at least one on insulating barrier the step of, Insulating barrier is formed on the compound semiconductor substrate and first gold medal on wherein described at least one On category layer, and insulating barrier is formed under first dielectric bumps on described at least one.

The circuit arrangement method of the 38. compound semiconductor integrated circuits according to claim 37, its Be characterised by, constitute the material of insulating barrier on described at least include being selected from following group at least one： Silicon nitride SiN and silicon oxide sio₂。

The circuit arrangement method of 39. compound semiconductor integrated circuits according to claim 23, its Be characterised by, before B3 steps also include one formed at least insulating barrier once the step of, wherein it is described extremely Few insulating barrier once is formed on the compound semiconductor substrate, and at least once insulating barrier shape Under the first metal layer described in Cheng Yu and under first dielectric bumps.

The circuit arrangement method of the 40. compound semiconductor integrated circuits according to claim 39, its It is characterised by, constitutes that described at least once the material of insulating barrier includes being selected from least one of following group： Silicon nitride SiN and silicon oxide sio₂。

The circuit arrangement method of 41. compound semiconductor integrated circuits according to claim 23, its It is characterised by, also includes that one forms an at least protective layer in the compound semiconductor collection after B5 steps The step of on circuit.

The circuit arrangement method of 42. compound semiconductor integrated circuits according to claim 41, its It is characterised by, the material of an at least protective layer described in composition includes at least one selected from following group：It is poly- Benzoxazoles PBO, silicon nitride SiN and silicon oxide sio₂。